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2021-02-15pinctrl: mediatek: Fix trigger type setting follow for unexpected interruptHailong Fan1-2/+11
When flipping the polarity will be generated interrupt under certain circumstances, but GPIO external signal has not changed. Then, mask the interrupt before polarity setting, and clear the unexpected interrupt after trigger type setting completed. Remove mtk_eint_flip_edge: because mtk_eint_unmask already calls it. Signed-off-by: Hailong Fan <[email protected]> Reviewed-by: Nicolas Boichat <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-02-12dt-bindings: pinctrl: Group tuples in pin control propertiesGeert Uytterhoeven8-13/+13
To improve human readability and enable automatic validation, the tuples in "pinctrl-*" properties should be grouped using angle brackets. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-02-12pinctrl: nuvoton: npcm7xx: Fix alignment of table header commentJonathan Neuschäfer1-1/+1
Make it so that each column label is in the column that it is supposed to refer to. Signed-off-by: Jonathan Neuschäfer <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-02-12pinctrl: at91-pio4: fix "Prefer 'unsigned int' to bare use of 'unsigned'"Claudiu Beznea1-53/+57
Fix "Prefer 'unsigned int' to bare use of 'unsigned'" checkpatch.pl warning. Signed-off-by: Claudiu Beznea <[email protected]> Acked-by: Ludovic Desroches <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-02-12pinctrl: at91-pio4: add support for slew-rateClaudiu Beznea1-0/+27
SAMA7G5 supports slew rate configuration. Adapt the driver for this. For output switching frequencies lower than 50MHz the slew rate needs to be enabled. Since most of the pins on SAMA7G5 fall into this category enabled the slew rate by default. Signed-off-by: Claudiu Beznea <[email protected]> Acked-by: Ludovic Desroches <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-02-12dt-bindings: pinctrl: at91-pio4: add slew-rateClaudiu Beznea1-3/+5
Document slew-rate DT binding for SAMA7G5. Signed-off-by: Claudiu Beznea <[email protected]> Acked-by: Ludovic Desroches <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-02-12pinctrl: actions: Add depends on || COMPILE_TESTLinus Walleij1-3/+3
I happened to apply the v1 of the patch restriction the selection to ARM or ARM64, sorry for my sloppiness. Fixing up the mistake as I can't back the patch out now. Fixes: 5784921f7b6c ("pinctrl: actions: Add the platform dependency to drivers") Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2021-02-12pinctrl: single: set function name when adding functionDrew Fustini1-0/+1
pcs_add_function() fails to set the function name in struct pcs_function when adding a new function. As a result this line in pcs_set_mux(): dev_dbg(pcs->dev, "enabling %s function%i\n", func->name, fselector); prints "(null)" for the function: pinctrl-single 44e10800.pinmux: enabling (null) function0 pinctrl-single 44e10800.pinmux: enabling (null) function1 pinctrl-single 44e10800.pinmux: enabling (null) function2 pinctrl-single 44e10800.pinmux: enabling (null) function3 With this fix, the output is now: pinctrl-single 44e10800.pinmux: enabling pinmux-uart0-pins function0 pinctrl-single 44e10800.pinmux: enabling pinmux-mmc0-pins function1 pinctrl-single 44e10800.pinmux: enabling pinmux-i2c0-pins function2 pinctrl-single 44e10800.pinmux: enabling pinmux-mmc0-pins function3 Cc: Jason Kridner <[email protected]> Cc: Robert Nelson <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Tony Lindgren <[email protected]> Signed-off-by: Drew Fustini <[email protected]> Acked-by: Tony Lindgren <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-02-12pinctrl: qcom: Add sc8180x TLMM driverBjorn Andersson3-0/+1634
Add pinctrl driver for the sc8180x TLMM block. A noteworthy difference from previous TLMM blocks is that the registers for GPIO 177 through 189 are for some reason offset from the typical layout. Other than that the driver is same old... Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-02-12dt-bindings: pinctrl: qcom: Add sc8180x bindingBjorn Andersson1-0/+152
Add binding for the TLMM block in the Qualcomm SC8180X platform. Signed-off-by: Bjorn Andersson <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-02-12dt-bindings: pinctrl: qcom: Define common TLMM bindingBjorn Andersson1-0/+85
Several properties are shared between all TLMM bindings. By providing a common binding to define these properties each platform's binding can be reduced to just listing which of these properties should be checked for - or further specified. Reviewed-by: Vinod Koul <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-02-12pinctrl: qcom: Add SM8350 pinctrl driverVinod Koul3-0/+1659
This adds pincontrol driver for tlmm block found in SM8350 SoC This patch is based on initial code downstream by Raghavendra. Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Vinod Koul <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-02-12dt-bindings: pinctrl: qcom: Add SM8350 pinctrl bindingsVinod Koul1-0/+145
Add device tree binding Documentation details for Qualcomm SM8350 pinctrl driver. Reviewed-by: Bjorn Andersson <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Vinod Koul <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-27pinctrl: samsung: use raw_spinlock for s3c64xxChanho Park1-2/+2
Convert spin_[lock|unlock] functions of pin bank to raw_spinlock to support preempt-rt for pinctrl-s3c64xx. Below patch converted spinlock_t to raw_spinlock_t but it didn't convert the s3c64xx's spinlock. Fixes: 1f306ecbe0f6 ("pinctrl: samsung: use raw_spinlock for locking") Cc: Tomasz Figa <[email protected]> Cc: Krzysztof Kozlowski <[email protected]> Cc: Sylwester Nawrocki <[email protected]> Cc: Linus Walleij <[email protected]> Signed-off-by: Chanho Park <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-26dt-bindings: mediatek: mt8192: Fix dt_binding_check warningRobert Foss1-2/+2
Silence indentation level warning reported by dt_binding_check in order to reduce noise during routine checks. $ make dt_binding_check mt8192-mt6359-rt1015-rt5682.yaml:10:4: [warning] wrong indentation: expected 2 but found 3 (indentation) Signed-off-by: Robert Foss <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-26pinctrl: qcom: spmi-mpp: Add PM8019 compatibleKonrad Dybcio2-0/+2
PM8019 provides 6 MPPs. Add a compatible to support them. Signed-off-by: Konrad Dybcio <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-26Merge tag 'intel-pinctrl-v5.12-1' of ↵Linus Walleij3-34/+88
gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.12-1 * Enable pin control on Intel Alder Lake-P * Traverse through capabilities, convert them to features for the future use The following is an automated git shortlog grouped by driver: intel: - Convert capability list to features - Drop unnecessary check for predefined features - Split intel_pinctrl_add_padgroups() for better maintenance tigerlake: - Add Alder Lake-P ACPI ID
2021-01-26Merge tag 'v5.11-rc2' into develLinus Walleij84-284/+506
Linux 5.11-rc2
2021-01-24pinctrl: pinmux: add function selector to pinmux-functionsDrew Fustini1-1/+1
Add the function selector to the pinmux-functions debugfs output. This is an integer which is the index into the pinmux function tree. It will make it easier to correlate function name to function selector without having to count the lines in the output. Example output of "pinmux-functions": function 0: pinmux-uart0-pins, groups = [ pinmux-uart0-pins ] function 1: pinmux-uart1-pins, groups = [ pinmux-uart1-pins ] function 2: pinmux-uart2-pins, groups = [ pinmux-uart2-pins ] function 3: pinmux-mmc0-pins, groups = [ pinmux-mmc0-pins ] function 3: pinmux-mmc1-pins, groups = [ pinmux-mmc1-pins ] function 5: pinmux-i2c0-pins, groups = [ pinmux-i2c0-pins ] function 6: pinmux-i2c1-pins, groups = [ pinmux-i2c1-pins ] function 7: pinmux-i2c2-pins, groups = [ pinmux-i2c2-pins ] function 8: pinmux-pwm0-pins, groups = [ pinmux-pwm0-pins ] function 9: pinmux-pwm1-pins, groups = [ pinmux-pwm1-pins ] function 10: pinmux-adc-pins, groups = [ pinmux-adc-pins ] Cc: Jason Kridner <[email protected]> Cc: Robert Nelson <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Tony Lindgren <[email protected]> Cc: Andy Shevchenko <[email protected]> Cc: Alexandre Belloni <[email protected]> Signed-off-by: Drew Fustini <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-23pinctrl: samsung: use raw_spinlock for lockingChanho Park4-22/+22
This patch converts spin_[lock|unlock] functions of pin bank to raw_spinlock to support preempt-rt. This can avoid BUG() assertion when irqchip callbacks are triggerred. Spinlocks can be converted rt_mutex which is preemptible when we apply preempt-rt patches. According to "Documentation/driver-api/gpio/driver.rst", "Realtime considerations: a realtime compliant GPIO driver should not use spinlock_t or any sleepable APIs (like PM runtime) as part of its irqchip implementation. - spinlock_t should be replaced with raw_spinlock_t.[1] " Cc: Tomasz Figa <[email protected]> Cc: Krzysztof Kozlowski <[email protected]> Cc: Sylwester Nawrocki <[email protected]> Cc: Linus Walleij <[email protected]> Signed-off-by: Chanho Park <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-22pinctrl: clarify #pinctrl-cells for pinctrl-single,pinsDrew Fustini1-1/+1
Document that #pinctrl-cells can be 1 or 2 for pinctrl-single,pins Fixes: 27c90e5e48d0 ("ARM: dts: am33xx-l4: change #pinctrl-cells from 1 to 2") Reported-by: Emmanuel Vadot <[email protected]> Link: https://lore.kernel.org/linux-gpio/[email protected]/ Cc: Tony Lindgren <[email protected]> Signed-off-by: Drew Fustini <[email protected]> Reviewed-by: Tony Lindgren <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-22pinctrl: actions: Add the platform dependency to driversManivannan Sadhasivam1-0/+3
The Actions Semi pinctrl drivers are a mix of both ARM32 and ARM64 platforms. So let's add the correct platform dependency to avoid them being selected on the other. Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-21pinctrl: sunxi: Add support for the Allwinner H616-R pin controllerAndre Przywara3-0/+62
There are only two pins left now, used to connect to the PMIC via I2C. Signed-off-by: Andre Przywara <[email protected]> Acked-by: Maxime Ripard <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-21pinctrl: sunxi: Add support for the Allwinner H616 pin controllerAndre Przywara3-0/+554
Port A is used for an internal connection to some analogue circuitry which looks like an AC200 IP (as in the H6), though this is not mentioned in the manual. Signed-off-by: Andre Przywara <[email protected]> Acked-by: Maxime Ripard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-21dt-bindings: pinctrl: Add Allwinner H616 compatible stringsAndre Przywara1-2/+15
A new SoC, a new compatible string. Also we were too miserly with just allowing seven interrupt banks. Signed-off-by: Andre Przywara <[email protected]> Acked-by: Maxime Ripard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-21pinctrl: ingenic: Improve JZ4760 supportPaul Cercueil1-10/+28
- Add otg function and otg-vbus group. - Add lcd-8bit, lcd-16bit, lcd-18bit, lcd-generic and lcd-special groups. Change the lcd-24bit group so that it only selects the pins that aren't in the lcd-18bit and lcd-generic groups (which breaks Device Tree in theory, but there is none out there for any JZ4760 based board, yet). Remove the lcd-no-pins group which is just useless. Signed-off-by: Paul Cercueil <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-21pinctrl: remove ste u300 driverArnd Bergmann3-1118/+0
The ST-Ericsson U300 platform is getting removed, so this driver is no longer needed. Cc: Linus Walleij <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-21pinctrl: remove coh901 driverArnd Bergmann5-798/+0
The ST-Ericsson U300 platform is getting removed, so this driver is no longer needed. Cc: Linus Walleij <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-21pinctrl: remove sirf atlas/prima driversArnd Bergmann10-9610/+0
The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Cc: Barry Song <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]> Acked-by: Barry Song <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-21pinctrl: remove zte zx driverArnd Bergmann8-1674/+0
The zte zx platform is getting removed, so this driver is no longer needed. Cc: Jun Nie <[email protected]> Cc: Shawn Guo <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-18dt-bindings: pinctrl: pinctrl-microchip-sgpio: Fix indentationJonathan Neuschäfer1-2/+2
yamllint warns: ./Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml 102:10 error wrong indentation: expected 10 but found 9 (indentation) Signed-off-by: Jonathan Neuschäfer <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-18pinctrl: bcm: Simplify bool comparisonJiapeng Zhong1-1/+1
Fix the follow coccicheck warnings: ./drivers/pinctrl/bcm/pinctrl-ns2-mux.c:856:29-38: WARNING: Comparison to bool. Reported-by: Abaci Robot <[email protected]> Signed-off-by: Jiapeng Zhong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-18pinctrl: ingenic: Only support SoCs enabled in configPaul Cercueil1-12/+48
Tested on a JZ4740 system (ARCH=mips make qi_lb60_defconfig), this saves about 14 KiB, by allowing the compiler to garbage-collect all the functions and tables that correspond to SoCs that were disabled in the config. Signed-off-by: Paul Cercueil <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-18kconfig.h: Add IF_ENABLED() macroPaul Cercueil1-0/+6
IF_ENABLED(CONFIG_FOO, ptr) evaluates to (ptr) if CONFIG_FOO is set to 'y' or 'm', NULL otherwise. The (ptr) argument must be a pointer. The IF_ENABLED() macro can be very useful to help GCC drop dead code. For instance, consider the following: #ifdef CONFIG_FOO_SUSPEND static int foo_suspend(struct device *dev) { ... } #endif static struct pm_ops foo_ops = { #ifdef CONFIG_FOO_SUSPEND .suspend = foo_suspend, #endif }; While this works, the foo_suspend() macro is compiled conditionally, only when CONFIG_FOO_SUSPEND is set. This is problematic, as there could be a build bug in this function, we wouldn't have a way to know unless the config option is set. An alternative is to declare foo_suspend() always, but mark it as maybe unused: static int __maybe_unused foo_suspend(struct device *dev) { ... } static struct pm_ops foo_ops = { #ifdef CONFIG_FOO_SUSPEND .suspend = foo_suspend, #endif }; Again, this works, but the __maybe_unused attribute is required to instruct the compiler that the function may not be referenced anywhere, and is safe to remove without making a fuss about it. This makes the programmer responsible for tagging the functions that can be garbage-collected. With this patch, it is now possible to write the following: static int foo_suspend(struct device *dev) { ... } static struct pm_ops foo_ops = { .suspend = IF_ENABLED(CONFIG_FOO_SUSPEND, foo_suspend), }; The foo_suspend() function will now be automatically dropped by the compiler, and it does not require any specific attribute. Signed-off-by: Paul Cercueil <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-18Merge tag 'renesas-pinctrl-for-v5.12-tag1' of ↵Linus Walleij7-18/+4533
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.12 - Restrict debug runtime-checks to Renesas platforms, - Initial support for the R-Car V3U SoC.
2021-01-18pinctrl: sprd: Simplify bool comparisonYANG LI1-1/+1
Fix the following coccicheck warning: ./drivers/pinctrl/sprd/pinctrl-sprd.c:690:8-23: WARNING: Comparison to bool Reported-by: Abaci Robot <[email protected]> Signed-off-by: YANG LI <[email protected]> Reviewed-by: Baolin Wang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-18pinctrl: ti :iodelay: Fixed inconsistent indentingSouptick Joarder1-3/+2
Kernel test robot throws below warning -> smatch warnings: drivers/pinctrl/ti/pinctrl-ti-iodelay.c:708 ti_iodelay_pinconf_group_dbg_show() warn: inconsistent indenting Fixed the inconsistent indenting. Reported-by: kernel test robot <[email protected]> Signed-off-by: Souptick Joarder <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-14pinctrl: renesas: r8a779a0: Add TPU pins, groups and functionsUlrich Hecht1-0/+44
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on the R-Car R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-01-14pinctrl: renesas: r8a779a0: Add TMU pins, groups and functionsUlrich Hecht1-0/+65
This patch adds TMU TCLK1-4 pins, groups and functions to the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-01-14pinctrl: renesas: r8a779a0: Add QSPI pins, groups, and functionsUlrich Hecht1-0/+72
Add the QSPI0-1 pins, groups and functions to the R8A779A0 (V3U) PFC driver. Signed-off-by: Ulrich Hecht <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-01-14pinctrl: renesas: r8a779a0: Add PWM pins, groups and functionsUlrich Hecht1-0/+77
This patch adds PWM0-4 pins, groups and functions to the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-01-14pinctrl: renesas: r8a779a0: Add MSIOF pins, groups and functionsUlrich Hecht1-0/+362
This patch adds MSIOF0-5 pins, groups and functions to R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-01-14pinctrl: renesas: r8a779a0: Add MMC pins, groups and functionsUlrich Hecht1-0/+79
This patch adds MMC pins, groups and functions to R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <[email protected]> Tested-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-01-14pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and functionUlrich Hecht1-0/+62
Add pins, groups, and function for the Interrupt Controller for External Devices (INTC-EX) on the R-Car R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-01-14pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functionsUlrich Hecht1-0/+134
This patch adds HSCIF0-3 pins, groups and functions to the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <[email protected]> Tested-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-01-14pinctrl: renesas: r8a779a0: Add DU pins, groups and functionUlrich Hecht1-0/+54
This patch adds DU pins, groups and function for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-01-14pinctrl: renesas: r8a779a0: Add CANFD pins, groups and functionsUlrich Hecht1-0/+137
This patch adds CANFD 0-7 and CANFD clock pinmux support for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-01-14pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functionsUlrich Hecht1-0/+595
This patch adds groups and function for AVB PHY, LINK, MAGIC, RGMII and PTP pins for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <[email protected]> Tested-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-01-14pinctrl: renesas: r8a779a0: Add I2C pins, groups and functionsUlrich Hecht1-0/+107
This patch adds I2C0-6 pins, groups and functions to the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <[email protected]> Tested-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-01-14pinctrl: renesas: r8a779a0: Add SCIF pins, groups and functionsUlrich Hecht1-0/+156
This patch adds SCIF0, 1, 3 and 4 pins, groups and functions for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <[email protected]> Tested-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
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