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2016-03-07pinctrl: core: create nolock version of pinctrl_find_gpio_range_from_pinJoachim Eastwood2-12/+27
pinctrl_find_gpio_range_from_pin takes the pctldev->mutex but so does pinconf_pins_show and this will cause a deadlock if pinctrl_find_gpio_range_from_pin is used in .pin_config_get callback. Create a nolock version of pinctrl_find_gpio_range_from_pin to allow pin to gpio lookup to be used from pinconf_pins_show. Signed-off-by: Joachim Eastwood <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-03-07pinctrl: lpc18xx: ensure ngroups is initialized at correct placeColin Ian King1-3/+2
The initialization of ngroups is occurring at the end of the first iteration of the outer loop, which means that the assignment pins[ngroups++] = i is potentially indexing into a region outside of array pins because ngroups is not initialized. Instead, initialize ngroups in the inner loop before the first inner loop iteration. Signed-off-by: Colin Ian King <[email protected]> Reviewed-by: Joachim Eastwood <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-03-03Merge branch 'sh-pfc-for-v4.6' of ↵Linus Walleij3-1/+91
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
2016-02-26pinctrl: sh-pfc: r8a7795: Add CAN FD supportRamesh Shanmugasundaram1-0/+37
This patch adds CANFD[0-1] pinmux support to r8a7795 SoC. Signed-off-by: Ramesh Shanmugasundaram <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-02-26pinctrl: sh-pfc: r8a7795: Add CAN supportRamesh Shanmugasundaram1-0/+52
This patch adds CAN[0-1] pinmux support to r8a7795 SoC. Signed-off-by: Ramesh Shanmugasundaram <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-02-26pinctrl: sh-pfc: r8a7794: Fix GP2[29] muxingAndrey Gusakov1-0/+1
GP2[29] muxing is controlled by 2-bit IP6[3:2] field, yet only 3 values are listed instead of 4... [Sergei: fixed up the formatting, renamed, added the changelog.] Signed-off-by: Andrey Gusakov <[email protected]> Signed-off-by: Sergei Shtylyov <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-02-26pinctrl: sh-pfc: Use ARCH_RENESASSimon Horman1-1/+1
Make use of ARCH_RENESAS in place of ARCH_SHMOBILE. This is part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs. Signed-off-by: Simon Horman <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-02-25pinctrl: mediatek/7623: delete unnecessary .ownerLinus Walleij1-1/+0
This is set by the device core. Cc: John Crispin <[email protected]> Reported-by: kbuild test robot <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-25pinctrl: sunxi: Add missing H3 R_PIO binding documentationKrzysztof Adamski1-0/+1
allwinner,sun8i-h3-r-pinctrl was added by commit ba83a11104ae ("pinctrl: sunxi: Add H3 R_PIO controller support") but the patch was missing proper binding documentation. This patch fixes this issue. Signed-off-by: Krzysztof Adamski <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-19pinctrl: mediatek: Add Pinctrl/GPIO/EINT driver for MT7623John Crispin4-0/+2323
Add the driver and header files required to make pinctrl work on MediaTek MT7623. Signed-off-by: John Crispin <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-19pinctrl: mediatek: Modify pinctrl bindings for mt7623John Crispin2-0/+521
Signed-off-by: John Crispin <[email protected]> Cc: [email protected] Signed-off-by: Linus Walleij <[email protected]>
2016-02-19Merge branch 'sh-pfc-for-v4.6' of ↵Linus Walleij11-2577/+3452
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
2016-02-19pinctrl: mediatek: add input-enable and direction setting for eint resourcesBiao Huang1-0/+4
To use pin as eint, user should make sure that: 1. pin is set to right mode, this is done in .irq_request_resources implementation already. 2. direction of the pin is input, which should call GPIO API to set pin to input gpio. We add what step 2 do to .irq_request_resources so that user doesn't need call GPIO API any more when pin for eint usage. Signed-off-by: Biao Huang <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-19pinctrl: mediatek: add input-enable setting in gpio_request_enableBiao Huang1-0/+1
Since input-disable cuts off input signal of gpio, add input-enable setting in .gpio_request_enable implementation to ensure gpio function well Signed-off-by: Biao Huang <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-18pinctrl: sh-pfc: r8a7794: Add EtherAVB pin groupsSergei Shtylyov1-0/+123
Add the EtherAVB pin groups to the R8A7794 PFC driver. Based on the patches by Mitsuhiro Kimura <[email protected]>. Signed-off-by: Sergei Shtylyov <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-02-18pinctrl: sh-pfc: Rework PFC GPIO supportMagnus Damm3-41/+24
The sh-pfc pinctrl driver is currently handling SoC-specific PFC hardware blocks on ARM64, ARM and SH architectures. For older SoCs using SH cores and some 32-bit ARM SoCs the PFC hardware also provides GPIO functionality. On the majority of 32-bit ARM SoCs from Renesas and so far all ARM64 SoCs the GPIO feature is provided by separate hardware blocks. So far GPIO support in the PFC driver has been compiled-in for the majority of the SoCs, but with this patch applied the SoCs with PFC support may select from one of the following: - CONFIG_PINCTRL_SH_PFC - Used if PFC lacks GPIO hardware - CONFIG_PINCTRL_SH_PFC_GPIO - Used if PFC includes GPIO support This patch results in the following changes: - The GPIO functionality is only compiled-in on relevant SoCs - The number of lines of code is reduced Build tested using the following configurations: - r8a7795 -> CONFIG_PINCTRL_SH_PFC_GPIO=n -> OK (ARM64) - r8a7790 -> CONFIG_PINCTRL_SH_PFC_GPIO=n -> OK (ARM) - r8a7790 + r8a7740 -> CONFIG_PINCTRL_SH_PFC_GPIO=y -> OK (ARM) - r8a7740 -> CONFIG_PINCTRL_SH_PFC_GPIO=y -> OK (ARM) - sh7751 -> CONFIG_PINCTRL_SH_PFC=n -> OK (SH rts7751r2d1) - sh7724 -> CONFIG_PINCTRL_SH_PFC_GPIO=y -> OK (SH ecovec24) Signed-off-by: Magnus Damm <[email protected]> Acked-by: Laurent Pinchart <[email protected]> [geert: s/def_bool n/bool/] Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-02-18pinctrl: sh-pfc: r8a7795: Add PWM supportTakeshi Kihara1-0/+153
This patch adds PWM[0-6] pinmux support to r8a7795 SoC. Signed-off-by: Takeshi Kihara <[email protected]> [uli: adapted to mainline PFC driver] Signed-off-by: Ulrich Hecht <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-02-18pinctrl: sh-pfc: r8a7795: Add support for INTC-EX IRQ pinsMagnus Damm1-0/+60
Most pins on the r8a7795 SoC can be configured in GPIO mode for interrupt and GPIO functionality, while a couple of them can also be routed to the INTC-EX hardware block (formerly known as IRQC). On r8a7795 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and this patch adds support for them to the PFC driver as "intc_ex_irqN". Tested on r8a7795 Salvator-X with an external loop back adapter on EXIO_D that connects pin 9 (IRQ2/GP2_02) and pin 26 (ExA22/GP2_06). Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-02-18pinctrl: sh-pfc: r8a7794: Add audio clock pin groupsRyo Kataoka1-0/+122
Add the audio clock pin groups to the R8A7794 PFC driver. [Sergei: fixed pin group names to reflect the reality, fixed pin names in the comments to *_pins[], lowercased the separator comment, resolved rejects, added the changelog, renamed the patch.] Signed-off-by: Ryo Kataoka <[email protected]> Signed-off-by: Sergei Shtylyov <[email protected]> Acked-by: Linus Walleij <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-02-18pinctrl: sh-pfc: r8a7794: Add SSI pin groupsRyo Kataoka1-2/+313
Add the SSI pin groups to the R8A7794 PFC driver. [Sergei: fixed inconsistent alternate pin group naming, split SSI5/6 pin groups into data/control ones, moved SSI7 data B group to its proper place, fixed pin names in the comments to *_pins[], extended Cogent Embedded's copyright, added the changelog, renamed the patch.] Signed-off-by: Ryo Kataoka <[email protected]> Signed-off-by: Sergei Shtylyov <[email protected]> Acked-by: Linus Walleij <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-02-17pinctrl: mtk2701: skip setting .ownerLinus Walleij1-1/+0
The device core will handle this and Coccinelle complains. Signed-off-by: Linus Walleij <[email protected]>
2016-02-16pinctrl: qcom: ipq4019: Add IPQ4019 pinctrl supportVaradarajan Narayanan4-0/+536
Add pinctrl driver support for IPQ4019 platform Signed-off-by: Sricharan R <[email protected]> Signed-off-by: Mathieu Olivari <[email protected]> Signed-off-by: Varadarajan Narayanan <[email protected]> Signed-off-by: Matthew McClintock <[email protected]> Acked-by: Rob Herring <[email protected]> Reviewed-by: Andy Gross <[email protected]> Acked-by: Bjorn Andersson <[email protected]> [Dropped .owner assignment] Signed-off-by: Linus Walleij <[email protected]>
2016-02-16pinctrl: mediatek: fix handling return value of mtk_pmx_find_gpio_modeAndrzej Hajda1-1/+1
The function can return negative values, so its result should be assigned to signed variable. The problem has been detected using coccinelle semantic patch scripts/coccinelle/tests/assign_signed_to_unsigned.cocci. Fixes: 59ee9c9 ('pinctrl: mediatek: Add gpio_request_enable support') Signed-off-by: Andrzej Hajda <[email protected]> Acked-by: Hongzhou Yang <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-16pinctrl: Turn AMD support to tristateJean Delvare1-1/+1
The pinctrl-amd driver builds just fine as a module so give users this option. Signed-off-by: Jean Delvare <[email protected]> Cc: Linus Walleij <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-15pinctrl: coh901: fix initconst annotationArnd Bergmann1-1/+1
Clang correctly points out that the section attribute for u300_gpio_confdata is in the wrong place: drivers/pinctrl/pinctrl-coh901.c:130:37: error: '__section__' attribute only applies to functions and global variables This moves it from the type name to the variable, so it actually gets discarded. Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-15pinctrl: Fix return value check in amd_gpio_probe()Wei Yongjun1-2/+2
In case of error, the function devm_ioremap_nocache() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-15pinctrl: zynq: fix typo in group name for qspi1Helmut Buchsbaum1-1/+1
Due to a typo Zynq pin controller does not set pin function of qspi1 when using function qspi1. So pin group for qspi1 has to be renamed to "qspi1_0_grp" as outlined in the corresponding bindings documentation. This also removes kernel message: zynq-pinctrl 700.pinctrl: invalid group "qspi1_0_grp" for function "qspi1" Signed-off-by: Helmut Buchsbaum <[email protected]> Acked-by: Sören Brinkmann <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-13pinctrl: mediatek: guard sub-directory with CONFIG_PINCTRL_MTKMasahiro Yamada3-13/+13
CONFIG_PINCTRL_MTK is more suitable than CONFIG_ARCH_MEDIATEK to guard the drivers/pinctrl/mediatek/ directory. (I renamed CONFIG_PINCTRL_MTK_COMMON to CONFIG_PINCTRL_MTK.) This allows COMPILE_TEST to descend into drivers/pinctrl/mediatek without CONFIG_ARCH_MEDIATEK define. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-12pinctrl: intel: Remove unneeded header includesJean Delvare1-4/+0
pinctrl-intel doesn't use anything from <linux/init.h>, <linux/acpi.h>, <linux/gpio.h> or <linux/pm.h>, so it should not include these header files. Signed-off-by: Jean Delvare <[email protected]> Cc: Heikki Krogerus <[email protected]> Acked-by: Mika Westerberg <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-11pinctrl: sunxi: Use pin number when calling sunxi_pmx_setKrzysztof Adamski1-2/+3
sunxi_pmx_set accepts pin number and then calculates offset by subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand, gets offset so we have to convert it to pin number so we won't get negative value in sunxi_pmx_set. This was only used on A10 so far, where there is only one GPIO chip with pin_base set to 0 so it didn't matter. However H3 also requires this workaround but have two pinmux sections, triggering problem for PL port. Signed-off-by: Krzysztof Adamski <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-11pinctrl: sunxi: Add H3 R_PIO controller supportKrzysztof Adamski3-0/+111
H3 has additional PIO controller similar to what we can find on A23. It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350. Signed-off-by: Krzysztof Adamski <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-10pinctrl: rockchip: add support for the rk3399David Wu2-15/+356
The pinctrl of rk3399 is much different from other's, especially the 3bits of drive strength. Signed-off-by: David Wu <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-10pinctrl: uniphier: add COMPILE_TEST optionMasahiro Yamada1-1/+1
Add COMPILE_TEST for the compilation test coverage. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-09Merge branch 'devel-mt2701' into develLinus Walleij7-1/+3712
2016-02-09pinctrl: stm32: Fix compile testing selectionMaxime Coquelin1-1/+1
While selecting the driver for compile testing seemed possible, the driver was not compiled because the driver directory was only added if ARCH_STM32 was selected. This patch now makes the pinctrl Makefile to add stm32 directory if PINCTRL_STM32 is selected. Signed-off-by: Maxime Coquelin <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-09pinctrl: stm32: Remove dependency with DT bindings header filesMaxime Coquelin2-2/+8
Some macros where defined in DT bindings headers, whereas only used in the driver. This patch moves these macros to the driver side. Signed-off-by: Maxime Coquelin <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-08pinctrl: sh-pfc: r8a7795: Add USB2.0 host supportTakeshi Kihara1-0/+43
This patch adds USB[0-2] (USB2.0 host) pinmux support to r8a7795 SoC. Signed-off-by: Takeshi Kihara <[email protected]> Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-02-08pinctrl: sh-pfc: r8a7795: Remove bits SEL_VSP_1 and SEL_VSP_0Geert Uytterhoeven1-3/+3
Cfr. Manual Errata for Rev 0.50 of the R-Car Gen3 datasheet. This has no user-visible impact, as the definitions were not really used. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Linus Walleij <[email protected]>
2016-02-08pinctrl: sh-pfc: r8a7795: Rename SSI_{WS,SCK}0129 to SSI_{WS,SCK}01239Geert Uytterhoeven1-7/+7
Cfr. Manual Errata for Rev 0.50 of the R-Car Gen3 datasheet. This has no user-visible impact, as the string used for configuration ("ssi01239_ctrl") was already correct. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Linus Walleij <[email protected]>
2016-02-08pinctrl: sh-pfc: Rename PINMUX_IPSR_DATA() to PINMUX_IPSR_GPSR()Geert Uytterhoeven8-2518/+2518
This macro describes a pinmux configuration that needs configuration in both a Peripheral Function Select Register (IPSR) and in a GPIO/Peripheral Function Select Register 1 (GPSR). Reflect that in the macro name for clarity. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Laurent Pinchart <[email protected]>
2016-02-08pinctrl: sh-pfc: Improve pinmux macros documentationGeert Uytterhoeven1-8/+88
Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Linus Walleij <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]>
2016-02-05pinctrl: pinctrl-pic32: Add PIC32 pin control driverJoshua Henderson4-0/+2471
Add a driver for the pin controller present on the Microchip PIC32 including the specific variant PIC32MZDA. This driver provides pinmux and pinconfig operations as well as GPIO and IRQ chips for the GPIO banks. Signed-off-by: Joshua Henderson <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: Linus Walleij <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-05pinctrl: Add DT bindings for PIC32 pin control and GPIOJoshua Henderson2-0/+109
Document the devicetree bindings for PINCTRL and GPIO found on Microchip PIC32 class devices. Signed-off-by: Joshua Henderson <[email protected]> Cc: Ralf Baechle <[email protected]> Acked-by: Rob Herring <[email protected]> Cc: Linus Walleij <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-05pinctrl: stm32: fix compile error and modernizeLinus Walleij1-9/+6
- Fix the dev->parent assignment compile error - Use gpiochip_get_data() to get the data pointer for the banks Cc: Maxime Coquelin <[email protected]> Cc: Patrice Chotard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-05pinctrl: tegra: move Tegra pinctrl drivers to sub-directoryMasahiro Yamada12-42/+43
Tegra has several pinctrl drivers. Now it is reasonable enough to move them into drivers/pinctrl/tegra/. Signed-off-by: Masahiro Yamada <[email protected]> Acked-by: Thierry Reding <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-05pinctrl: mediatek: Add gpio_request_enable supportBiao Huang1-0/+36
Implement the .gpio_request_enable() callbacks in struct pinmux_ops in mediatek pinctrl driver. Make sure that when gpio_request is called, GPIO on the pin is enabled. Signed-off-by: Biao Huang <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-01-28pinctrl: sunxi: guard sub-directory with CONFIG_PINCTRL_SUNXIMasahiro Yamada3-17/+17
CONFIG_PINCTRL_SUNXI is more suitable than CONFIG_ARCH_SUNXI to guard the drivers/pinctrl/sunxi/ directory. (I renamed CONFIG_PINCTRL_SUNXI_COMMON to CONFIG_PINCTRL_SUNXI.) Signed-off-by: Masahiro Yamada <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-01-28pinctrl: nomadik: stn8815 CLCD alternate functionsLinus Walleij1-0/+7
The STn8815 has 22 dedicated pins for CLCD with up to 16 bits in parallel, but pins 32 thru 39 can be used for an additional CLCD signal lines 16 thru 23. Signed-off-by: Linus Walleij <[email protected]>
2016-01-28pinctrl: pxa: guard sub-directory with CONFIG_PINCTRL_PXAMasahiro Yamada1-1/+1
CONFIG_PINCTRL_PXA is more suitable than CONFIG_ARCH_PXA to guard the drivers/pinctrl/pxa/ directory. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-01-28pinctrl: mediatek: Add Pinctrl/GPIO/EINT driver for mt2701Biao Huang6-1/+2941
Add mt2701 support using mediatek common pinctrl driver. MT2701 have some special pins need an extra setting register than other ICs, so adding this support to common code. Signed-off-by: Biao Huang <[email protected]> Acked-by: Yingjoe Chen <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
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