aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2020-04-22drm/amd/powerplay: properly set the dpm_enabled stateEvan Quan5-66/+216
On the ASIC powered down(in baco or system suspend), the dpm_enabled will be set as false. Then all access (e.g. df state setting issued on RAS error event) to SMU will be blocked. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/powerplay: correct i2c eeprom init/fini sequenceEvan Quan3-15/+17
As data transfer may starts immediately after i2c eeprom init completed. Thus i2c eeprom should be initialized after SMU ready. And i2c data transfer should be prohibited when SMU down. That is the i2c eeprom fini sequence needs to be updated also. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/powerplay: bump the NAVI10 smu-driver if versionEvan Quan1-1/+1
To fit the latest SMC firmware 42.53 and eliminate the warning on driver loading. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/powerplay: revise the way to retrieve the board parametersEvan Quan2-71/+130
It can support different NV1x ASIC better. And this can guard no member got missing. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amdgpu: fix the hw hang during perform system reboot and resetPrike Liang1-0/+2
The system reboot failed as some IP blocks enter power gate before perform hw resource destory. Meanwhile use unify interface to set device CGPG to ungate state can simplify the amdgpu poweroff or reset ungate guard. Fixes: 487eca11a321ef ("drm/amdgpu: fix gfx hang during suspend with video playback (v2)") Signed-off-by: Prike Liang <[email protected]> Tested-by: Mengbing Wang <[email protected]> Tested-by: Paul Menzel <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: remove redundant assignment to variable dp_ref_clk_khzColin Ian King1-1/+1
The variable dp_ref_clk_khz is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/radeon: remove defined but not used variables in ci_dpm.cJason Yan1-14/+0
Fix the following gcc warning: drivers/gpu/drm/radeon/ci_dpm.c:82:36: warning: ‘defaults_saturn_pro’ defined but not used [-Wunused-const-variable=] static const struct ci_pt_defaults defaults_saturn_pro = ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/radeon/ci_dpm.c:68:36: warning: ‘defaults_bonaire_pro’ defined but not used [-Wunused-const-variable=] static const struct ci_pt_defaults defaults_bonaire_pro = ^~~~~~~~~~~~~~~~~~~~ Reported-by: Hulk Robot <[email protected]> Signed-off-by: Jason Yan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/radeon: remove defined but not used 'dte_data_tahiti_le'Jason Yan1-18/+0
Fix the following gcc warning: drivers/gpu/drm/radeon/si_dpm.c:255:33: warning: ‘dte_data_tahiti_le’ defined but not used [-Wunused-const-variable=] static const struct si_dte_data dte_data_tahiti_le = Reported-by: Hulk Robot <[email protected]> Signed-off-by: Jason Yan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amdgpu: remove dead code in si_dpm.cJason Yan1-20/+0
This code is dead, let's remove it. Reported-by: Hulk Robot <[email protected]> Signed-off-by: Jason Yan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amd/amdgpu: remove hardcoded module name in printsAurabindo Pillai6-9/+9
Let format prefixes take care of printing the module name through pr_fmt and dev_fmt definitions. Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amd/amdgpu: add print prefix for dev_* variantsAurabindo Pillai1-0/+6
Define dev_fmt macro for informative print messages Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amd/amdgpu: add prefix for pr_* printsAurabindo Pillai1-0/+6
amdgpu uses lots of pr_* calls for printing error messages. With this prefix, errors shall be more obvious to the end use regarding its origin, and may help debugging. Prefix format: [xxx.xxxxx] amdgpu: ... Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amd/display: code clean up in dce80_hw_sequencer.cJason Yan1-28/+0
Fix the following gcc warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_hw_sequencer.c:43:46: warning: ‘reg_offsets’ defined but not used [-Wunused-const-variable=] static const struct dce80_hw_seq_reg_offsets reg_offsets[] = { ^~~~~~~~~~~ Reported-by: Hulk Robot <[email protected]> Signed-off-by: Jason Yan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amdgpu/ring: simplify scheduler setup logicAlex Deucher1-3/+1
Set up a GPU scheduler based on the ring flag rather than the ring type. Reviewed-by: Christian König <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amdgpu/kiq: add no_scheduler flag to KIQAlex Deucher1-0/+1
We don't want a GPU scheduler for this ring. Reviewed-by: Christian König <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amdgpu/ring: add no_scheduler flagAlex Deucher2-1/+3
This allows IPs to flag whether a specific ring requires a GPU scheduler or not. E.g., sometimes instances of an IP are asymmetric and have different capabilities. Reviewed-by: Christian König <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amdgpu/powerplay: get SMC FW size to a flexible wayLikun Gao2-2/+3
Get SMC fw size before backdoor loading instead of giving an certain value, as it may different for different ASIC. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Reviewed-by: Evan Quan <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amdgpu: fix wrong vram lost counter increment V2Evan Quan5-14/+18
Vram lost counter is wrongly increased by two during baco reset. V2: assumed vram lost for mode1 reset on all ASICs Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amdgpu: replace DRM prefix with PCI device info for GFX RASGuchun Chen1-20/+27
Prefix RAS message printing in GFX IP with PCI device info, which assists the debug in multiple GPU case. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amdgpu: resume kiq access debugfsYintian Tao2-3/+11
If there is no GPU hang, user still can access debugfs through kiq. Signed-off-by: Yintian Tao <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amdgpu: refine ras related message printGuchun Chen3-29/+48
Prefix ras related kernel message logging with PCI device info by replacing DRM_INFO/WARN/ERROR with dev_info/warn/err. This can clearly tell user about GPU device information where ras is. And add some other ras message printing to make it more clear and friendly as well. Suggested-by: Hawking Zhang <[email protected]> Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amdgpu: add uncorrectable error count print in UMC ecc irq cbGuchun Chen1-0/+3
Uncorrectable error count printing is missed when issuing UMC UE injection. When going to the error count log function in GPU recover work thread, there is no chance to get correct error count value by last error injection and print, because the error status register is automatically cleared after reading in UMC ecc irq callback. So add such message printing in UMC ecc irq cb to be consistent with other RAS error interrupt cases. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amd/powerplay: force the trim of the mclk dpm_levels if OD is enabledSergei Lopatin1-1/+4
Should prevent flicker if PP_OVERDRIVE_MASK is set. bug: https://bugs.freedesktop.org/show_bug.cgi?id=102646 bug: https://bugs.freedesktop.org/show_bug.cgi?id=108941 bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1088 bug: https://gitlab.freedesktop.org/drm/amd/-/issues/628 Signed-off-by: Sergei Lopatin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amd/display: Change "error" to "dc_log" at amdgpu_dm dpcd reading stageZhan Liu1-1/+1
[Why] If reading dpcd happens ahead of hw initialization, then aconnector is NULL at this point. This is expected, so there is no need to output an error (which will spam dmesg.log) [How] Change type of message from "error" to "DC_LOG_DC". Signed-off-by: Zhan Liu <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Zhan Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-13drm/amdgpu: restrict debugfs register access under SR-IOVYintian Tao4-6/+106
Under bare metal, there is no more else to take care of the GPU register access through MMIO. Under Virtualization, to access GPU register is implemented through KIQ during run-time due to world-switch. Therefore, under SR-IOV user can only access debugfs to r/w GPU registers when meets all three conditions below. - amdgpu_gpu_recovery=0 - TDR happened - in_gpu_reset=0 v2: merge amdgpu_virt_can_access_debugfs() into amdgpu_virt_enable_access_debugfs() v3: drop ret variable in amdgpu_virt_enable_access_debugfs() and directly return result Signed-off-by: Yintian Tao <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: increased atom cmd timeoutJohn Clements1-2/+5
added macro to define timeout Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/powerplay: unload mp1 for Arcturus RAS baco resetEvan Quan1-0/+6
This sequence is recommended by PMFW team for the baco reset with PMFW reloaded. And it seems able to address the random failure seen on Arcturus. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09amdgpu_kms: Remove unnecessary condition checkAurabindo Pillai1-6/+4
Execution will only reach here if the asserted condition is true. Hence there is no need for the additional check. Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu/display: fix warning when compiling without debugfsAlex Deucher1-1/+1
fixes unused variable warning. Reported-by: Eric Biggers <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: unify fw_write_wait for new gfx9 asicsAaron Liu1-0/+2
Make the fw_write_wait default case true since presumably all new gfx9 asics will have updated firmware. That is using unique WAIT_REG_MEM packet with opration=1. Signed-off-by: Aaron Liu <[email protected]> Tested-by: Aaron Liu <[email protected]> Tested-by: Yuxian Dai <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: support access regs outside of mmio barHawking Zhang3-39/+28
add indirect access support to registers outside of mmio bar. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: retire AMDGPU_REGS_KIQ flagHawking Zhang2-5/+4
all the register access through kiq is redirected to amdgpu_kiq_rreg/amdgpu_kiq_wreg Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: retire RREG32_IDX/WREG32_IDXHawking Zhang2-6/+2
those are not needed anymore Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: retire indirect mmio reg support from cgsHawking Zhang2-5/+4
not needed anymore Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: replace indirect mmio access in non-dc code pathHawking Zhang4-22/+22
all the mmCUR_CONTROL instances are in mmr range and can be accessd directly by using RREG32/WREG32 Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: remove inproper workaround for vega10Hawking Zhang2-18/+0
the workaround is not needed for soc15 ASICs except for vega10. it is even not needed with latest vega10 vbios. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/powerplay: error out on forcing clock setting not supportedEvan Quan1-1/+46
For Arcturus, forcing clock to some specific level is not supported with 54.18 and onwards SMU firmware. As according to firmware team, they adopt new gfx dpm tuned parameters which can cover all the use case in a much smooth way. Thus setting through driver interface is not needed and maybe do a disservice. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: fix gfx hang during suspend with video playback (v2)Prike Liang1-2/+3
The system will be hang up during S3 suspend because of SMU is pending for GC not respose the register CP_HQD_ACTIVE access request.This issue root cause of accessing the GC register under enter GFX CGGPG and can be fixed by disable GFX CGPG before perform suspend. v2: Use disable the GFX CGPG instead of RLC safe mode guard. Signed-off-by: Prike Liang <[email protected]> Tested-by: Mengbing Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: add HDCP caps debugfsBhawanpreet Lakha3-0/+112
Add debugfs to get HDCP capability. This is also useful for kms_content_protection igt test. Use: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: query hdcp capability during link detectBhawanpreet Lakha5-0/+196
[Why] Query the hdcp caps of a link, it is useful and can be reported to the user [How] Create a query function and call it during link detect Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amdgpu: Re-enable FRU check for most models v5Kent Russell1-3/+13
There is at least 1 VG20 DID that does not have an FRU, and trying to read that will cause a hang. For now, explicitly support reading the FRU for Arcturus and for the WKS VG20 DIDs, and skip for everything else. This re-enables serial number reporting for server cards v2: Add ASIC check v3: Don't default to true for pre-VG20 v4: Use DID instead of parsing the VBIOS v5: Sqaush in overflow warning fix Signed-off-by: Kent Russell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: 3.2.80Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: Make DMCUB bss/data firmware blob optionalNicholas Kazlauskas4-16/+41
[Why] By moving everything out of .data into the other regions we can drop the requirement for the second blob and unify it all into the inst/const blob. [How] We need to still support the blob being there and not being there for backwards compatibility. Look for the DMCUB metadata section in the end of the inst/const blob instead of bss/data is missing. Clear CW2 if we don't have the data blob so we don't hang when transitioning between data blob/blobless firmwares. Don't memcpy the blob into CW2 region if it doesn't exist. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: determine USB C DP2 mode only when USB DP Alt is enabledWenjing Liu10-64/+101
[why] When display is connected with a native DP port, DP2 mode register value is a don't care. Driver mistakenly reduce max supported lane count to 2 lane based on the don't care value. [how] Add additional check only if USB C DP alt mode is enabled, we will determine max lane count supported based on current mode. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: Check for null fclk voltage when parsing clock tableMichael Strauss1-1/+1
[WHY] In cases where a clock table is malformed such that fclk entries have frequencies but not voltages listed, we don't catch the error and set clocks to 0 instead of using hardcoded values as we should. [HOW] Add check for clock tables fclk entry's voltage as well Signed-off-by: Michael Strauss <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: Acknowledge wm_optimized_requiredJoshua Aberback1-2/+3
[Why] If dc->clk_mgr->funcs->are_clock_states_equal is set, then wm_optimized_required is never checked. In that case, when going from a higher mode to a lower mode, wm_optimized_required remains true until the next mode change. [How] - move from else-if to unconditional or Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Jun Lei <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: Update DRAM watermark before checking to update TTUJaehyun Chung1-1/+2
[Why] In most cases, DRAM watermark is large enough that the result of the condition to increase TTU doesn't change after DRAM watermark is increased. However, there is are cases where the condition fails and becomes true after DRAM watermark is increased. This results in minTTU < DRAM watermarks which leads to PSR hang since p-state is requested but not allowed. [How] Check whether to update TTU after DRAM watermark is updated. Signed-off-by: Jaehyun Chung <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: Avoid create MST prop after registrationJerry (Fangzhi) Zuo2-3/+13
[Why] Prop are created at boot stage, and not allowed to create new prop after device registration. [How] Reuse the connector property from SST if exist. Signed-off-by: Jerry (Fangzhi) Zuo <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: Make cursor source translation adjustment optionalNicholas Kazlauskas4-4/+19
[Why] In some usecases, like tiled display, the stream and plane configuration can be setup in a way where the caller expects DAL to perform the clipping, eg: P0: src_rect(0, 0, w, h) dst_rect(0, 0, w, h) P1: src_rect(w, 0, w, h) dst_rect(0, 0, w, h) Cursor is enabled on both streams with the same position. This can result in double cursor on tiled display, even though this behavior is technically correct from the DC interface point of view. We need a mechanism to control this dynamically. [How] This is something that should live in the DM layer based on detection of the specified configuration but it's not something that we really have enough information to deal with today. Add a flag to the cursor position state that specifies whether we want DC to do the translation or not and make it opt-in and let the DM decide when to do it. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-09drm/amd/display: Revert to old formula in set_vtg_paramsAlvin Lee1-2/+4
[Why] New formula + cursor change causing underflow on certain configs [How] Rever to old formula Signed-off-by: Alvin Lee <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.