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2019-10-28drm/tegra: vic: Use common IOMMU attach/detach codeThierry Reding1-19/+8
Reuse common code to attach to or detach from an IOMMU domain. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: vic: Inherit DMA mask from host1xThierry Reding1-0/+7
VIC, just like all other host1x clients, has the same addressing range as its parent host1x device. Inherit the DMA mask to reflect that. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: vic: Skip stream ID programming without IOMMUThierry Reding1-3/+5
If VIC is not behind an IOMMU, don't touch any of the registers related to stream ID programming. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: Use DRM_DEBUG_DRIVER for driver messagesThierry Reding1-4/+4
The driver-specific messages should use the DRM_UT_DRIVER category so that they can be properly filtered. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: Inherit device DMA parameters from host1xThierry Reding2-0/+18
The display controllers and VIC don't have any limitations on the DMA segment size. Inherit the DMA parameters from the parent device, which also doesn't have any such limitations. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28gpu: host1x: Make host1x_cdma_wait_pushbuffer_space() staticBen Dooks (Codethink)1-3/+3
The host1x_cdma_wait_pushbuffer_space() function is not declared or directly called from outside the file it is in, so make it static. Fixes the following sparse warning: drivers/gpu/host1x/cdma.c:235:5: warning: symbol 'host1x_cdma_wait_pushbuffer_space' was not declared. Should it be static? Signed-off-by: Ben Dooks <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2019-10-28gpu: host1x: Request channels for clients, not devicesThierry Reding6-10/+12
A struct device doesn't carry much information that a channel might be interested in, but the client very much does. Request channels for the clients rather than their parent devices and store a pointer to them in order to have that information available when needed. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28gpu: host1x: Explicitly initialize host1x_info structuresThierry Reding1-0/+12
It's technically not required to explicitly initialize the fields that will be zero by default, but it's easier to read these structures if they are all initialized uniformly. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28gpu: host1x: Remove gratuitous blank lineThierry Reding1-1/+0
Signed-off-by: Thierry Reding <[email protected]>
2019-10-28gpu: host1x: Do not limit DMA segment sizeThierry Reding3-1/+6
host1x nor any its clients have any limitations on the DMA segment size, so don't pretend that they do. Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/todo: Clarify situation around fbdev and defioThomas Zimmermann1-4/+4
The TODO item is misleading and makes it seem as if fbdev emulation cannot be used with SHMEM. Rephrase the text to describe the current situation more correctly. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Noralf Trønnes <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-28drm/fb-helper: Remove drm_fb_helper_defio_init() and update docsThomas Zimmermann2-49/+13
There are no users of drm_fb_helper_defio_init(), so we can remove it. The documentation around defio support is a bit misleading and should mention compatibility issues with SHMEM helpers. Clarify this. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Noralf Trønnes <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-27drm/i915/rps: Flip interpretation of ips fmin/fmax to max rpsChris Wilson1-3/+5
ips uses clock delays as opposed to rps frequency bins. To fit the delays into the same rps calculations, we need to invert the ips delays. Fixes: 3e7abf814193 ("drm/i915: Extract GT render power state management") Signed-off-by: Chris Wilson <[email protected]> Cc: Andi Shyti <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-27drm/i915: Put future HW and their uAPIs under STAGING & BROKENChris Wilson3-0/+28
We would like some freedom to break the user API/ABI for future HW but yet still expose the driver for upstream development on that HW. Currently, we have the i915.force_probe module parameter to avoid binding to HW while the driver is under development, but that is still a little too soft with respect to the stringent no-regression rules if we also plan to be redesigning the uAPI to go along with the new HW. To allow the uAPI to be changed during development, only expose that API and in development HW under STAGING (and BROKEN). Hopefully, making it explicit that such interfaces to that HW are under development and not to be blindly enabled by distributions. Signed-off-by: Chris Wilson <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Dave Airlie <[email protected]> Acked-by: Dave Airlie <[email protected]> Acked-by: Jani Nikula <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-26drm/i915: Split memory_region initialisation into its own fileChris Wilson6-74/+75
Pull the memory region bookkeeping into its file. Let's start clean and see how long it lasts! Signed-off-by: Chris Wilson <[email protected]> Cc: Matthew Auld <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-26drm/i915: Extract the GuC interrupt handlersAndi Shyti3-102/+89
Pull the GuC interrupt handlers out of i915_irq.c. They now use the GT interrupt facilities rather than the central dispatch. Based on a patch by Chris Wilson. Signed-off-by: Andi Shyti <[email protected]> Cc: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-26drm/i915: Extract GT render power state managementAndi Shyti24-2310/+2126
i915_irq.c is large. One reason for this is that has a large chunk of the GT render power management stashed away in it. Extract that logic out of i915_irq.c and intel_pm.c and put it under one roof. Based on a patch by Chris Wilson. Signed-off-by: Andi Shyti <[email protected]> Cc: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-26drm/i915/tgl: Adjust the location of RING_MI_MODE in the context imageChris Wilson2-3/+87
The location of RING_MI_MODE (used to stop the ring across resets) moved for Tigerlake. Fixup the new location and include a selftest to verify the location in the default context image. Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Acked-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-26drm/i915: Encapsulate kconfig constant values inside boolean predicatesChris Wilson5-5/+19
Avoid angering clang and smatch by using a constant value in a '&&' test, by forcing that constant value into a boolean. E.g., drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:159:13: warning: use of logical '&&' with constant operand [-Wconstant-logical-operand] if (!delay && CONFIG_DRM_I915_PREEMPT_TIMEOUT) { ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Reported-by: kbuild test robot <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: Nathan Chancellor <[email protected]> Cc: Nick Desaulniers <[email protected]> Cc: Jani Nikula <[email protected]> Reviewed-by: Nathan Chancellor <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915/tc: Clear DKL_TX_PMD_LANE_SUS before program voltage swingJosé Roberto de Souza2-0/+8
This sequence was recently added to fix internal HW sequences to reset TC ports. HSDES: 1507287614 HSDES: 14010071447 BSpec: 49292 Reviewed-by: Lucas De Marchi <[email protected]> Cc: Lucas De Marchi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915/pmu: Initialise the spinlock before registeringChris Wilson1-18/+19
As the GT may be running in parallel with the module initialisation code, we may enter i915_pmu_gt_parked() as we are executing i915_pmu_register(). We have to init the spinlock before we mark pmu.event_init so that it is available for use by i915_pmu_gt_parked() (which may run as soon as event_init is set). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112127 Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915/selftests/blt: add some kthreads into the mixMatthew Auld1-25/+153
We can be more aggressive in our testing by launching a number of kthreads, where each is submitting its own copy or fill batches on a set of random sized objects. Also since the underlying fill and copy batches can be pre-empted mid-batch(for particularly large objects), throw in a random mixture of ctx priorities per thread to make pre-emption a possibility. Signed-off-by: Matthew Auld <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915/selftests: add sanity selftest for huge-GTT-pagesMatthew Auld1-0/+99
Now that for all the relevant backends we do randomised testing, we need to make sure we still sanity check the obvious cases that might blow up, such that introducing a temporary regression is less likely. Also rather than do this for every backend, just limit to our two memory types: system and local. Suggested-by: Chris Wilson <[email protected]> Signed-off-by: Matthew Auld <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915/selftests: prefer random sizes for the huge-GTT-page smoke testsMatthew Auld1-149/+80
Ditch the dubious static list of sizes to enumerate, in favour of choosing a random size within the limits of each backing store. With repeated CI runs this should give us a wider range of object sizes, and in turn more page-size combinations, while using less machine time. Signed-off-by: Matthew Auld <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915/selftests: extend coverage to include LMEM huge-pagesMatthew Auld1-1/+122
Add LMEM objects to list of backends we test for huge-GTT-pages. Signed-off-by: Matthew Auld <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915/selftests: add write-dword test for LMEMMatthew Auld1-0/+166
Simple test writing to dwords across an object, using various engines in a randomized order, checking that our writes land from the cpu. Signed-off-by: Matthew Auld <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915/lmem: support kernel mappingAbdiel Janulgue5-18/+192
We can create LMEM objects, but we also need to support mapping them into kernel space for internal use. Signed-off-by: Abdiel Janulgue <[email protected]> Signed-off-by: Matthew Auld <[email protected]> Signed-off-by: Steve Hampson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915: setup io-mapping for LMEMAbdiel Janulgue1-2/+26
Create an io-mapping to describe the CPU aperture for lmem. Signed-off-by: Abdiel Janulgue <[email protected]> Cc: Matthew Auld <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915: support creating LMEM objectsMatthew Auld8-0/+159
We currently define LMEM, or local memory, as just another memory region, like system memory or stolen, which we can expose to userspace and can be mapped to the CPU via some BAR. Signed-off-by: Matthew Auld <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Abdiel Janulgue <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915: split gen11_irq_handler to make it shareableLucas De Marchi1-5/+14
Split gen11_irq_handler() to receive as parameter the function pointers. This allows to share the interrupt handler even if the enable/disable functions are different. Make sure it's always inlined to avoid the extra indirect call on the hot path. Checking with gcc 9 this produce the exact same code as of now: $ size drivers/gpu/drm/i915/i915_irq*.o text data bss dec hex filename 47511 560 0 48071 bbc7 drivers/gpu/drm/i915/i915_irq.o 47511 560 0 48071 bbc7 drivers/gpu/drm/i915/i915_irq_new.o $ gdb -batch -ex 'file drivers/gpu/drm/i915/i915_irq.o' -ex 'disassemble gen11_irq_handler' > /tmp/old.s $ gdb -batch -ex 'file drivers/gpu/drm/i915/i915_irq_new.o' -ex 'disassemble gen11_irq_handler' > /tmp/new.s $ git diff --no-index /tmp/{old,new}.s $ So, no change in behavior, just a simple refactor. Cc: Daniele Ceraolo Spurio <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915: do not set MOCS control values on dgfxLucas De Marchi1-0/+6
On dgfx there's no LLC and eDRAM control table. Since now this also means the device has global MOCS, just return early on the initialization function. L3 settings still apply and still need to be tweaked. Bspec: 45101 Cc: Daniele Ceraolo Spurio <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Daniele Ceraolo Spurio <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915: add new gen12 dgfx platform macroStuart Summers1-0/+4
Add a new macro for GEN12 platforms to be grouped under dgfx feature set. Signed-off-by: Stuart Summers <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/i915: Add is_dgfx to device infoJosé Roberto de Souza2-0/+2
This will be helpful to diferentiate a set of GPUs with the same GEN version. Signed-off-by: José Roberto de Souza <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-25drm/amdgpu: If amdgpu_ib_schedule fails return back the error.Andrey Grodzovsky1-1/+3
Use ERR_PTR to return back the error happened during amdgpu_ib_schedule. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/sched: Set error to s_fence if HW job submission failed.Andrey Grodzovsky1-3/+16
Problem: When run_job fails and HW fence returned is NULL we still signal the s_fence to avoid hangs but the user has no way of knowing if the actual HW job was ran and finished. Fix: Allow .run_job implementations to return ERR_PTR in the fence pointer returned and then set this error for s_fence->finished fence so whoever wait on this fence can inspect the signaled fence for an error. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu/powerplay: modify the parameters of SMU_MSG_PowerUpVcn to 0chen gong1-1/+1
The parameters what SMU_MSG_PowerUpVcn need is 0, not 1 Signed-off-by: chen gong <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu/gfx10: update gfx golden settings for navi12Tianci.Yin1-1/+1
update registers: mmCGTT_SPI_CLK_CTRL Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu/gfx10: update gfx golden settings for navi14Tianci.Yin1-1/+1
update registers: mmCGTT_SPI_CLK_CTRL Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu/gfx10: update gfx golden settingsTianci.Yin1-1/+1
update registers: mmCGTT_SPI_CLK_CTRL Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/powerplay: correct current clock level label for ArcturusEvan Quan1-8/+16
For dpm disabled case, it's assumed the only one support clock level is always current clock level. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/powerplay: skip unsupported clock limit settings on Arcturus V2Evan Quan2-116/+39
For Arcturus, clock limit settings on uclk/socclk/fclk domains are not supported. V2: simplify the code to support both SGPU and MGPU cases Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu: Allow reading more status registers on si/cikMarek Olšák5-1/+34
Allow userspace to read the same status registers for every family. Based on commit c7890fea, added any of these registers if defined in the include files of each architecture. Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu: Move amdgpu_ras_recovery_init to after SMU ready.Andrey Grodzovsky2-11/+13
For Arcturus the I2C traffic is done through SMU tables and so we must postpone RAS recovery init to after they are ready which is in amdgpu_device_ip_hw_init_phase2. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Evan Quan <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu: Use ARCTURUS in RAS EEPROM.Andrey Grodzovsky1-1/+8
Add Arcturus EEPROM/I2C support in generic EEPROM code. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Evan Quan <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/powerplay: Add EEPROM I2C read/write support to Arcturus.Andrey Grodzovsky1-0/+229
The communication is done through SMU table and hence the code is in powerplay. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Evan Quan <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amd/powerplay: Add interface for I2C transactions to SMU.Andrey Grodzovsky1-0/+9
Will be used by Arcturus support for RAS page retirement. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> reviewed-by: Evan Quan <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu: Add DC feature mask to disable fractional pwmLeo Li3-0/+8
[Why] Some LED panel drivers might not like fractional PWM. In such cases, backlight flickering may be observed. [How] Add a DC feature mask to disable fractional PWM, and associate it with the preexisting dc_config flag. The flag is only plumbed through the dmcu firmware, so plumb it through the driver path as well. To disable, add the following to the linux cmdline: amdgpu.dcfeaturemask=0x4 Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204957 Signed-off-by: Leo Li <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Tested-by: Lukáš Krejčí <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu: remove unused parameter in amdgpu_gfx_kiq_free_ringNirmoy Das5-7/+5
Signed-off-by: Nirmoy Das <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu/vcn: Enable VCN2.5 encodingJames Zhu1-3/+0
After VCN2.5 firmware (Version ENC: 1.1 Revision: 11), VCN2.5 encoding can work properly. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu/sdma5: do not execute 0-sized IBs (v2)Pelloux-prayer, Pierre-eric1-0/+1
This seems to help with https://bugs.freedesktop.org/show_bug.cgi?id=111481. v2: insert a NOP instead of skipping all 0-sized IBs to avoid breaking older hw Signed-off-by: Pierre-Eric Pelloux-Prayer <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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