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Add the clock controller node for the AmLogic GXBB machine.
Signed-off-by: Michael Turquette <[email protected]>
Signed-off-by: Kevin Hilman <[email protected]>
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Previous changes in this series allowed exposing the card clock from the
rk3399 SDHCI device and allowed consuming the card clock in the rk3399
eMMC PHY. Hook things up in the main rk3399 dtsi file.
Signed-off-by: Douglas Anderson <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
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On rk3399 we'd like to be able to properly set corecfg registers in the
Arasan SDHCI component. Specify the syscon to enable that.
Signed-off-by: Douglas Anderson <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
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The juno dts have entries for the hwmon scpi, let's create thermal zones
for the temperature sensors described in the Juno ARM Development
Platform Implementation Details.
Cc: Liviu Dudau <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Acked-by: Punit Agrawal <[email protected]>
Signed-off-by: Javi Merino <[email protected]>
Signed-off-by: Sudeep Holla <[email protected]>
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This patch adds power domain information to coresight devices using
SCPI power domains.
Cc: Lorenzo Pieralisi <[email protected]>
Acked-by: Liviu Dudau <[email protected]>
Signed-off-by: Sudeep Holla <[email protected]>
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Most of the debug-related components on Juno are located in the coreSight
subsystem while others are located in the Cortex-Axx clusters, the SCP
subsystem, and in the main system.
Each core in the two processor clusters contain an Embedded Trace
Macrocell(ETM) which generates real-time trace information that trace
tools can use and an ATB trace output that is sent to a funnel before
going to the CoreSight subsystem.
The trace output signals combine with two trace expansions using another
funnel and fed into the Embedded Trace FIFO(ETF0).
The output trace data stream of the funnel is then replicated before it
is sent to either the:
- Trace Port Interface Unit(TPIU), that sends it out using the trace port.
- ETR that can write the trace data to memory located in the application
memory space
Cc: Lorenzo Pieralisi <[email protected]>
Acked-by: Liviu Dudau <[email protected]>
Acked-by: Mathieu Poirier <[email protected]>
Signed-off-by: Sudeep Holla <[email protected]>
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Signed-off-by: Khiem Nguyen <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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This patch adds DRIF module clocks for r8a7795 SoC.
Signed-off-by: Ramesh Shanmugasundaram <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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According to the latest information, the parent clock of the LVDS module
clock is the S0D4 clock, not the S2D1 clock.
Note that this change has no influence on actual operation, as the
rcar-du LVDS encoder driver doesn't use the parent clock's rate.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
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Reviewed-by: Laurent Pinchart <[email protected]>
Signed-off-by: Kieran Bingham <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Renesas R-Car V2H (R8A7792) clocks are handled by R-Car gen2 clock driver.
Signed-off-by: Sergei Shtylyov <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Renesas R8A7792 SoC also has the CPG MSTP clocks...
Signed-off-by: Sergei Shtylyov <[email protected]>
Acked-by: Simon Horman <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Renesas R8A7792 SoC is a member of the R-Car gen2 family and so has CPG...
Signed-off-by: Sergei Shtylyov <[email protected]>
Acked-by: Simon Horman <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Adds the cache nodes and next-level-cache property for the
cacheinfo to work.
Signed-off-by: Li Yang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Adds the cache nodes and next-level-cache property for the
cacheinfo to work.
Signed-off-by: Li Yang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Node qmlclk has no consumer, so remove it.
Signed-off-by: Duc Dang <[email protected]>
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Correct X-Gene 2 timer interrupt polarity as low-level triggered.
Signed-off-by: Duc Dang <[email protected]>
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Unit addresses should not have a leading '0x'. Remove them.
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Duc Dang <[email protected]>
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The convention in these files is to use lowercase for "0x" prefixes and for
the hex constants themselves, but a few changes didn't follow that
convention, which makes the file annoying to read.
Use lowercase consistently for the hex constants. No functional change
intended.
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Duc Dang <[email protected]>
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http://github.com/Broadcom/stblinux into next/dt64
This pull request contains Device Tree changes for Broadcom ARM64-based SoCS:
- Anup adds nodes for the AHCI and SATA3 PHY peripherals to the Northstar2 SoCs
- Dhanajay enables pinctrl for the Northstar2 SoCs
- Jon Mason enables all of the UART peripherals found in the NS2 SVK and
finally adds the CCI-400 and PMU nodes
* tag 'arm-soc/for-4.8/devicetree-arm64' of http://github.com/Broadcom/stblinux:
arm64: dts: NS2: Add CCI-400 PMU support
arm64: dts: NS2: Add all of the UARTs
arm64: dts: Enable GPIO for Broadcom NS2 SoC
arm64: dts: enable pinctrl for Broadcom NS2 SoC
arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2
dt-bindings: ata: add compatible string for iProc AHCI controller
Signed-off-by: Olof Johansson <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt64
Amlogic DT 64-bit changes for v4.8
- add pinctrl driver and pins for several devices
- add reset driver
* tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM64: dts: amlogic: Enable Reset Controller on GXBB-based platforms
ARM64: dts: amlogic: gxbb: add ethernet
ARM64: dts: amlogic: gxbb: pinctrl: add/update UART
ARM64: dts: amlogic: add pins for EMMC, SD
ARM64: dts: amlogic: Enable pin controller on GXBB-based platforms
documentation: Add compatibles for Amlogic Meson GXBB pin controllers
ARM64: dts: amlogic: Add hiu and periphs buses
Signed-off-by: Olof Johansson <[email protected]>
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The 2nd additional region is the GIC virtual cpu interface register
base and size.
As the gic400 of rk3368 says, the cpu interface register map as below
:
-0x0000 GICC_CTRL
.
.
.
-0x00fc GICC_IIDR
-0x1000 GICC_IDR
Obviously, the region size should be greater than 0x1000.
So we should make sure to include the GICC_IDR since the kernel will access
it in some cases.
Fixes: b790c2cab5ca ("arm64: dts: add Rockchip rk3368 core dtsi and board dts for the r88 board")
Signed-off-by: Caesar Wang <[email protected]>
Reviewed-by: Shawn Lin <[email protected]>
Cc: [email protected]
[added Fixes and stable-cc]
Signed-off-by: Heiko Stuebner <[email protected]>
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We've got 9 (count em!) i2c controllers on rk3399, some of which are in
the PMU power domain and some of which are normal peripherals. Add them
all to the main rk3399 dtsi file so future patches can turn them on in
the board dts files.
Note: by default we try to set the i2c clock rate to 200 MHz so that we
can achieve good i2c functional clock rates. 200 MHz gives us the
ability to make very close to 100 kHz / 400 kHz / 1 MHz rates. If
boards want to tune clock rates further they can always override.
Possibly boards could want to tune this if:
- they wanted to save an infinitesimal amount of power and they knew
their i2c bus was slow anyway. Since we gate the functional clock
when the i2c bus is not active, power savings would only be while i2c
transfers were happening and probably won't be very big anyway.
- they wanted to eek out a bit more speed by carefully tuning the source
clock to make divisions work out perfectly, accounting for the rise /
fall time measured on an actual board.
Note also that we still request 200 MHz for the PMU i2c busses even
though we expect that we won't make that exactly (currently PPLL is 676
MHz which gives us 169 MHz).
Signed-off-by: David Wu <[email protected]>
Signed-off-by: Jianqun Xu <[email protected]>
[dianders: wrote desc; put in assigned-clocks; reordered nodes]
Signed-off-by: Douglas Anderson <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
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The 'dma-coherent' indicates that the hardware IP block can ensure
the coherency of the data transferred from/to the IP block. This
can avoid the software cache flush/invalid actions, and improve
the performance significantly.
The PCI IP block of ls1043a has this capability, so adding this
feature to improve the PCI performance.
Signed-off-by: Liu Gang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Add 'dma-coherent' description for PCI nodes.
The 'dma-coherent' indicates that the hardware IP block can ensure
the coherency of the data transferred from/to the IP block. This
can avoid the software cache flush/invalid actions, and improve
the performance significantly.
The PCI IP block of ls1043a has this capability, so adding
this feature to improve the PCI performance.
Signed-off-by: Liu Gang <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Kevin Hilman <[email protected]>
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Acked-by: Rob Herring <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Kevin Hilman <[email protected]>
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As Documentation/arm64/booting.txt says, the cpu-release-addr
location should be reserved.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Mark Rutland <[email protected]>
Signed-off-by: Olof Johansson <[email protected]>
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At first, 256 byte of the head of DRAM space was reserved for some
reasons. However, as the progress of development, it turned out
unnecessary, and it was never used in the end. Move the CPU release
address to leave no space.
Signed-off-by: Masahiro Yamada <[email protected]>
Signed-off-by: Olof Johansson <[email protected]>
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This node consists of various system-level configuration registers.
Signed-off-by: Masahiro Yamada <[email protected]>
Signed-off-by: Olof Johansson <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64
Renesas ARM64 Based SoC DT Updates for v4.8
* Fix W=1 dtc warnings and other cleanups
* Enable watchdog timer
* Enable DMA for I2C
* Increase the size of GIC-400 mapped registers: be nicer to hypervisors
* Support RTS/CTS hardware flow control
* tag 'renesas-arm64-dt-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: r8a7795: Drop 0x from unit address of gic
arm64: dts: salvator-x: Fix W=1 dtc warnings
arm64: dts: r8a7795: Fix W=1 dtc warnings
arm64: dts: r8a7795: Use SYSC "always-on" PM Domain for RWDT node
arm64: dts: salvator-x: Enable watchdog timer
arm64: dts: r8a7795: Add RWDT node
arm64: dts: r8a7795: enable DMA for I2C
arm64: dts: r8a7795: Increase the size of GIC-400 mapped registers
arm64: dts: salvator-x: SCIF1 supports RTS/CTS hardware flow control
Signed-off-by: Olof Johansson <[email protected]>
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Update reserved-memory in accordance with memory the detailed memory map
for 8916, so that we will be able to reference the firmware memory
regions.
Signed-off-by: Bjorn Andersson <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This adds the devicetree node for the SCM firmware.
Acked-by: Bjorn Andersson <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
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Add the PMU so we can get proper perf event support on this SoC.
Signed-off-by: Stephen Boyd <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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Add device bindings for CPUs to suspend using PSCI as the enable-method.
Cc: <[email protected]>
Signed-off-by: Lina Iyer <[email protected]>
Tested-by: Andy Gross <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch enables bam dma node, dma is used for both tx and rx on spi
and on high speed serial.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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Add the necessary properties to enable the SD-card on db410c boards.
Signed-off-by: Georgi Djakov <[email protected]>
Tested-by: Kevin Hilman <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property
is used to disable rx detection in P3 PHY mode.
Signed-off-by: Rajesh Bhagat <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property
is used to disable rx detection in P3 PHY mode.
Signed-off-by: Rajesh Bhagat <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and
LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1,
since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update
the #address-cells and reg properties accordingly.
Signed-off-by: Alison Wang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Signed-off-by: Gerd Hoffmann <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
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This merge brings over the DT ethernet nodes from 32-bit (used so that
we can get the MAC address for it) so that we can expose it on arm64
as well.
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While this devicetree also works for booting in 32-bit mode, it's
placed in arm64 since it's a 64-bit CPU (as suggested by Arnd).
Signed-off-by: Eric Anholt <[email protected]>
Acked-by: Stephen Warren <[email protected]> (v1)
Signed-off-by: Gerd Hoffmann <[email protected]>
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Signed-off-by: Eric Anholt <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Acked-by: Rob Herring <[email protected]>
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This adds thermal zone and tsadc nodes to rk3399 dtsi, rk3399 thermal
data is including the cpu and gpu sensor zone node.
The thermal zone node is the node containing all the required info
for describing a thermal zone, including its cooling device bindings.
The thermal zone node must contain, apart from its own properties, one
sub-node containing trip nodes and one sub-node containing all the zone
cooling maps.
The following is the parameter is introduced:
* polling-delay:
The maximum number of milliseconds to wait between polls
* polling-delay-passive:
The maximum number of milliseconds to wait between polls when performing
passive cooling.
* trips:
A sub-node which is a container of only trip point nodes required to
describe the thermal zone.
* cooling-maps:
A sub-node which is a container of only cooling device map nodes, used to
describe the relation between trips and cooling devices.
* cooling-device:
A phandle of a cooling device with its specifier, referring to which
cooling device is used in this cooling specifier binding. In the cooling
specifier, the first cell is the minimum cooling state and the second cell
is the maximum cooling state used in this map.
Signed-off-by: Caesar Wang <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
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Initial support for R-Car M3-W (r8a7796), including basic core clocks,
and SCIF2 (console) and INTC-AP (GIC) module clocks.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Tested-by: Simon Horman <[email protected]>
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Extract the code to support parts common to all members of the R-Car
Gen3 SoC family into a separate file, to ease sharing among SoC-specific
drivers.
Note that while the cpg_pll_configs[] arrays and the selection of the
config based on the MODE bits are identical on R-Car H3 and R-Car M3-W,
they are not common, and may be different on other R-Car Gen3 SoCs.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Tested-by: Simon Horman <[email protected]>
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Add all R-Car M3-W Clock Pulse Generator Core Clock Outputs, as listed
in Table 8.2b ("List of Clocks [R-Car M3-W]") of the R-Car Gen3
datasheet (rev. 0.51 + Errata for Rev051 Mar 31 2016).
Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, and SSPSRC) are
not included, as they are used as internal clock sources only, and never
referenced from DT.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Tested-by: Simon Horman <[email protected]>
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Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Rob Herring <[email protected]>
Tested-by: Simon Horman <[email protected]>
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Add dtsi file to support lg1313 SoC which based on Cortex-A53.
Also add dts file to support lg1312 reference board which based
on lg1313 SoC.
Signed-off-by: Chanho Min <[email protected]>
Signed-off-by: Olof Johansson <[email protected]>
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