| Age | Commit message (Collapse) | Author | Files | Lines |
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This adds support for enabling, disabling, and setting the rate of the
audio domain clocks. It will be necessary for setting the pixel clock
for HDMI in the VC4 driver and let us write a cpufreq driver. It will
also improve compatibility with user changes to the firmware's
config.txt, since our previous fixed clocks are unaware of it.
The firmware also has support for configuring the clocks through the
mailbox channel, but the pixel clock setup by the firmware doesn't
work, and it's Raspberry Pi specific anyway. The only conflicts we
should have with the firmware would be if we made firmware calls that
result in clock management (like opening firmware V3D or ISP access,
which we don't support in upstream), or on hardware over-thermal or
under-voltage (when the firmware would rewrite PLLB to take the ARM
out of overclock). If that happens, our cached .recalc_rate() results
would be incorrect, but that's no worse than our current state where
we used fixed clocks.
The existing fixed clocks in the code are left in place to provide
backwards compatibility with old device tree files.
Signed-off-by: Eric Anholt <[email protected]>
Tested-by: Martin Sperl <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
one clock of SPDIF, which is missed before.
We found an issue that imx can't enter low power mode with spdif
if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
so its parent clock (PLL clock) is prepared, the prepare operation of
PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
then it can enter low power mode.
So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
SPDIF_GCLK's parent clock is ipg clock.
Signed-off-by: Shengjiu Wang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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8960 family of devices have TSENS as part of GCC in hardware.
Hence DT would represent a GCC node with GCC properties as well
as TSENS. Create a virtual platform child device here for TSENS
so the driver can probe it and use the parent (GCC) to extract DT
properties.
Suggested-by: Stephen Boyd <[email protected]>
Signed-off-by: Rajendra Nayak <[email protected]>
[[email protected]: Massaged to work with devm friendly
qcom_cc_probe()]
Signed-off-by: Stephen Boyd <[email protected]>
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Having this hidden config below the COMMON_CLK_QCOM config causes
menuconfig to stop indenting config items after it.
<*> Support for Qualcomm's clock controllers
{M} APQ8084 Global Clock Controller
<M> APQ8084 Multimedia Clock Controller
{M} IPQ806x Global Clock Controller
<M> IPQ806x LPASS Clock Controller
<M> MSM8660 Global Clock Controller
<M> MSM8916 Global Clock Controller
{M} APQ8064/MSM8960 Global Clock Controller
<M> APQ8064/MSM8960 LPASS Clock Controller
<M> MSM8960 Multimedia Clock Controller
{M} MSM8974 Global Clock Controller
<M> MSM8974 Multimedia Clock Controller
Move it up above anything else so that we don't get odd
indenting.
Cc: Rajendra Nayak <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Now that qcom_cc_remove() is a nop, drop calls to
qcom_cc_remove() and any empty driver remove functions.
Cc: Rajendra Nayak <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Some APIs in qcom_cc_probe() don't have a devm counterpart, so we
have to use the calling device's platform data to pass pointers
to the remove path. Let's use devm_add_action() instead, so that
the remove path doesn't need to do anything, allowing us to
remove qcom_cc_remove() entirely.
Cc: Rajendra Nayak <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add support for new PLL-type for stih418 A9-PLL.
Currently the 407_A9_PLL type being used, it is corrected with this patch
4600c28 PLL allows to reach higher frequencies
so its programming algorithm is extended.
Signed-off-by: Pankaj Dev <[email protected]>
Signed-off-by: Gabriel Fernandez <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Change A9 PLL rate, as per requirement from the cpufreq framework,
for DVFS. For rate change, the A9 clock needs to be temporarily sourced
from PLL external to A9 and then sourced back to A9-PLL
Signed-off-by: Pankaj Dev <[email protected]>
Signed-off-by: Gabriel Fernandez <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The patch adds support for enable/disable of the Clockgen PLLs.
clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs.
Signed-off-by: Pankaj Dev <[email protected]>
Signed-off-by: Gabriel Fernandez <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The oxili_cx GDSC is inside the power domain of the oxili GDSC.
Add the dependency so that the CX domain can properly power up.
Reported-by: Rob Clark <[email protected]>
Cc: Rajendra Nayak <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Export these symbols so they can be used in loadable kernel
modules.
Cc: Rob Clark <[email protected]>
Cc: Rajendra Nayak <[email protected]>
Cc: Kevin Hilman <[email protected]>
Cc: Ulf Hansson <[email protected]>
Acked-by: Rafael J. Wysocki <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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This patch adds the driver and devicetree documentation for the
Silicon Labs SI514 clock generator chip. This is an I2C controlled
oscillator capable of generating clock signals ranging from 100kHz
to 250MHz.
Signed-off-by: Mike Looijmans <[email protected]>
[[email protected]: Drop clk.h include, remove some casts]
Signed-off-by: Stephen Boyd <[email protected]>
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Add ADC root clock support in imx7d clock tree.
Signed-off-by: Haibo Chen <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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clk-next
Pull mediatek clock support and fixes from James Liao:
"This is a collection of new Mediatek clocks support and fixes.
These patches come from Joe and me, including clock support for
subsystems, GPT and some minor fixes."
* 'v4.3-rc3-clk' of https://github.com/jamesjjliao/linux:
clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS
clk: mediatek: Add subsystem clocks of MT8173
dt-bindings: ARM: Mediatek: Document devicetree bindings for clock controllers
clk: mediatek: Fix rate and dependency of MT8173 clocks
clk: mediatek: Add fixed clocks support for Mediatek SoC.
clk: mediatek: Add __initdata and __init for data and functions
clk: mediatek: Remove unused code from MT8173.
clk: mediatek: Removed unused dpi_ck clock from MT8173
clk: mediatek: add 13mhz clock for MT8173
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drivers/clk/samsung/clk-exynos7.c:896:33:
warning: symbol 'fixed_rate_clks_fsys0' was not declared. Should
it be static?
drivers/clk/samsung/clk-exynos7.c:1010:33:
warning: symbol 'fixed_rate_clks_fsys1' was not declared. Should
it be static?
Cc: Sylwester Nawrocki <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Pull updates from Sylwester Nawrocki:
"Fixes, improvements and addition of some missing features
of the exynos7 clock controller driver."
* tag 'clk-samsung-4.4' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: exynos7: Add required clock tree for UFS
clk: samsung: exynos7: Add missing fixed_clks to cmu_info
clk: samsung: exynos7: Correct CMU_FSYS1 clocks names
clk: samsung: exynos7: Correct CMU_FSYS0 clocks names
clk: samsung: exynos7: Correct CMU_PERIS clocks names
clk: samsung: exynos7: Correct CMU_PERIC1 clocks names
clk: samsung: exynos7: Correct CMU_PERIC0 clocks names
clk: samsung: exynos7: Correct CMU_CCORE clocks names
clk: samsung: exynos7: Correct CMU_TOP1 clocks names
clk: samsung: exynos7: Correct CMU_TOP0 clocks names
clk: samsung: exynos7: Adds missing clocks gates of CMU_TOPC
clk: samsung: exynos7: Change the CMU_TOPC block clock names
clk: samsung: exynos7: Correct nr_clk_ids for fsys1
clk: samsung: exynos7: Correct nr_clk_ids for fsys0
clk: samsung: exynos7: Fix CMU TOP1 block
clk: samsung: exynos7: Fix CMU TOPC block clock
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* clk-fixes: (3 commits)
clk: ti: dflt: fix enable_reg validity check
clk: ti: fix dual-registration of uart4_ick
clk: ti: clk-7xx: Remove hardwired ABE clock configuration
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We have couple of standard but rare used baudrates which are not supported by
1,8432MHz reference frequency. Besides that user can potentially ask for any
baudrate (via BOTHER flag) and we currently don't fully support that. Since
clk-fractional-divider is moved to use rational best approximation for
reference frequency we may amend the driver to support whatever user wants.
Acked-by: Greg Kroah-Hartman <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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This patch converts the code to use rational best approximation algorithm which
is much more precise.
Suggested-by: Stephen Boyd <[email protected]>
Reviewed-by: Heikki Krogerus <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The ->mwidth and ->nwidth fields will be used by clk-fractional-divider when it
will be switched to rational base approximation algorithm.
Reviewed-by: Heiko Stuebner <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The patch adds mwidth and nwidth fields to the struct clk_fractional_divider
for further usage. While here, use GENMASK() instead of open coding this
functionality.
Reviewed-by: Heikki Krogerus <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Rename function parameter to be more explicit what it is for. This also makes
it in align with struct clk_ops.
There is no functional change.
Reviewed-by: Heikki Krogerus <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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https://github.com/t-kristo/linux-pm into clk-fixes
Pull fixes from Tero Kristo:
"A few TI clock driver fixes to pull against 4.3-rc"
* 'for-4.3-rc/ti-clk-fixes' of https://github.com/t-kristo/linux-pm: (3 commits)
clk: ti: dflt: fix enable_reg validity check
clk: ti: fix dual-registration of uart4_ick
clk: ti: clk-7xx: Remove hardwired ABE clock configuration
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The default clock enabling functions for TI clocks -
omap2_dflt_clk_enable() and omap2_dflt_clk_disable() perform a
NULL check for the enable_reg field of the clk_hw_omap structure.
This enable_reg field however is merely a combination of the index
of the master IP module, and the offset from the master IP module's
base address. A value of 0 is perfectly valid, and the current error
checking will fail in these cases. The issue was found when trying
to enable the iva2_ck clock on OMAP3 platforms.
So, switch the check to use IS_ERR. This correction is similar to the
logic used in commit c807dbedb5e5 ("clk: ti: fix ti_clk_get_reg_addr
error handling").
Fixes: 9f37e90efaf0 ("clk: ti: dflt: move support for default gate clock..")
Signed-off-by: Suman Anna <[email protected]>
Signed-off-by: Tero Kristo <[email protected]>
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On the OMAP AM3517 platform the uart4_ick gets registered
twice, causing any power management to /dev/ttyO3 to fail
when trying to wake the device up.
This solves the following oops:
[] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa09e008
[] PC is at serial_omap_pm+0x48/0x15c
[] LR is at _raw_spin_unlock_irqrestore+0x30/0x5c
Fixes: aafd900cab87 ("CLK: TI: add omap3 clock init file")
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Ben Dooks <[email protected]>
Signed-off-by: Tero Kristo <[email protected]>
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The ABE related clocks should be configured via DT and not have it wired
inside of the kernel.
Fixes: a74c52def9ab ("clk: ti: clk-7xx: Correct ABE DPLL configuration")
Signed-off-by: Peter Ujfalusi <[email protected]>
Signed-off-by: Tero Kristo <[email protected]>
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Previously we've only supported a few fixed clocks based on
assumptions about how the firmware sets up the clocks, but this
binding will let us control the actual (audio power domain) clock
manager.
Signed-off-by: Eric Anholt <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Acked-by: Lee Jones <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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clk-bcm2835.c predates the drivers under bcm/, but all the new BCM
drivers are going in there so let's follow them.
Signed-off-by: Eric Anholt <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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This simplifies the given function by getting rid of the manual
sign extension as well as saving an absolute value in an extra
variable.
Signed-off-by: Martin Kepplinger <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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mmc host controller's IO input/output timing is unpredictable if
bootloader execute tuning for HS200 mode. It might make kernel failed
to initialize mmc card in identification mode. The root cause is
tuning phase and degree setting for HS200 mode in bootloader aren't
applicable to that of identification mode in kernel stage. Anyway, we
can't force all bootloaders to reset tuning phase and degree setting
before into kernel. Simply reset it in rockchip_clk_register_mmc.
Signed-off-by: Shawn Lin <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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On drivers/clk/mxs/clk-frac.c, the function clk_frac_round_rate returned a bad
result. The division before multiplication computes a wrong value ; the
calculation is inverted to fix the problem. The second issue is that the exact
rate have decimals and they are truncate. The consequence is that the function
clk_frac_set_rate (which use the result of clk_frac_round_rate) computes a
wrong value for the register (the rate generated can be closer to the desired
rate). The correction is : if there is decimal to the result, it is rounded to
the next larger integer.
On drivers/clk/mxs/clk-frac.c, the function clk_frac_recalc_rate returned
a bad result. The multiplication is made before the division to compute a
correct value.
Signed-off-by: Victorien Vedrine <[email protected]>
Acked-by: Shawn Guo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The function can return negative value.
The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1].
[1]: http://permalink.gmane.org/gmane.linux.kernel/2046107
Signed-off-by: Andrzej Hajda <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Separate the update of pll registers from the actual set_rate function
so that the init callback does not need to access clk-API functions.
As we now have separated the getting and setting of the pll parameters
we can also directly use these new functions in other places too.
Signed-off-by: Heiko Stuebner <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add a new type of clocks that can be provided to a peripheral.
In addition to the peripheral clock, this new clock that can use several
input clocks as parents can generate divided rates.
This would allow a peripheral to have finer grained clocks for generating
a baud rate, clocking an asynchronous part or having more
options in frequency.
Signed-off-by: Nicolas Ferre <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
[[email protected]: Transition to new clk_hw provider APIs]
Signed-off-by: Stephen Boyd <[email protected]>
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Add support for the new sama5d2 SoC and adapt capabilities.
Signed-off-by: Nicolas Ferre <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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As some more information is added to the PCR register, we'd better use
a copy of its content and modify just the peripheral-related bits.
Implement a read-modify-write for the enable() and disable() callbacks.
Signed-off-by: Nicolas Ferre <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add _MASK and _OFFSET values and cleanup register fields layout.
Signed-off-by: Nicolas Ferre <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add REF2USB_TX clock support into MT8173 APMIXEDSYS. This clock
is needed by USB 3.0.
Signed-off-by: James Liao <[email protected]>
Reviewed-by: Daniel Kurtz <[email protected]>
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Most multimedia subsystem clocks will be accessed by multiple
drivers, so it's a better way to manage these clocks in CCF.
This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT
subsystems.
Signed-off-by: James Liao <[email protected]>
Reviewed-by: Daniel Kurtz <[email protected]>
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This adds the binding documentation for the mmsys, imgsys, vdecsys,
vencsys and vencltsys controllers found on Mediatek SoCs.
Signed-off-by: James Liao <[email protected]>
Reviewed-by: Daniel Kurtz <[email protected]>
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Remove the dependency from clk_null, and give all root clocks a
typical rate, include clkph_mck_o, usb_syspll_125m and hdmitx_dig_cts.
dpi_ck was removed due to no clock reference to it.
Replace parent clock of infra_cpum with cpum_ck, which is an external
clock and can be defined in the device tree.
Signed-off-by: James Liao <[email protected]>
Reviewed-by: Daniel Kurtz <[email protected]>
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This patch adds fixed clocks support by using CCF fixed-rate
clock implementation.
Signed-off-by: James Liao <[email protected]>
Reviewed-by: Daniel Kurtz <[email protected]>
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Add __init for clock registration functions, and add __initdata for
mtk_gate_regs initial structures.
Signed-off-by: James Liao <[email protected]>
Reviewed-by: Daniel Kurtz <[email protected]>
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Remove unused header files from MT8173, and remove unused
keywords from function declaration.
Signed-off-by: James Liao <[email protected]>
Reviewed-by: Daniel Kurtz <[email protected]>
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The dpi_ck clock can be removed because it not actually used
in topckgen and subsystems.
Signed-off-by: James Liao <[email protected]>
Reviewed-by: Daniel Kurtz <[email protected]>
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Add 13mhz clock used by GPT timer in infracfg.
Signed-off-by: Yingjoe Chen <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: James Liao <[email protected]>
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mxc_timer_init must not be called from within mx31_clocks_init_dt. It will
eventually be called by imx31_timer_init_dt
(drivers/clocksource/timer-imx-gpt.c).
This arranges the initialization code similar to clk-imx27.c
Signed-off-by: Alexander Stein <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Power management on of NoC(Notwork On Chip) requires that disconnect
and reconnect routine should been done during clk disable/enable.
also there are different types of clocks,
For NoC Macro clocks, write idle_bit and wait for hardward ACK;
For Socket clocks, write idle_bit;
For others, do nothing.
Signed-off-by: Guo Zeng <[email protected]>
Signed-off-by: Barry Song <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>
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re-order the codes more reasonable by moving variable-definition
together.
Signed-off-by: Guo Zeng <[email protected]>
Signed-off-by: Barry Song <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>
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