aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2023-04-13clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in ↵Mohammad Rafi Shaik1-0/+2
lpass_cc_sc7280_desc Add GDSCs in lpass_cc_sc7280_desc struct. When qcom,adsp-pil-mode is enabled, GDSCs required to solve dependencies in lpass_audiocc probe(). Fixes: 0cbcfbe50cbf ("clk: qcom: lpass: Handle the regmap overlap of lpasscc and lpass_aon") Signed-off-by: Mohammad Rafi Shaik <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-04-13clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registrationSrinivasa Rao Mandadapu1-6/+10
The qdsp6ss memory region is being shared by ADSP remoteproc device and lpasscc clock device, hence causing memory conflict. To avoid this, when qdsp6ss clocks are being enabled in remoteproc driver, skip qdsp6ss clock registration if "qcom,adsp-pil-mode" is enabled and also assign max_register value. Fixes: 4ab43d171181 ("clk: qcom: Add lpass clock controller driver for SC7280") Signed-off-by: Srinivasa Rao Mandadapu <[email protected]> Signed-off-by: Mohammad Rafi Shaik <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-04-13dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode propertySrinivasa Rao Mandadapu1-0/+7
When this property is set, the remoteproc is used to boot the LPASS and therefore qdsp6ss clocks would be used to bring LPASS out of reset, hence they are directly controlled by the remoteproc. This is a cleanup done to handle overlap of regmap of lpasscc and adsp remoteproc blocks. Signed-off-by: Srinivasa Rao Mandadapu <[email protected]> Signed-off-by: Mohammad Rafi Shaik <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-04-12clk: qcom: rpm: Use managed `of_clk_add_hw_provider()`Lars-Peter Clausen1-8/+2
Use the managed `devm_of_clk_add_hw_provider()` instead of `of_clk_add_hw_provider()`. This makes sure the provider gets automatically removed on unbind and allows to completely eliminate the drivers `remove()` callback. Signed-off-by: Lars-Peter Clausen <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-04-07clk: qcom: Add Global Clock Controller driver for IPQ9574Devi Priya3-0/+4257
Add Global Clock Controller (GCC) driver for ipq9574 based devices Co-developed-by: Anusha Rao <[email protected]> Signed-off-by: Anusha Rao <[email protected]> Signed-off-by: Devi Priya <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-04-07Merge branch '[email protected]' into clk-for-6.4Bjorn Andersson3-0/+438
Merge IPQ9574 Global Clock Controller binding through a topic branch to allow it also be introduced in the Devicetree source tree.
2023-04-07dt-bindings: clock: Add ipq9574 clock and reset definitionsDevi Priya3-0/+438
Add clock and reset ID definitions for ipq9574 Reviewed-by: Krzysztof Kozlowski <[email protected]> Co-developed-by: Anusha Rao <[email protected]> Signed-off-by: Anusha Rao <[email protected]> Signed-off-by: Devi Priya <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-04-07clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait valueKonrad Dybcio1-0/+1
Configure the disable wait value on the CX GDSC to ensure we don't get any undefined behavior. This was omitted when first adding the driver. Fixes: 8397e24278b3 ("clk: qcom: Add GPU clock controller driver for SM6375") Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-04-07clk: qcom: gcc-sm6115: Mark RCGs shared where applicableKonrad Dybcio1-25/+25
The vast majority of shared RCGs were not marked as such. Fix it. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-04-04clk: qcom: dispcc-qcm2290: Add MDSS_CORE resetKonrad Dybcio1-0/+7
Add the MDSS_CORE reset which can be asserted to reset the state of the entire MDSS. Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-04-04Merge branch '[email protected]' ↵Bjorn Andersson1-0/+4
into clk-for-6.4 Merge dt-binding include file additions through topic branch, to allow them to be made available in DT source tree as well.
2023-04-04dt-bindings: clock: dispcc-qcm2290: Add MDSS_CORE resetKonrad Dybcio1-0/+4
Add the MDSS_CORE reset which can be asserted to reset the state of the entire MDSS. Signed-off-by: Konrad Dybcio <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-23clk: qcom: apss-ipq-pll: add support for IPQ5332Kathiravan T1-1/+57
IPQ5332 APSS PLL is of type Stromer Plus. Add support for the same. To configure the stromer plus PLL separate API (clock_stromer_pll_configure) to be used. To achieve this, introduce the new member pll_type in device data structure and call the appropriate function based on this. Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Kathiravan T <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-23dt-bindings: clock: qcom,a53pll: add IPQ5332 compatibleKathiravan T1-0/+1
Add IPQ5332 compatible to A53 PLL bindings. Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Kathiravan T <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-23clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL typesKathiravan T1-19/+41
APSS PLL found on the IPQ8074 and IPQ6018 are of type Huayra PLL. But, IPQ5332 APSS PLL is of type Stromer Plus. To accommodate both these PLLs, refactor the driver to take the clk_alpha_pll, alpha_pll_config via driver data. Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Kathiravan T <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-23dt-bindings: mailbox: qcom,apcs-kpss-global: fix SDX55 'if' matchKrzysztof Kozlowski1-2/+3
The qcom,sdx55-apcs-gcc is followed by another compatible (syscon), thus the 'if' clause must match by contains. Fixes: 0d17014e9189 ("dt-bindings: mailbox: Add binding for SDX55 APCS") Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-23dt-bindings: mailbox: qcom,apcs-kpss-global: correct SDX55 clocksKrzysztof Kozlowski1-2/+2
SDX55 and SDX65 DTS takes clocks in a bit different order. Adjust bindings to the DTS. Fixes: 0d17014e9189 ("dt-bindings: mailbox: Add binding for SDX55 APCS") Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-21clk: qcom: gcc-msm8998: Update the .pwrsts for usb gdscKonrad Dybcio1-1/+2
The USB controller on msm8998 doesn't retain its state when the system goes into low power state and the GDSCs are turned off. This can be observed by the USB connection not coming back alive after putting the device into suspend, essentially breaking USB. Work around this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. This change should be reverted when a proper suspend sequence is implemented in the USB drivers. Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-21clk: qcom: gcc-msm8996: Update the .pwrsts for usb gdscKonrad Dybcio1-1/+2
The USB controller on MSM8996 doesn't retain its state when the system goes into low power state and the GDSCs are turned off. This can be observed by the USB connection not coming back alive after putting the device into suspend, essentially breaking USB. Work around this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. This change should be reverted when a proper suspend sequence is implemented in the USB drivers. Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-21clk: qcom: gcc-sm6375: Update the .pwrsts for usb gdscKonrad Dybcio1-1/+2
The USB controller on sm6375 doesn't retain its state when the system goes into low power state and the GDSCs are turned off. This can be observed by the USB connection not coming back alive after putting the device into suspend, essentially breaking USB. Work around this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. This change should be reverted when a proper suspend sequence is implemented in the USB drivers. Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-15clk: qcom: smd-rpm: Add clocks for MSM8917Otto Pflüger1-0/+35
MSM8917 has mostly the same rpm clocks as MSM8953, but lacks RF_CLK3 and IPA_CLK and additionally has the BIMC_GPU clock. Signed-off-by: Otto Pflüger <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-15clk: qcom: Add global clock controller driver for MSM8917Otto Pflüger3-0/+3314
This driver provides clocks, resets and power domains needed for various components of the MSM8917 SoC and the very similar QM215 SoC. According to [1] in the downstream kernel, the GPU clock has a different source mapping on QM215 (gcc_gfx3d_map vs gcc_gfx3d_map_qm215). [1]: https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LF.UM.8.6.2-28000-89xx.0/include/dt-bindings/clock/msm-clocks-hwio-8952.h#L298 Signed-off-by: Otto Pflüger <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-15Merge branch '[email protected]' into clk-for-6.4Bjorn Andersson3-4/+201
Merge MSM8917 Global Clock Controller and RPM clock controller bindings through topic branch, to make it possible to introduce in Devicetree source depending on these.
2023-03-15dt-bindings: clock: qcom,rpmcc: Add MSM8917Otto Pflüger1-0/+2
Document the qcom,rpmcc-msm8917 compatible. Signed-off-by: Otto Pflüger <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-15dt-bindings: clock: Add MSM8917 global clock controllerOtto Pflüger2-4/+199
Add a device tree binding to describe clocks, resets and power domains provided by the global clock controller on MSM8917 SoCs and the very similar QM215 SoCs. Add the new compatibles to qcom,gcc-msm8909.yaml. There is no need to create another YAML file because the bindings are identical (MSM8917 GCC requires the same parent clocks as the MSM8909 GCC). Signed-off-by: Otto Pflüger <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-15clk: qcom: smd: Add XO RPM clocks for MSM8226/MSM8974Rayyan Ansari1-0/+2
Add the XO and XO_A clocks to the MSM8974 clock list, which is also used on MSM8226. Signed-off-by: Rayyan Ansari <[email protected]> Tested-by: Luca Weiss <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-15dt-bindings: arm: msm: Rework kpss-gcc driver Documentation to yamlChristian Marangi2-44/+88
Rework kpss-gcc driver Documentation to yaml Documentation and move it to clock as it's a clock-controller. The current kpss-gcc Documentation have major problems and can't be converted directly. Introduce various changes to the original Documentation. Add #clock-cells additional binding as this clock outputs a static clk named acpu_l2_aux with supported compatible. Only some compatible require and outputs a clock, for the others, set only the reg as a required binding to correctly export the kpss-gcc registers. As the reg is shared also add the required syscon compatible. Signed-off-by: Christian Marangi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-15dt-bindings: arm: msm: Convert and split kpss-acc driver Documentation to yamlChristian Marangi3-49/+114
Convert kpss-acc driver Documentation to yaml. The original Documentation was wrong all along. Fix it while we are converting it. The example was wrong as kpss-acc-v2 should only expose the regs but we don't have any driver that expose additional clocks. The kpss-acc driver is only specific to v1. For this exact reason, split the Documentation to 2 different schema, v1 as clock-controller and v2 for power-manager as per msm-3.10 specification, the exposed regs handle power manager. Signed-off-by: Christian Marangi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-15clk: qcom: ipq5332: mark GPLL4 as ignore unused temporarilyKathiravan T1-0/+11
Clock framework disables the GPLL4 source since there are no active users for this source currently. Some of the clocks initialized by the bootloaders uses the GPLL4 as the source. Due to this, when the GPLL4 is disabled by the clock framework, system is going for the reboot. To avoid this, mark the GPLL4 as ignore unused so that clock framework doesn't disable it. Once the users of this source is enabled, we can get rid of this flag. Signed-off-by: Kathiravan T <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-15clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoCKathiravan T3-0/+3822
Add support for the global clock controller found on IPQ5332 SoC. PLL used on IPQ5332 is of type Stromer Plus PLL, however the programming sequence is same as Stromer PLL, so lets re-use the Stromer PLL ops. Signed-off-by: Kathiravan T <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-15clk: qcom: Add STROMER PLUS PLL type for IPQ5332Kathiravan T2-0/+12
Add the support for stromer plus pll, which is found on the IPQ5332 SoCs. Programming sequence is same as the stromer pll, so we can re-use the same. Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Kathiravan T <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-15clk: qcom: clk-alpha-pll: Add support for Stromer PLLsVaradarajan Narayanan2-2/+139
Add programming sequence support for managing the Stromer PLLs. Reviewed-by: Stephen Boyd <[email protected]> Co-developed-by: Sricharan R <[email protected]> Signed-off-by: Sricharan R <[email protected]> Signed-off-by: Varadarajan Narayanan <[email protected]> Signed-off-by: Kathiravan T <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-15Merge branch '[email protected]' into clk-for-6.4Bjorn Andersson2-0/+409
Merge the IPQ5332 Global Clock Controller binding through a topic branch to make it possible to include in Devicetree source as well.
2023-03-15dt-bindings: clock: Add Qualcomm IPQ5332 GCCKathiravan T2-0/+409
Add binding for the Qualcomm IPQ5332 Global Clock Controller. Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Kathiravan T <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-15clk: qcom: remove unused variables gpucc_parent_data,map_2Tom Rix1-12/+0
gcc with W=1 reports these errors drivers/clk/qcom/gpucc-sm6375.c:145:37: error: ‘gpucc_parent_data_2’ defined but not used [-Werror=unused-const-variable=] 145 | static const struct clk_parent_data gpucc_parent_data_2[] = { | ^~~~~~~~~~~~~~~~~~~ drivers/clk/qcom/gpucc-sm6375.c:139:32: error: ‘gpucc_parent_map_2’ defined but not used [-Werror=unused-const-variable=] 139 | static const struct parent_map gpucc_parent_map_2[] = { | ^~~~~~~~~~~~~~~~~~ These variables are not used, so remove them. Signed-off-by: Tom Rix <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-15clk: qcom: gcc-qcm2290: Fix up gcc_sdcc2_apps_clk_srcKonrad Dybcio1-1/+2
Add the PARENT_ENABLE flag to prevent the clock from getting stuck at boot and use floor_ops to avoid SDHCI overclocking. Fixes: 496d1a13d405 ("clk: qcom: Add Global Clock Controller driver for QCM2290") Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-13clk: qcom: gcc-ipq4019: convert to parent dataRobert Marko1-258/+222
Convert the IPQ4019 GCC driver to use parent data instead of global name matching. Utilize ARRAY_SIZE for num_parents instead of hardcoding the value. Signed-off-by: Robert Marko <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-13clk: qcom: gcc-ipq4019: move pcnoc clocks upRobert Marko1-37/+37
Move pcnoc clocks up just after PLL-s to be able to use their HW fields. Signed-off-by: Robert Marko <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-13clk: qcom: gcc-ipq4019: move PLL clocks upRobert Marko1-328/+328
Move PLL clock declarations up, before clock parent tables, so that we can use pll hw clock fields in the next commit. Signed-off-by: Robert Marko <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-13clk: qcom: gcc-ipq4019: convert XO and sleep clk to parent_dataRobert Marko1-30/+45
Start off IPQ4019 GCC conversion by converting XO and sleep clks to parent data in order to directly pass them. Signed-off-by: Robert Marko <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-13dt-bindings: clock: split qcom,gcc-ipq4019 to separate fileRobert Marko2-2/+53
Move schema for the GCC on IPQ4019 platform to a separate file to be able to allow passing XO and sleep clks directly to GCC. Signed-off-by: Robert Marko <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-13clk: qcom: Add Global Clock Controller (GCC) driver for SM7150Danila Tikhonov3-0/+3057
Add support for the global clock controller found on SM7150 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Co-developed-by: David Wronek <[email protected]> Signed-off-by: David Wronek <[email protected]> Signed-off-by: Danila Tikhonov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-13Merge branch '[email protected]' into clk-for-6.4Bjorn Andersson2-0/+238
Merge SM7180 Global Clock Controller binding through a dedicated topic branch, so that it can be introduced into the Devicetree source tree as well in the same kernel release.
2023-03-13dt-bindings: clock: Add SM7150 GCC clocksDanila Tikhonov2-0/+238
Add device tree bindings for global clock subsystem clock controller for Qualcomm Technology Inc's SM7150 SoCs. Co-developed-by: David Wronek <[email protected]> Signed-off-by: David Wronek <[email protected]> Signed-off-by: Danila Tikhonov <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-13clk: qcom: clk-hfpll: switch to .determine_rateLuca Weiss1-7/+7
.determine_rate is meant to replace .round_rate. The former comes with a benefit which is especially relevant on 32-bit systems: since .determine_rate uses an "unsigned long" (compared to a "signed long" which is used by .round_rate) the maximum value on 32-bit systems increases from 2^31 (or approx. 2.14GHz) to 2^32 (or approx. 4.29GHz). Signed-off-by: Luca Weiss <[email protected]> Tested-by: Christian Marangi <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-13clk: qcom: clk-krait: switch to .determine_rateLuca Weiss1-5/+5
.determine_rate is meant to replace .round_rate. The former comes with a benefit which is especially relevant on 32-bit systems: since .determine_rate uses an "unsigned long" (compared to a "signed long" which is used by .round_rate) the maximum value on 32-bit systems increases from 2^31 (or approx. 2.14GHz) to 2^32 (or approx. 4.29GHz). Signed-off-by: Luca Weiss <[email protected]> Tested-by: Christian Marangi <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-13clk: qcom: Add GPU clock controller driver for SM6115Konrad Dybcio3-0/+513
Add support for the GPU clock controller found on SM6115. Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-13clk: qcom: Add GPU clock controller driver for SM6375Konrad Dybcio3-0/+479
Add support for the GPU clock controller found on SM6375. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-13clk: qcom: Add GPU clock controller driver for SM6125Konrad Dybcio3-0/+434
Add support for the GPU clock controller found on SM6125. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-13clk: qcom: branch: Clean up branch enable registersKonrad Dybcio2-9/+8
Prefix the "branch enable" registers with CBCR_ to be closer to what they are actually called in Qualcomm terms, use GENMASK instead of shifting values around and adjust their usage accordingly. Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
Powered by cgit, Gruvboxed by Blaster4385.