aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2019-07-12Merge branches 'clk-debugfs', 'clk-unused', 'clk-refactor' and 'clk-qoriq' ↵Stephen Boyd9-194/+30
into clk-next - Add a 'clk_parent' file in clk debugfs - Remove dead code in various clk drivers * clk-debugfs: clk: Add clk_parent entry in debugfs * clk-unused: clk: qcom: Fix -Wunused-const-variable clk: mmp: frac: Remove set but not used variable 'prev_rate' clk: ti: Remove unused functions clk: mediatek: mt8516: Remove unused variable * clk-refactor: clk: clk-cdce706: simplify getting the adapter of a client clk: Simplify clk_core_can_round() * clk-qoriq: clk: qoriq: add support for lx2160a
2019-07-12Merge branches 'clk-bulk-optional', 'clk-kirkwood', 'clk-socfpga' and ↵Stephen Boyd9-12/+120
'clk-docs' into clk-next - Add a clk_bulk_get_optional() API (with devm too) - Support for Marvell 98DX1135 SoCs * clk-bulk-optional: clk: Document some devm_clk_bulk*() APIs clk: Add devm_clk_bulk_get_optional() function clk: Add clk_bulk_get_optional() function * clk-kirkwood: clk: kirkwood: Add support for MV98DX1135 dt-bindings: clock: mvebu: Add compatible string for 98dx1135 core clock * clk-socfpga: clk: socfpga: stratix10: fix divider entry for the emac clocks clk: socfpga: stratix10: add additional clocks needed for the NAND IP * clk-docs: clk: Grammar missing "and", Spelling s/statisfied/satisfied/
2019-07-12Merge branches 'clk-ti', 'clk-samsung', 'clk-imx' and 'clk-allwinner' into ↵Stephen Boyd52-2387/+3349
clk-next * clk-ti: clk: ti: Use int to check return value from of_property_count_elems_of_size() firmware: ti_sci: extend clock identifiers from u8 to u32 clk: keystone: sci-clk: extend clock IDs to 32 bits clk: keystone: sci-clk: probe clocks from DT instead of firmware clk: keystone: sci-clk: split out the fw clock parsing to own function clk: keystone: sci-clk: cut down the clock name length * clk-samsung: clk: samsung: Add bus clock for GPU/G3D on Exynos4412 clk: samsung: add new clocks for DMC for Exynos5422 SoC clk: samsung: add BPLL rate table for Exynos 5422 SoC clk: samsung: add needed IDs for DMC clocks in Exynos5420 clk: samsung: exynos5433: Use of_clk_get_parent_count() * clk-imx: (38 commits) clk: imx8mq: Keep uart clocks on during system boot clk: imx: Remove __init for imx_register_uart_clocks() API clk: imx6q: fix section mismatch warning clk: imx8mq: Use devm_platform_ioremap_resource() instead of of_iomap() clk: imx8mq: Use imx_check_clocks() API directly clk: imx: Remove __init for imx_check_clocks() API clk: imx6sll: Switch to clk_hw based API clk: imx7d: Switch to clk_hw based API clk: imx6ul: Switch to clk_hw based API clk: imx6sx: Switch to clk_hw based API clk: imx6q: Switch to clk_hw based API clk: imx6sl: Switch to clk_hw based API clk: imx: Switch wrappers to clk_hw based API clk: imx: clk-fixup-mux: Switch to clk_hw based API clk: imx: clk-fixup-div: Switch to clk_hw based API clk: imx: clk-gate-exclusive: Switch to clk_hw based API clk: imx: clk-pfd: Switch to clk_hw based API clk: imx: clk-pllv3: Switch to clk_hw based API clk: imx: clk-gate2: Switch to clk_hw based API clk: imx: clk-cpu: Switch to clk_hw based API ... * clk-allwinner: (29 commits) clk: Simplify debugfs printing and add a newline clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE clk: sunxi-ng: gate: Add macros for referencing local clock parents clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_* clk: sunxi-ng: switch to of_clk_hw_register() for registering clks clk: fixed-factor: Add CLK_FIXED_FACTOR_FW_NAME for DT clock-names parent ...
2019-07-12Merge branches 'clk-qcom-gdsc-warn', 'clk-ingenic', 'clk-qcom-qcs404-reset', ↵Stephen Boyd31-208/+1298
'clk-xgene-limit' and 'clk-meson' into clk-next * clk-qcom-gdsc-warn: clk: qcom: gdsc: WARN when failing to toggle * clk-ingenic: MIPS: Remove dead code clk: ingenic: Remove unused functions MIPS: jz4740: PM: Let CGU driver suspend clocks and set sleep mode clk: ingenic: Handle setting the Low-Power Mode bit clk: ingenic: Add missing header in cgu.h clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly clk: ingenic/jz4725b: Fix incorrect dividers for main clocks clk: ingenic/jz4770: Fix incorrect dividers for main clocks clk: ingenic/jz4740: Fix incorrect dividers for main clocks clk: ingenic: Add support for divider tables * clk-qcom-qcs404-reset: clk: gcc-qcs404: Add PCIe resets * clk-xgene-limit: clk: xgene: Don't build COMMON_CLK_XGENE by default * clk-meson: clk: meson: g12a: mark fclk_div3 as critical clk: meson: g12a: Add support for G12B CPUB clocks dt-bindings: clk: meson: add g12b periph clock controller bindings clk: meson-g12a: add temperature sensor clocks dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs clk: meson: meson8b: add the cts_i958 clock clk: meson: meson8b: add the cts_mclk_i958 clocks clk: meson: meson8b: add the cts_amclk clocks dt-bindings: clock: meson8b: add the audio clocks clk: meson: g12a: add controller register init clk: meson: eeclk: add init regs clk: meson: g12a: add mpll register init sequences clk: meson: mpll: add init callback and regs clk: meson: axg: spread spectrum is on mpll2 clk: meson: gxbb: no spread spectrum on mpll0 clk: meson: mpll: properly handle spread spectrum clk: meson: meson8b: fix a typo in the VPU parent names array variable clk: meson: fix MPLL 50M binding id typo
2019-07-12Merge branches 'clk-pwm-duty', 'clk-bcm', 'clk-mtk', 'clk-qcom-msm8998-gpu' ↵Stephen Boyd21-144/+343
and 'clk-renesas' into clk-next - Add support to get duty cycle of generic pwm clks * clk-pwm-duty: clk: pwm: implement the .get_duty_cycle callback * clk-bcm: clk: bcm: Allow CLK_BCM2835 for ARCH_BRCMSTB clk: bcm: Make BCM2835 clock drivers selectable * clk-mtk: clk: mediatek: Remove MT8183 unused clock clk: mediatek: add audsys clock driver for MT8516 dt-bindings: mediatek: audsys: add support for MT8516 * clk-qcom-msm8998-gpu: dt-bindings: clock: Document gpucc for msm8998 * clk-renesas: clk: renesas: cpg-mssr: Use [] to denote a flexible array member clk: renesas: cpg-mssr: Combine driver-private and clock array allocation clk: renesas: mstp: Combine group-private and clock array allocation clk: renesas: div6: Combine clock-private and parent array allocation clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_priv clk: renesas: r8a774a1: Add TMU clock clk: renesas: r8a77995: Add CMM clocks clk: renesas: r8a77990: Add CMM clocks clk: renesas: r8a77965: Add CMM clocks clk: renesas: r8a7795: Add CMM clocks clk: renesas: r9a06g032: Add clock domain support dt-bindings: clock: renesas: r9a06g032-sysctrl: Document power Domains clk: renesas: mstp: Remove error messages on out-of-memory conditions clk: renesas: cpg-mssr: Remove error messages on out-of-memory conditions clk: renesas: cpg-mssr: Use genpd of_node instead of local copy clk: renesas: r8a7796: Add CMM clocks clk: renesas: r8a779{5|6|65}: Add TPU clock
2019-06-25clk: qoriq: add support for lx2160aVabhav Sharma1-0/+12
Add clockgen support and configuration for NXP SoC lx2160a with compatible property as "fsl,lx2160a-clockgen". Signed-off-by: Tang Yuantian <[email protected]> Signed-off-by: Yogesh Gaur <[email protected]> Signed-off-by: Vabhav Sharma <[email protected]> Acked-by: Scott Wood <[email protected]> Acked-by: Stephen Boyd <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25clk: clk-cdce706: simplify getting the adapter of a clientWolfram Sang1-1/+1
We have a dedicated pointer for that, so use it. Much easier to read and less computation involved. Signed-off-by: Wolfram Sang <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25clk: qcom: Fix -Wunused-const-variableNathan Huckleberry1-36/+0
Clang produces the following warning drivers/clk/qcom/gcc-msm8996.c:133:32: warning: unused variable 'gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map' [-Wunused-const-variable] static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map[] = { ^drivers/clk/qcom/gcc-msm8996.c:141:27: warning: unused variable 'gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div' [-Wunused-const-variable] static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div[] = { ^ drivers/clk/qcom/gcc-msm8996.c:187:32: warning: unused variable 'gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map' [-Wunused-const-variable] static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map[] = { ^ drivers/clk/qcom/gcc-msm8996.c:197:27: warning: unused variable 'gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div' [-Wunused-const-variable] static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[] = { It looks like these were never used. Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Cc: [email protected] Link: https://github.com/ClangBuiltLinux/linux/issues/518 Suggested-by: Nathan Chancellor <[email protected]> Signed-off-by: Nathan Huckleberry <[email protected]> Reviewed-by: Nathan Chancellor <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25MIPS: Remove dead codePaul Cercueil4-38/+0
Remove the unused <asm/mach-jz4740/clock.h> include. Signed-off-by: Paul Cercueil <[email protected]> Acked-by: Paul Burton <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25clk: ingenic: Remove unused functionsPaul Cercueil1-73/+0
These functions are not called anywhere anymore, they can safely be removed. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25MIPS: jz4740: PM: Let CGU driver suspend clocks and set sleep modePaul Cercueil1-8/+0
Instead of forcing the jz4740 clocks to suspend here, we let the CGU driver handle it. We also let the CGU driver set the "sleep mode" bit. This has the added benefit that now it is possible to build a kernel on SoCs newer than the JZ4740 with CONFIG_PM. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25clk: ingenic: Handle setting the Low-Power Mode bitPaul Cercueil7-32/+69
The Low-Power Mode, when enabled, will make the "wait" MIPS instruction suspend the system. This is not really clock-related, but this bit happens to be in the register set of the CGU. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25clk: ingenic: Add missing header in cgu.hPaul Cercueil1-0/+1
The cgu.h has structures that contain 'clk_onecell_data' and 'clk_hw' structures (no pointers), so the <linux/clk-provider.h> header should be included. Signed-off-by: Paul Cercueil <[email protected]> [[email protected]: Drop removal of includes in drivers] Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25clk: Add clk_parent entry in debugfsLeonard Crestez1-0/+15
This allows to easily determine the parent in shell scripts without parsing more complex files. Add the clk_parent file for all clks which can have a parent, not just muxes. This way it can be used to determine the clk tree structure without parsing more complex files. Signed-off-by: Leonard Crestez <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25clk: Grammar missing "and", Spelling s/statisfied/satisfied/Geert Uytterhoeven1-2/+2
Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25clk: Simplify clk_core_can_round()Geert Uytterhoeven1-4/+1
A boolean expression already evaluates to true or false, so there is no need to check the result and return true or false explicitly. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Jerome Brunet <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25clk: socfpga: stratix10: fix divider entry for the emac clocksDinh Nguyen1-2/+2
The fixed dividers for the emac clocks should be 2 not 4. Signed-off-by: Dinh Nguyen <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25clk: socfpga: stratix10: add additional clocks needed for the NAND IPDinh Nguyen2-2/+8
The nand_clk is actually called the nand_x_clk and the parent is the l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the nand_x_clk and has a fixed divider of 4. The same is true for the nand_ecc_clk. Signed-off-by: Dinh Nguyen <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25clk: kirkwood: Add support for MV98DX1135Chris Packham1-0/+17
The 98DX1135 is a switch chip with an integrated CPU. This is similar to the 98DX4122 except that the core clock speed is fixed to 166Mhz. Signed-off-by: Chris Packham <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25dt-bindings: clock: mvebu: Add compatible string for 98dx1135 core clockChris Packham1-0/+1
Add compatible string for the core clock on the 98dx1135 switch with integrated CPU. Signed-off-by: Chris Packham <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25clk: Document some devm_clk_bulk*() APIsStephen Boyd1-0/+4
Add some new clk devm APIs that we've added over time to the devres documentation. Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25clk: Add devm_clk_bulk_get_optional() functionSylwester Nawrocki2-3/+47
Add managed version of the clk_bulk_get_optional() helper function. Signed-off-by: Sylwester Nawrocki <[email protected]> [[email protected]: Mark __devm_clk_bulk_get() static] Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25clk: Add clk_bulk_get_optional() functionSylwester Nawrocki2-3/+39
clk_bulk_get_optional() allows to get a group of clocks where one or more is optional. For a not available clock, e.g. not specifed in the clock consumer node in DT, its respective struct clk pointer will be NULL. This allows for operating on a group of returned clocks (struct clk_bulk_data array) with existing clk_bulk* APIs. Signed-off-by: Sylwester Nawrocki <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-25clk: Simplify debugfs printing and add a newlineStephen Boyd1-19/+15
The possible parent printing function duplicates a bunch of if conditions. Pull that into another function so we can print an extra character at the end, either a space or a newline. This way we can add the required newline that got lost here and also shorten the code. Fixes: 2d156b78ce8f ("clk: Fix debugfs clk_possible_parents for clks without parent string names") Cc: Chen-Yu Tsai <[email protected]> Tested-by: Chen-Yu Tsai <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-24Merge tag 'imx-clk-5.3' of ↵Stephen Boyd21-1994/+2225
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx Pull i.MX clk driver changes from Shawn Guo: - A series from Abel Vesa to switch i.MX6 and i.MX7 clock drivers to clk_hw based API - Add GPIO, SNVS and GIC clocks for i.MX8 drivers - Create a common function imx_mmdc_mask_handshake() for masking MMDC handshake - Drop __init for function imx_check_clocks() and imx_register_uart_clocks(), so that they can be used by i.MX8 clock drivers which use driver model - Use devm_platform_ioremap_resource() instead of of_iomap() for imx8mq clock driver - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock. - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting * tag 'imx-clk-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (38 commits) clk: imx8mq: Keep uart clocks on during system boot clk: imx: Remove __init for imx_register_uart_clocks() API clk: imx6q: fix section mismatch warning clk: imx8mq: Use devm_platform_ioremap_resource() instead of of_iomap() clk: imx8mq: Use imx_check_clocks() API directly clk: imx: Remove __init for imx_check_clocks() API clk: imx6sll: Switch to clk_hw based API clk: imx7d: Switch to clk_hw based API clk: imx6ul: Switch to clk_hw based API clk: imx6sx: Switch to clk_hw based API clk: imx6q: Switch to clk_hw based API clk: imx6sl: Switch to clk_hw based API clk: imx: Switch wrappers to clk_hw based API clk: imx: clk-fixup-mux: Switch to clk_hw based API clk: imx: clk-fixup-div: Switch to clk_hw based API clk: imx: clk-gate-exclusive: Switch to clk_hw based API clk: imx: clk-pfd: Switch to clk_hw based API clk: imx: clk-pllv3: Switch to clk_hw based API clk: imx: clk-gate2: Switch to clk_hw based API clk: imx: clk-cpu: Switch to clk_hw based API ...
2019-06-24Merge tag 'clk-v5.3-samsung' of ↵Stephen Boyd5-10/+92
git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung Pull Samsung clk driver updates from Sylwester Nawrocki: - Addition of clocks required for new Exynos5422 Dynamic Memory Controller driver - clock definition for Exynos4412 Mali - minor clean up of clk-exynos5433.c * tag 'clk-v5.3-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: Add bus clock for GPU/G3D on Exynos4412 clk: samsung: add new clocks for DMC for Exynos5422 SoC clk: samsung: add BPLL rate table for Exynos 5422 SoC clk: samsung: add needed IDs for DMC clocks in Exynos5420 clk: samsung: exynos5433: Use of_clk_get_parent_count()
2019-06-24Merge tag 'clk-renesas-for-v5.3-tag2' of ↵Stephen Boyd8-36/+36
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add CMM (Color Management Module) clocks on R-Car H3, M3-N, E3, and D3 - Add TPU (Timer Pulse Unit / PWM) clocks on RZ/G2M - Small cleanups and fixes * tag 'clk-renesas-for-v5.3-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Use [] to denote a flexible array member clk: renesas: cpg-mssr: Combine driver-private and clock array allocation clk: renesas: mstp: Combine group-private and clock array allocation clk: renesas: div6: Combine clock-private and parent array allocation clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_priv clk: renesas: r8a774a1: Add TMU clock clk: renesas: r8a77995: Add CMM clocks clk: renesas: r8a77990: Add CMM clocks clk: renesas: r8a77965: Add CMM clocks clk: renesas: r8a7795: Add CMM clocks
2019-06-24Merge tag 'sunxi-ng-parent-rewrite-part-1-take-2' of ↵Stephen Boyd18-223/+526
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner sunxi-ng clk driver parent relation rewrite part 1 - take 2 from Chen-Yu Tsai: "The first part of ongoing work to convert the sunxi-ng clk driver from using global clock name strings to describe clk parenting, to having direct struct clk_hw pointers, or local names based on clock-names from the device tree binding. This is based on Stephen Boyd's recent work allowing clk drivers to specify clk parents using struct clk_hw * or parsing DT phandles in the clk node. This series can be split into a few major parts: 1) The first patch is a small fix for clk debugfs representation. 2) A bunch of CLK_HW_INIT_* helper macros are added. These cover the situations I encountered, or assume I will encounter, such as single internal (struct clk_hw *) parent, single DT (struct clk_parent_data .fw_name), multiple internal parents, and multiple mixed (internal + DT) parents. A special variant for just an internal single parent is added, CLK_HW_INIT_HWS, which lets the driver share the singular list, instead of having the compiler create a compound literal every time. It might even make sense to only keep this variant. 3) A bunch of CLK_FIXED_FACTOR_* helper macros are added. The rationale is the same as the single parent CLK_HW_INIT_* helpers. 4) Bulk conversion of CLK_FIXED_FACTOR to use local parent references, either struct clk_hw * or DT .fw_name types, whichever the hardware requires. 5) The beginning of SUNXI_CCU_GATE conversion to local parent references. This part is not done. They are included as justification and examples for the shared list of clk parents case." * tag 'sunxi-ng-parent-rewrite-part-1-take-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (25 commits) clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE clk: sunxi-ng: gate: Add macros for referencing local clock parents clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_* clk: sunxi-ng: switch to of_clk_hw_register() for registering clks clk: fixed-factor: Add CLK_FIXED_FACTOR_FW_NAME for DT clock-names parent clk: fixed-factor: Add CLK_FIXED_FACTOR_HWS which takes list of struct clk_hw * ...
2019-06-24Merge tag 'sunxi-clk-for-5.3-201906210814' of ↵Stephen Boyd4-63/+144
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clk driver updates from Maxime Ripard: - A few patches to fix two minor bugs - Introduce a schema for our device tree bindings * tag 'sunxi-clk-for-5.3-201906210814' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: dt-bindings: clk: Convert Allwinner CCU to a schema clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register clk-sunxi: fix a missing-check bug in sunxi_divs_clk_setup()
2019-06-24clk: ti: Use int to check return value from of_property_count_elems_of_size()Stephen Boyd1-4/+5
This function can return a negative number when it fails, but res->sets is at most a u16 which can't hold that negative number. Let's store the result into an int, ret, and then assign that to res->sets when it works to avoid this logical impossibility. Signed-off-by: Stephen Boyd <[email protected]>
2019-06-24Merge tag 'keystone-clk-for-5.3-v2' of ↵Stephen Boyd5-94/+362
git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into clk-ti Pull TI Keystone clk driver changes from Tero Kristo: - Add support for 32 bit clock IDs for sci-clks, this is needed for the new J721e SoC which has a few devices that have more than 255 clocks associated to them. - Clock probing done from DT by default instead of firmware side. Scanning clocks from DT is much faster than firmware, and also we can omit unnecessary clocks which saves even more time. This has been done in the interest of saving boot time. - Remove the device tree node path from the registered sci-clk names. This mainly makes the debugfs interface more readable. - Also contains a single drivers/firmware change which needs to go in via this pull-request; to support the 32bit clock IDs. * tag 'keystone-clk-for-5.3-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux: firmware: ti_sci: extend clock identifiers from u8 to u32 clk: keystone: sci-clk: extend clock IDs to 32 bits clk: keystone: sci-clk: probe clocks from DT instead of firmware clk: keystone: sci-clk: split out the fw clock parsing to own function clk: keystone: sci-clk: cut down the clock name length
2019-06-24Merge tag 'clk-meson-5.3-1' of https://github.com/BayLibre/clk-meson into ↵Stephen Boyd13-32/+1088
clk-meson Pull Amlogic clk driver updates from Jerome Brunet: - Fix mpll fractional part and spread sprectrum issues - Add meson8 audio clocks - Add g12a temperature sensors clocks - Add g12a and g12b cpu clocks * tag 'clk-meson-5.3-1' of https://github.com/BayLibre/clk-meson: clk: meson: g12a: mark fclk_div3 as critical clk: meson: g12a: Add support for G12B CPUB clocks dt-bindings: clk: meson: add g12b periph clock controller bindings clk: meson-g12a: add temperature sensor clocks dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs clk: meson: meson8b: add the cts_i958 clock clk: meson: meson8b: add the cts_mclk_i958 clocks clk: meson: meson8b: add the cts_amclk clocks dt-bindings: clock: meson8b: add the audio clocks clk: meson: g12a: add controller register init clk: meson: eeclk: add init regs clk: meson: g12a: add mpll register init sequences clk: meson: mpll: add init callback and regs clk: meson: axg: spread spectrum is on mpll2 clk: meson: gxbb: no spread spectrum on mpll0 clk: meson: mpll: properly handle spread spectrum clk: meson: meson8b: fix a typo in the VPU parent names array variable clk: meson: fix MPLL 50M binding id typo
2019-06-24clk: imx8mq: Keep uart clocks on during system bootAnson Huang1-0/+10
Call imx_register_uart_clocks() API to keep uart clocks enabled when earlyprintk or earlycon is active. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-06-24clk: imx: Remove __init for imx_register_uart_clocks() APIAnson Huang1-3/+3
Some of i.MX SoCs' clock driver use platform driver model, and they need to call imx_register_uart_clocks() API, so imx_register_uart_clocks() API should NOT be in .init section. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-06-22clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATEChen-Yu Tsai1-14/+23
With the new clk parenting code and SUNXI_CCU_GATE macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing SUNXI_CCU_GATE definitions to SUNXI_CCU_GATE_HWS as the parent clock is internal to this clock unit. To avoid duplication of clock definitions, we fix up the parent reference for A83T in the A83T init function. Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Chen-Yu Tsai <[email protected]>
2019-06-22clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATEChen-Yu Tsai1-12/+20
With the new clk parenting code and SUNXI_CCU_GATE macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing SUNXI_CCU_GATE definitions to SUNXI_CCU_GATE_DATA to specify the parent clock. Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Chen-Yu Tsai <[email protected]>
2019-06-22clk: sunxi-ng: gate: Add macros for referencing local clock parentsChen-Yu Tsai1-0/+53
With the new clk parenting code, clk_init_data was expanded to include .parent_hws, for clk drivers to directly reference parents by clk_hw, and .parent_data, for clk drivers to specify parents using a combination of device tree clock-names, pointers to struct clk_hw, device tree clocks, and/or fallback global clock names. Add four new macros: - SUNXI_CCU_GATE_HW, that can take a struct clk_hw pointer, instead of a string, as its parent. - SUNXI_CCU_GATE_FW that takes a string to match a clock-names entry in the device tree to specify the clock parent. - SUNXI_CCU_GATE_HWS that takes an array of struct clk_hw * as its parent. This allows the array to be shared with other clk declarations. - SUNXI_CCU_GATE_DATA that takes an array of struct clk_parent_data * as its parent. This allows the array to be shared with other clk declarations. Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Chen-Yu Tsai <[email protected]>
2019-06-22clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-1/+1
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Chen-Yu Tsai <[email protected]>
2019-06-22clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-25/+44
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. A forward declaration for struct clk_fixed_factor pll_periph0_4x_clk is added as the definitions of the fixed factor clocks appear much later in the file. The position of fixed factor clock definitions will be moved for all drivers at a later time, before the conversion of all other clock types. Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Chen-Yu Tsai <[email protected]>
2019-06-22clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-15/+26
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Chen-Yu Tsai <[email protected]>
2019-06-22clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-10/+19
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Chen-Yu Tsai <[email protected]>
2019-06-20clk: renesas: cpg-mssr: Use [] to denote a flexible array memberGeert Uytterhoeven1-1/+1
Flexible array members should be denoted using [] instead of [0], else gcc will not warn when they are no longer at the end of the structure. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Simon Horman <[email protected]>
2019-06-20clk: renesas: cpg-mssr: Combine driver-private and clock array allocationGeert Uytterhoeven1-14/+6
Make cpg_mssr_priv.clks[] a flexible array member, and use the new struct_size() helper, to combine the allocation of the driver-private structure and array of available clocks. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Simon Horman <[email protected]>
2019-06-20clk: renesas: mstp: Combine group-private and clock array allocationGeert Uytterhoeven1-6/+6
Make mstp_clock_group.clks[] a flexible array member, and use the new struct_size() helper, to combine the allocation of the group-private structure and array of module clocks. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Simon Horman <[email protected]>
2019-06-20clk: renesas: div6: Combine clock-private and parent array allocationGeert Uytterhoeven1-14/+5
Make div6_clock.parents[] a flexible array member, and use the new struct_size() helper, to combine the allocation of the clock-private structure and array of parent clocks. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Simon Horman <[email protected]>
2019-06-20clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_privGeert Uytterhoeven1-1/+2
New fields were added, but kerneldoc was forgotten, or inserted at the wrong place. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Simon Horman <[email protected]>
2019-06-19clk: samsung: Add bus clock for GPU/G3D on Exynos4412Krzysztof Kozlowski2-0/+2
Add ID and gate for bus clock for GPU (Mali 400) on Exynos4412. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2019-06-18clk: imx6q: fix section mismatch warningArnd Bergmann1-2/+3
The imx6q_obtain_fixed_clk_hw lacks an __init marker, which leads to this otherwise harmless warning: WARNING: vmlinux.o(.text+0x495358): Section mismatch in reference from the function imx6q_obtain_fixed_clk_hw() to the function .init.text:imx_obtain_fixed_clock_hw() The function imx6q_obtain_fixed_clk_hw() references the function __init imx_obtain_fixed_clock_hw(). This is often because imx6q_obtain_fixed_clk_hw lacks a __init annotation or the annotation of imx_obtain_fixed_clock_hw is wrong. Fixes: 992b703b5b38 ("clk: imx6q: Switch to clk_hw based API") Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-06-18clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-1/+1
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Chen-Yu Tsai <[email protected]>
2019-06-18clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-10/+19
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Chen-Yu Tsai <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.