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With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Chen-Yu Tsai <[email protected]>
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With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Chen-Yu Tsai <[email protected]>
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With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Chen-Yu Tsai <[email protected]>
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With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Chen-Yu Tsai <[email protected]>
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With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Chen-Yu Tsai <[email protected]>
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With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Chen-Yu Tsai <[email protected]>
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With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.
Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Chen-Yu Tsai <[email protected]>
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With the new clk parenting code and CLK_HW_INIT_* macros, we can
reference parents locally via pointers to struct clk_hw or DT
clock-names.
Convert existing CLK_HW_INIT_* definitions to describe parents using
either struct clk_hw pointers or clock-names from the device tree
binding.
For the AR100, this also allows us to merge the generic AR100 and the
A83T specific one, which only differed in the global clock names for
their parent clocks. The device tree bindings used the same name
specifiers.
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Chen-Yu Tsai <[email protected]>
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Commit 89a5ddcc799d ("clk: Add of_clk_hw_register() API for early clk
drivers") introduces a new API for registering clks, which allows the
user to directly specify a device node, even if there is no struct
device attached to it. The device node is used for local DT clock-names
matching.
Switch to of_clk_hw_register() so that local DT clock-names matching
works.
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Chen-Yu Tsai <[email protected]>
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With the new clk parenting code, clk_init_data was expanded to include
.parent_data, for clk drivers to specify parents using a combination of
device tree clock-names, pointers to struct clk_hw, device tree clocks,
and/or fallback global clock names.
Add a new macro, CLK_FIXED_FACTOR_FW_NAME, that takes a string to match
a clock-names entry in the device tree to specify the clock parent.
Signed-off-by: Chen-Yu Tsai <[email protected]>
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With the new clk parenting code, clk_init_data was expanded to include
.parent_hws, for clk drivers to directly reference parents by clk_hw.
Add a new macro, CLK_FIXED_FACTOR_HWS, that can take an array of pointers
to struct clk_hw, instead of a string, as its parent. Taking an array
instead of a direct pointer allows the reuse of the array for multiple
clks, rather than having one compound literal with the same contents
allocated for each clk declaration.
Signed-off-by: Chen-Yu Tsai <[email protected]>
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With the new clk parenting code, clk_init_data was expanded to include
.parent_hws, for clk drivers to directly reference parents by clk_hw.
Add a new macro, CLK_FIXED_FACTOR_HW, that can take a struct clk_hw
pointer, instead of a string, as its parent.
Signed-off-by: Chen-Yu Tsai <[email protected]>
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With the new clk parenting code, struct clk_init_data was expanded to
include .parent_data, for clk drivers that have parents referenced using
a combination of device tree clock-names, clock indices, and/or struct
clk_hw pointers.
Add a new macro that can take a list of struct clk_parent_data for
drivers to use.
Signed-off-by: Chen-Yu Tsai <[email protected]>
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With the new clk parenting code, clk_init_data was expanded to include
.parent_data, for clk drivers that have parents referenced using a
combination of device tree clock-names, clock indices, and/or clk_hw
pointers.
Add a CLK_HW_INIT macro for specifying a single parent from the device
tree using .fw_name in struct clk_parent_data.
Signed-off-by: Chen-Yu Tsai <[email protected]>
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With the new clk parenting code, struct clk_init_data was expanded to
include .parent_hws, for clk drivers to directly list parents by
pointing to their respective struct clk_hw's.
Add macros that can take either one single struct clk_hw *, or an array
of them, for drivers to use.
A special CLK_HW_INIT_HWS macro is included, which takes an array of
struct clk_hw *, but sets .num_parents to 1. This variant is to allow
the reuse of the array, instead of having a compound literal allocated
for each clk sharing the same parent.
Signed-off-by: Chen-Yu Tsai <[email protected]>
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Following the commit fc0c209c147f ("clk: Allow parents to be specified
without string names"), the parent name string is not always populated.
Instead, fetch the parents clk_core struct using the appropriate helper,
and read its name directly. If that fails, go through the possible
sources of parent names. The order in which they are used is different
from how parents are looked up, with the global name having precedence
over local fw_name and indices. This makes more sense as a) the
parent_maps structure does not differentiate between legacy global names
and fallback global names, and b) global names likely provide more
information than local fw_names.
Fixes: fc0c209c147f ("clk: Allow parents to be specified without string names")
Signed-off-by: Chen-Yu Tsai <[email protected]>
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This patch adds the TMU clocks to the R8A774A1 SoC.
Signed-off-by: Fabrizio Castro <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Add clock definitions for CMM units on Renesas R-Car D3.
Signed-off-by: Jacopo Mondi <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Add clock definitions for CMM units on Renesas R-Car E3.
Signed-off-by: Jacopo Mondi <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Add clock definitions for CMM units on Renesas R-Car M3-N.
Signed-off-by: Jacopo Mondi <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Add clock definitions for CMM units on Renesas R-Car H3.
Signed-off-by: Jacopo Mondi <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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i.MX8MQ clock driver uses platform driver model, better to use
devm_platform_ioremap_resource() instead of of_iomap() to get
IO base.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Use imx_check_clocks() API to check clocks directly.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Some of i.MX SoCs' clock driver use platform driver model,
and they need to call imx_check_clocks() API, so
imx_check_clocks() API should NOT be in .init section.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Building COMMON_CLK_XGENE is pointless, unless we're building for
an XGENE system.
Signed-off-by: Marc Gonzalez <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Future SoCs are going to have more than 255 device clocks in certain cases,
and thus the API must be extended to support this. The support is done in
backwards compatible extension, in which the new u32 clock identifier
fields are only used if the existing u8 size clock identifier is set as
255. In all the other cases, the existing u8 clock identifier is used. As
the size of the messages sent / received is not verified for existing
devices / old firmware, increasing the size of the messages from the end
is also fine. Due to this reason, depending on ABI version isn't necessary
either.
Acked-by: Santosh Shilimkar <[email protected]>
Signed-off-by: Tero Kristo <[email protected]>
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On Amlogic Meson G12b platform, the fclk_div3 seems to be necessary for
the system to operate correctly.
Disabling it cause the entire system to freeze, including peripherals.
Let's mark this clock as critical, fixing boot on G12b platforms.
Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
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Update the Meson G12A Clock driver to support the Amlogic G12B SoC.
G12B clock driver is very close, the main differences are :
- the clock tree is duplicated for the both clusters, and the
SYS_PLL are swapped between the clusters
- G12B has additional clocks like for CSI an other components
Here only the cpu clock tree is handled.
Reviewed-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
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Update the documentation to support clock driver for the Amlogic G12B SoC.
G12B clock driver is very close, the main differences are :
- the clock tree is duplicated for the both clusters, and the
SYS_PLL are swapped between the clusters
- G12B has additional clocks like for CSI an other components
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
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Add the TS clocks used by two temperature sensors
Reviewed-by: Martin Blumenstingl<[email protected]>
Signed-off-by: Guillaume La Roque <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]> [fixed commit description]
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Add clock ids used by the temperature sensors of the G12A Socs
Reviewed-by: Martin Blumenstingl <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Guillaume La Roque <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]> [fixed commit message]
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Add the cts_i958 clock to control the clock source of the spdif output
block. It is used to select whether the clock source of the spdif output
is cts_amclk (when data are taken from i2s buffer) or the cts_mclk_i958
(when data are taken from the spdif buffer). The setup for this clock is
identical to GXBB, so this ports commit 7eaa44f6207fb6 ("clk: meson:
gxbb: add cts_i958 clock") to the Meson8/Meson8b/Meson8m2 clock driver.
Signed-off-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
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Add the SPDIF master clock also referred as cts_mclk_i958. The setup for
this clock is identical to GXBB, so this ports commit 3c277c247eabeb
("clk: meson: gxbb: add cts_mclk_i958") to the Meson8/Meson8b/Meson8m2
clock driver.
Signed-off-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
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Add the I2S master clock also referred as cts_amclk. The setup for this
clock is identical to GXBB, so this ports commit 4087bd4b21702d ("clk:
meson: gxbb: add cts_amclk") to the Meson8/Meson8b/Meson8m2 clock
driver.
Signed-off-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
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The audio controllers on Meson8, Meson8b and Meson8m2 use similar
(potentially the same) audio clocks as GXBB, GXL and GXM. Add the
CLKID_CTS_AMCLK, CLKID_CTS_MCLK_I958 and CLKID_CTS_I958 clock IDs so
they can be used for the audio controllers.
Signed-off-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
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Enabling PCIe requires several of the PCIe related resets from GCC, so
add them all.
Reviewed-by: Niklas Cassel <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Reviewed-by: Vinod Koul <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Failing to toggle a GDSC as the driver core is attaching the
power-domain to a device will cause a silent probe deferral. Provide an
explicit warning to the developer, in order to reduce the amount of time
it takes to debug this.
Signed-off-by: Bjorn Andersson <[email protected]>
Reviewed-by: Jeffrey Hugo <[email protected]>
Tested-by: Jeffrey Hugo <[email protected]>
Reviewed-by: Marc Gonzalez <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Fixes gcc '-Wunused-but-set-variable' warning:
drivers/clk/mmp/clk-frac.c: In function clk_factor_set_rate:
drivers/clk/mmp/clk-frac.c:81:16: warning: variable prev_rate set but not used [-Wunused-but-set-variable]
It's never used and can be removed.
Signed-off-by: YueHaibing <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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They are not used any more since
commit 7558562a70fb ("clk: ti: Drop legacy clk-3xxx-legacy code")
Reported-by: Hulk Robot <[email protected]>
Suggested-by: Tero Kristo <[email protected]>
Signed-off-by: YueHaibing <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Variable 'ddrphycfg_parents' is defined static and initialized, but not
used in the file.
../drivers/clk/mediatek/clk-mt8516.c:234:27: warning: ‘ddrphycfg_parents’ defined but not used [-Wunused-const-variable=]
static const char * const ddrphycfg_parents[] __initconst = {
^~~~~~~~~~~~~~~~~
Signed-off-by: Philippe Mazenauer <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The code was setting the bit 21 of the CPCCR register to use a divider
of 2 for the "pll half" clock, and clearing the bit to use a divider
of 1.
This is the opposite of how this register field works: a cleared bit
means that the /2 divider is used, and a set bit means that the divider
is 1.
Restore the correct behaviour using the newly introduced .div_table
field.
Signed-off-by: Paul Cercueil <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The main clocks (cclk, hclk, pclk, mclk, ipu) were using
incorrect dividers, and thus reported an incorrect rate.
Signed-off-by: Paul Cercueil <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using
incorrect dividers, and thus reported an incorrect rate.
Signed-off-by: Paul Cercueil <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The main clocks (cclk, hclk, pclk, mclk, lcd) were using
incorrect dividers, and thus reported an incorrect rate.
Signed-off-by: Paul Cercueil <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Some clocks provided on Ingenic SoCs have dividers, whose hardware value
as written in the register cannot be expressed as an affine function
to the actual divider value.
For instance, for the CPU clock on the JZ4770, the dividers are coded as
follows:
------------------
| Bits | Div |
------------------
| 0 0 0 | 1 |
| 0 0 1 | 2 |
| 0 1 0 | 3 |
| 0 1 1 | 4 |
| 1 0 0 | 6 |
| 1 0 1 | 8 |
| 1 1 0 | 12 |
------------------
To support this setup, we introduce a new field in the
ingenic_cgu_div_info structure that allows to specify the divider table.
Signed-off-by: Paul Cercueil <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add TPU (Timer Pulse Unit / PWM) clocks on R-Car H3, M3-W, and M3-N
- Add CMM (Color Management Module) clocks on R-Car M3-W
- Add Clock Domain support on RZ/N1
* tag 'clk-renesas-for-v5.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r9a06g032: Add clock domain support
dt-bindings: clock: renesas: r9a06g032-sysctrl: Document power Domains
clk: renesas: mstp: Remove error messages on out-of-memory conditions
clk: renesas: cpg-mssr: Remove error messages on out-of-memory conditions
clk: renesas: cpg-mssr: Use genpd of_node instead of local copy
clk: renesas: r8a7796: Add CMM clocks
clk: renesas: r8a779{5|6|65}: Add TPU clock
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Currently, the clock identifiers are limited to 255. To support future
SoCs, this muse be extended to 32 bits, which should provide way more
than enough space. Basic support for extending the clock API is going
to be implemented in the firmware driver, but there are some minor
changes that need to be done on the clock driver side first.
Acked-by: Santosh Shilimkar <[email protected]>
Signed-off-by: Tero Kristo <[email protected]>
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