| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
The A20 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>
|
|
The A31 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>
|
|
The A10s and A13 gates have a non continuous set of clock IDs that are
valid. Add the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>
|
|
The A10 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
The i.MX clock updates for 4.3:
- Provide a better IPU clock initial settings on imx6dl for getting
HDMI and LVDS at the same time.
- Add clock driver support for i.MX6UL SoC
- Add a second clock for RTC device on i.MX31 and i.MX35
|
|
The patch was generated using fixed coccinelle semantic patch
scripts/coccinelle/api/memdup.cocci [1].
[1]: http://permalink.gmane.org/gmane.linux.kernel/2014320
Signed-off-by: Andrzej Hajda <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
The imx35 don't define clocks for rtc.
This patch add two clocks, as needed
by the mxc rtc driver.
Signed-off-by: Philippe Reynes <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
|
|
The mxc rtc driver needs two clock.
It was defined only one clock, so we
define the second clock.
Signed-off-by: Philippe Reynes <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
|
|
*of_iomap()* will check the device node pointer, and if the pointer is
NULL it will return error code. So refine clock's init flow by checking
the device node with this simple way; and polish a little for the print
out message.
Signed-off-by: Leo Yan <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
The ">" should be ">=" or we end up reading beyond the end of the array.
Fixes: 6e973d2c4385 ('clk: vexpress: Add separate SP810 driver')
Signed-off-by: Dan Carpenter <[email protected]>
Acked-by: Pawel Moll <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
However TSADC is present only on Exynos4210 so on Trats2 board (with
Exynos4412 SoC) the exynos-adc driver could not be probed:
ERROR: could not get clock /adc@126C0000:adc(0)
exynos-adc 126c0000.adc: failed getting clock, err = -2
exynos-adc: probe of 126c0000.adc failed with error -2
Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
Converter is located in different register and it is named in datasheet
as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
is the same as purpose of TSADC from Exynos4210.
The patch adds gate clock for Exynos4x12 using the proper register so
backward compatibility is preserved. This fixes the probe of exynos-adc
driver on Exynos4x12 boards and allows accessing sensors connected to it
on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Cc: <[email protected]>
Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
Reviewed-by: Javier Martinez Canillas <[email protected]>
Acked-by: Tomasz Figa <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
set_irq_flags is ARM specific with custom flags which have genirq
equivalents. Convert drivers to use the genirq interfaces directly, so we
can kill off set_irq_flags. The translation of flags is as follows:
IRQF_VALID -> !IRQ_NOREQUEST
IRQF_PROBE -> !IRQ_NOPROBE
IRQF_NOAUTOEN -> IRQ_NOAUTOEN
For IRQs managed by an irqdomain, the irqdomain core code handles clearing
and setting IRQ_NOREQUEST already, so there is no need to do this in
.map() functions and we can simply remove the set_irq_flags calls. Some
users also modify IRQ_NOPROBE and this has been maintained although it
is not clear that is really needed. There appears to be a great deal of
blind copy and paste of this code.
Signed-off-by: Rob Herring <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Cc: Mike Turquette <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Cc: [email protected]
Signed-off-by: Stephen Boyd <[email protected]>
|
|
The array of parent names can be made as array of const pointers to
const strings.
Signed-off-by: Jun Nie <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
Add SPDIF/I2S and GPIO clock for zx296702
Signed-off-by: Jun Nie <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
Add SPDIF/I2S divider clock method for zx296702
Signed-off-by: Jun Nie <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
This patch cleans up the driver for,
- Use devm_kcalloc() variant instead of devm_kzalloc() for array
allocation.
- clk_prepare()/unprepare(), remove "ret" variable as it is not required
- use __exit for cleanup function
As I am referring this driver as a reference for my 88pm800 clk driver,
applying same changes here as well.
Signed-off-by: Vaibhav Hiremath <[email protected]>
Tested-by: Anand Moon <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
The recursive spinlock implementation trips up sparse and it
complains that these functions have lock imbalances. That isn't
really true though, so add some __acquires() and __releases()
information so that sparse is quiet.
drivers/clk/clk.c:116:22: warning: context imbalance in 'clk_enable_lock' - wrong count at exit
drivers/clk/clk.c:141:9: warning: context imbalance in 'clk_enable_unlock' - unexpected unlock
Signed-off-by: Stephen Boyd <[email protected]>
|
|
The basic clock types use conditional locking for the register
accessor spinlocks. Add __acquire() and __release() markings in
the right locations so that sparse isn't tripped up on the
conditional locking.
drivers/clk/clk-mux.c:68:12: warning: context imbalance in 'clk_mux_set_parent' - different lock contexts for basic block
drivers/clk/clk-divider.c:379:12: warning: context imbalance in 'clk_divider_set_rate' - different lock contexts for basic block
drivers/clk/clk-gate.c:71:9: warning: context imbalance in 'clk_gate_endisable' - different lock contexts for basic block
drivers/clk/clk-fractional-divider.c:36:9: warning: context imbalance in 'clk_fd_recalc_rate' - different lock contexts for basic block
drivers/clk/clk-fractional-divider.c:68:12: warning: context imbalance in 'clk_fd_set_rate' - different lock contexts for basic block
Cc: Andy Shevchenko <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
The missing license causes the clk-qcom.ko module to taint the
kernel. Add the appropriate license to avoid taint.
Signed-off-by: Stephen Boyd <[email protected]>
|
|
Let's encourage const arrays of parent names like other basic
clock types.
Cc: Sergej Sawazki <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into clk-next
|
|
This commit allows certain Broadcom STB clock dividers to be used with
clk-divider.c. It allows for a clock whose field value is the equal
to the divisor, execpt when the field value is zero, in which case the
divisor is 2^width. For example, consider a divisor clock with a two
bit field:
value divisor
0 4
1 1
2 2
3 3
Signed-off-by: Jim Quinlan <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>
|
|
Convert the code to use GENMASK() helper instead of div_mask() macro.
Signed-off-by: Andy Shevchenko <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
Legacy drivers which are not yet ported, such as cpufreq-pxa[23]xx, rely
on pxaXXx_get_clk_frequency_khz() to find the CPU core frequency.
This reporting was broken because the expected unit is kHz and not
Hz. Fix the reporting for pxa25x, pxa27x and pxa3xx.
Fixes: fe7710fae477 ("clk: add pxa25x clock drivers")
Fixes: d40670dc6169 ("clk: add pxa27x clock drivers")
Fixes: 9bbb8a338fb2 ("clk: pxa: add pxa3xx clock driver")
Signed-off-by: Robert Jarzmik <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
In the TRM we see that BWADJ is "a 12-bit bus that selects the values
1-4096 for the bandwidth divider (NB)":
NB = BWADJ[11:0] + 1
The recommended setting of NB: NB = NF / 2.
So:
NB = NF / 2
BWADJ[11:0] + 1 = NF / 2
BWADJ[11:0] = NF / 2 - 1
Right now, we have:
{ \
.rate = _rate##U, \
.nr = _nr, \
.nf = _nf, \
.no = _no, \
.bwadj = (_nf >> 1), \
}
That means we set bwadj to NF / 2, not NF / 2 - 1
All of this is a bit confusing because we specify "NR" (the 1-based
value), "NF" (the 1-based value), "NO" (the 1-based value), but
"BWADJ" (the 0-based value) instead of "NB" (the 1-based value).
Let's change to working with "NB" and fix the off by one error. This
may affect PLL jitter in a small way (hopefully for the better).
Signed-off-by: Douglas Anderson <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
* cleanup-clk-h-includes: (62 commits)
clk: Remove clk.h from clk-provider.h
clk: h8300: Remove clk.h and clkdev.h includes
clk: at91: Include clk.h and slab.h
clk: ti: Switch clk-provider.h include to clk.h
clk: pistachio: Include clk.h
clk: ingenic: Include clk.h
clk: si570: Include clk.h
clk: moxart: Include clk.h
clk: cdce925: Include clk.h
clk: Include clk.h in clk.c
clk: zynq: Include clk.h
clk: ti: Include clk.h
clk: sunxi: Include clk.h and remove unused clkdev.h includes
clk: st: Include clk.h
clk: qcom: Include clk.h
clk: highbank: Include clk.h
clk: bcm: Include clk.h
clk: versatile: Remove clk.h and clkdev.h includes
clk: ux500: Remove clk.h and clkdev.h includes
clk: tegra: Properly include clk.h
...
|
|
Use of_clk_parent_fill to fill in the parent clock names' array.
Signed-off-by: Dinh Nguyen <[email protected]>
Cc: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
Use of_clk_parent_fill to fill in the parent clock names' array.
Signed-off-by: Dinh Nguyen <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Cc: "Emilio López" <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
Use of_clk_parent_fill to fill in the parent clock names' array.
Signed-off-by: Dinh Nguyen <[email protected]>
Tested-by Gabriel Fernandez <[email protected]>
Cc: Peter Griffin <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
Use of_clk_parent_fill to fill in the parent clock names' array.
Signed-off-by: Dinh Nguyen <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
Use of_clk_parent_fill to fill in the parent clock names' array.
Signed-off-by: Dinh Nguyen <[email protected]>
Cc: Boris Brezillon <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting by adding
div-rate table to lookup suitable post divider setting under a
specified frequency.
Signed-off-by: James Liao <[email protected]>
Acked-by: Sascha Hauer <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
Avoid u32 overflow when calculate post divider setting, and
increase the max post divider setting from 3 (/8) to 4 (/16).
Signed-off-by: James Liao <[email protected]>
Acked-by: Sascha Hauer <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
Write postdiv and pcw settings at the same time for PLLs if postdiv
and pcw settings are on the same register.
This is need by PLLs such as MT8173 MMPLL and ARM*PLL.
Signed-off-by: James Liao <[email protected]>
Acked-by: Sascha Hauer <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
clk providers are using the consumer APIs to set min/max rates on
the clock they're providing. To encourage clk providers to move
away from the consumer APIs, add a provider API to set the
min/max rate of a clock. The assumption is that this is done
before the clock can be requested via clk_get() and that the
clock rate is already within the boundaries of the min/max that's
configured.
Tested-by: Sudeep Holla <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
Use devm_clk_register() to simplify the code by removing
twl6040_clk_remove().
Signed-off-by: Axel Lin <[email protected]>
Acked-by: Peter Ujfalusi <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
The devm_clk_unregister() in .probe error case is not necessary as it will
be automatically called when probe fails.
Signed-off-by: Axel Lin <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
The CCF implementations for the various shmobile SoCs don't use clkdev
functionality, hence drop the inclusion of <linux/clkdev.h>.
Add the missing #include <linux/slab.h>, which was included implicitly
through <asm/clkdev.h> before.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
Add __force here so that sparse doesn't complain about us playing
tricks with __iomem.
Acked-by: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
Sparse complains about these structures missing static, but they
also don't look to be used. Remove them.
drivers/clk/ti/clk-3xxx.c:74:30: warning: symbol 'clkhwops_omap3430es2_ssi_wait' was not declared. Should it be static?
drivers/clk/ti/clk-3xxx.c:157:30: warning: symbol 'clkhwops_omap3430es2_hsotgusb_wait' was not declared. Should it be static?
Acked-by: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
This variable isn't exported outside of this file so mark it
static. Silences the following sparse warning:
drivers/clk/ti/clk.c:36:24: warning: symbol 'ti_clk_features' was not declared. Should it be static?
Acked-by: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
smatch reports a failure to check kzalloc() here:
drivers/clk/ti/clk.c:232
omap2_clk_provider_init() error: potential null dereference 'io'.
(kzalloc returns null)
Check for an allocation failure and return -ENOMEM.
Acked-by: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
into clk-next
From Tero Kristo:
"This pull request contains the TI clock driver set to move the
clock implementations under clock driver. Some small portions of
the clock driver code still remain under mach-omap2 after this,
it should be decided whether this code is now obsolete and should
be deleted or should someone try to fix it."
Slight merge conflicts with determine_rate prototype changes.
|
|
of_clk_get_parent_count() may return negative error code, so num_parents
needs to be int rather than unsigned int.
Signed-off-by: Axel Lin <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
The other ce clocks have the flag set, but ce1 doesn't, so
clk_set_rate() doesn't propagate up the tree to the ce1_src_clk.
Set the flag as this is supported.
Reported-by: Bjorn Andersson <[email protected]>
Tested-by: Bjorn Andersson <[email protected]>
Fixes: 02824653200b ("clk: qcom: Add APQ8084 Global Clock Controller support")
Fixes: d33faa9ead8d ("clk: qcom: Add support for MSM8974's global clock controller (GCC)")
Signed-off-by: Stephen Boyd <[email protected]>
|
|
We don't unlock the mutex if we fail to allocate the parent names
array. Unlock it and return an error in this case as well.
Reported-by: kbuild test robot <[email protected]>
Acked-by: Julia Lawall <[email protected]>
Cc: Sergej Sawazki <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
There doesn't seem to be any reason why we can't use the standard
readb()/writeb() accessors here because ctrl_inb() and
ctrl_outb() match the generic implementation of readb() and
writeb() that the h8300 architecture uses. This allows us to test
compile this driver on other architectures besides h8300.
Cc: Yoshinori Sato <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
We don't need to print an error on allocation failures, drop it.
While we're here, change the sizeof() to be sizeof(*<ptr>) to
make code more future proof.
Cc: Yoshinori Sato <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
* clk-determine-rate-struct:
clk: fix some determine_rate implementations
clk: change clk_ops' ->determine_rate() prototype
|
|
Some determine_rate implementations are not returning an error
when they failed to adapt the rate according to the rate request.
Fix them so that they return an error instead of silently
returning 0.
Signed-off-by: Boris Brezillon <[email protected]>
CC: Jonathan Corbet <[email protected]>
CC: Tony Lindgren <[email protected]>
CC: Ralf Baechle <[email protected]>
CC: "Emilio López" <[email protected]>
CC: Maxime Ripard <[email protected]>
Cc: Tero Kristo <[email protected]>
CC: Peter De Schrijver <[email protected]>
CC: Prashant Gaikwad <[email protected]>
CC: Stephen Warren <[email protected]>
CC: Thierry Reding <[email protected]>
CC: Alexandre Courbot <[email protected]>
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]
Signed-off-by: Stephen Boyd <[email protected]>
|