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2015-07-20simplefb: Include clk.hStephen Boyd1-0/+1
This driver uses the consumer API, so include clk.h explicitly instead of impliclty through the provider API. Cc: Luc Verhaegen <[email protected]> Cc: Hans de Goede <[email protected]> Acked-by: Geert Uytterhoeven <[email protected]> Cc: Maxime Ripard <[email protected]> Cc: David Herrmann <[email protected]> Cc: Tomi Valkeinen <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-20ACPI: Remove clk.h includeStephen Boyd2-2/+0
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Remove the includes here because these are a provider drivers. Cc: Ken Xue <[email protected]> Cc: Mika Westerberg <[email protected]> Cc: Rafael J. Wysocki <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-20clocksource: cadence_ttc: Remove clk-provider.h includeStephen Boyd1-1/+0
This file doesn't use the clk provider APIs. Remove the include. Cc: Michal Simek <[email protected]> Cc: Daniel Lezcano <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-20spi: spi-pxa2xx: Remove clk.h includeStephen Boyd1-1/+0
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Remove the include here because this is a provider driver. Cc: Daniel Mack <[email protected]> Cc: Haojian Zhuang <[email protected]> Cc: Robert Jarzmik <[email protected]> Cc: Mark Brown <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-20staging: clocking-wizard: Include clk.hStephen Boyd1-0/+1
This clock provider uses the consumer API, so include clk.h explicitly. Acked-by: Sören Brinkmann <[email protected]> Acked-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-20powerpc/512x: clk: Include clk.hStephen Boyd1-0/+1
This clock provider uses the consumer API, so include clk.h explicitly. Cc: Gerhard Sittig <[email protected]> Cc: Scott Wood <[email protected]> Acked-by: Anatolij Gustschin <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-20MIPS: Alchemy: Include clk.hStephen Boyd1-0/+1
This clock provider uses the consumer API, so include clk.h explicitly. Cc: Manuel Lauss <[email protected]> Acked-by: Ralf Baechle <[email protected]> Cc: Linux-MIPS <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-20arm64: Remove clk-provider.h includeStephen Boyd1-1/+0
This file doesn't use the clk provider APIs. Remove the include. Acked-by: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-20ARM: OMAP2+: Include clk.hStephen Boyd3-0/+3
These files use the consumer API, so include clk.h explicitly. Acked-by: Tero Kristo <[email protected]> Cc: Tony Lindgren <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-20ARM: s3c64xx: Remove clk-provider.h includeStephen Boyd1-1/+0
This file doesn't use the clk provider APIs. Remove the include. Signed-off-by: Stephen Boyd <[email protected]>
2015-07-20ARM: orion5x: Remove clk-provider.h includeStephen Boyd1-1/+0
This file doesn't use the clk provider APIs. Remove the include. Cc: Thomas Petazzoni <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-20ARM: mvebu: Remove clk-provider.h includeStephen Boyd1-1/+0
This file doesn't use the clk provider APIs. Remove the include. Cc: Thomas Petazzoni <[email protected]> Cc: Gregory CLEMENT <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-20ARM: keystone: Remove clk-provider.h includeStephen Boyd1-1/+0
This file doesn't use the clk provider APIs. Remove the include. Cc: Nishanth Menon <[email protected]> Cc: Sekhar Nori <[email protected]> Acked-by: Santosh Shilimkar <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-20ARM: hisi: Remove clk-provider.h includeStephen Boyd1-1/+0
This file doesn't use the clk provider APIs. Remove the include. Cc: Haojian Zhuang <[email protected]> Cc: Wei Xu <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-20ARM: at91: Remove clk-provider.h includeStephen Boyd1-1/+0
This file doesn't use the clk provider APIs. Remove the include. Acked-by: Alexandre Belloni <[email protected]> Cc: Boris Brezillon <[email protected]> Cc: Nicolas Ferre <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-14clk: imx: add imx6ul clk tree supportFrank Li3-0/+673
Add imx6ul clock driver support. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Bai Ping <[email protected]> Signed-off-by: Fugang Duan <[email protected]> Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2015-07-13clk: st: Fix error paths and allocation styleStephen Boyd1-38/+45
The error paths in this file leak memory and mappings and test for pointers being valid after dereferencing them. Fix these problems and properly free resources on errors. Fix some stylistic things too like using sizeof(*ptr) and fitting more code on a single line. Note that we don't unregister clocks here. That needs a clk_composite_unregister() API that we don't have right now. Acked-by: Gabriel Fernandez <[email protected]> Cc: Pankaj Dev <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-13clk: imx: clk-imx6q: Provide initial IPU clock settings for mx6dlFabio Estevam1-0/+4
Currently it is not possible to use HDMI and LVDS at the same time on a imx6dl-sabresd board. Fix this usecase by setting IMX6QDL_CLK_PLL3_PFD1_540M to 540MHz and also by setting it as the parent of IMX6QDL_CLK_IPU1_SEL. Based on the configuration done in the FSL kernel. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2015-07-07Merge branch 'clk-fixes' into clk-nextStephen Boyd1-1/+1
* clk-fixes: drivers: clk: st: Incorrect register offset used for lock_status
2015-07-07clk: Move clk_provider_list to scope of function using itStephen Boyd1-2/+1
The list isn't used after of_clk_init() is called, so we don't need to keep an empty list around after init. Put the list on the stack. Cc: Gregory CLEMENT <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-07clk: Check for allocation errors in of_clk_init()Stephen Boyd1-2/+11
Dan Carpenter reports that we don't check the allocation here for failure. Add a failure check and free any previously allocated providers from the clk_provider_list. Reported-by: Dan Carpenter <[email protected]> Cc: Gregory CLEMENT <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-07Merge branch 'clk-rk3368' into clk-nextStephen Boyd14-16/+1555
* clk-rk3368: clk: rockchip: add rk3368 clock controller clk: rockchip: add missing include guards clk: rockchip: add dt-binding header for rk3368 dt-bindings: add documentation of rk3668 clock controller clk: rockchip: define the inverters of rk3066/rk3188 and rk3288 clk: rockchip: fix issues in the mmc-phase clock clk: rockchip: add support for phase inverters clk: rockchip: add COMPOSITE_NOGATE_DIVTBL variant clk: rockchip: protect register macros against multipart values clk: rockchip: fix faulty vip parent name on rk3288 clk: rockchip: rk3288: add CLK_SET_RATE_PARENT to sclk_mac
2015-07-07clk: qcom: Add support for SR2 PLLsGeorgi Djakov2-0/+76
Add support for SR2 type pll operations. SR2 is optimized for Time Interval Error (TIE) or absolute jitter. Signed-off-by: Georgi Djakov <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-07clk: at91: Silence warnings and cleanup __init/extern usageStephen Boyd1-66/+58
Remove useless ifdefs around function prototypes to silence the following sparse warnings when the configs aren't enabled. drivers/clk/at91/clk-h32mx.c:95:13: warning: symbol 'of_sama5d4_clk_h32mx_setup' was not declared. Should it be static? drivers/clk/at91/clk-utmi.c:159:13: warning: symbol 'of_at91sam9x5_clk_utmi_setup' was not declared. Should it be static? Plus, using __init and extern in function prototypes doesn't do anything, so just drop it throughout this file. Acked-by: Boris BREZILLON <[email protected]> Acked-by: Alexandre Belloni <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-07drivers: clk: st: Incorrect register offset used for lock_statusPankaj Dev1-1/+1
Incorrect register offset used for sthi407 clockgenC Signed-off-by: Pankaj Dev <[email protected]> Signed-off-by: Gabriel Fernandez <[email protected]> Fixes: 51306d56ba81 ("clk: st: STiH407: Support for clockgenC0") Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: qcom: Constify the parent names arraysGeorgi Djakov11-67/+67
Make const both the array and the strings, so they can be moved to .rodata section. Signed-off-by: Georgi Djakov <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: xgene: Delete duplicated name fieldMatthias Brugger1-15/+13
X-Gene clocks implement it's name in the clock private struct. This is a duplication of the name field. We can delete the field and rely on the common implementation to retrieve the name. Signed-off-by: Matthias Brugger <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: Rename clk-gpio-gate.c to clk-gpio.cSergej Sawazki2-1/+1
The file clk-gpio-gate.c does not only contain the gate clock, but also the mux clock. Rename the file to clk-gpio.c. Cc: Jyri Sarha <[email protected]> Signed-off-by: Sergej Sawazki <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: add gpio controlled clock multiplexerSergej Sawazki3-64/+214
Add a common clock driver for basic gpio controlled clock multiplexers. This driver can be used for devices like 5V41068A or 831721I from IDT or for discrete multiplexer circuits. The 'select' pin selects one of two parent clocks. Cc: Jyri Sarha <[email protected]> Signed-off-by: Sergej Sawazki <[email protected]> [[email protected]: Fix error paths to free memory and do it in the correct order] Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: gpio-gate: Stay silent on EPROBE_DEFERSergej Sawazki1-2/+3
Do not output an error message if requesting gpio failes with EPROBE_DEFER. Cc: Jyri Sarha <[email protected]> Signed-off-by: Sergej Sawazki <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: gpio-gate: Include export.h instead of module.hSergej Sawazki1-1/+1
Include export.h for EXPORT_SYMBOL_GPL, no need to include module.h. Cc: Jyri Sarha <[email protected]> Signed-off-by: Sergej Sawazki <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06Merge branch 'clk-fixes' into clk-nextStephen Boyd15-49/+73
* clk-fixes: clk: mediatek: mt8173: Fix enabling of critical clocks drivers: clk: st: Fix mux bit-setting for Cortex A9 clocks drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocks drivers: clk: st: Fix flexgen lock init drivers: clk: st: Fix FSYN channel values drivers: clk: st: Remove unused code clk: qcom: Use parent rate when set rate to pixel RCG clock clk: at91: do not leak resources clk: stm32: Fix out-by-one error path in the index lookup clk: iproc: fix bit manipulation arithmetic clk: iproc: fix memory leak from clock name
2015-07-06clk: mediatek: mt8173: Fix enabling of critical clocksSascha Hauer1-5/+21
On the MT8173 the clocks are provided by different units. To enable the critical clocks we must be sure that all parent clocks are already registered, otherwise the parents of the critical clocks end up being unused and get disabled later. To find a place where all parents are registered we try each time after we've registered some clocks if all known providers are present now and only then we enable the critical clocks Signed-off-by: Sascha Hauer <[email protected]> Signed-off-by: James Liao <[email protected]> [[email protected]: Marked function and data __init] Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: rockchip: add rk3368 clock controllerHeiko Stuebner3-0/+898
Describe the clock tree and software resets of the rk3368 ARM64 SoC Signed-off-by: Heiko Stuebner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: rockchip: add missing include guardsHeiko Stuebner4-0/+20
Review for the rk3368 turned up that the clock header was missing include guards. This is also true for the already existing clock binding headers, so add them. Signed-off-by: Heiko Stuebner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: rockchip: add dt-binding header for rk3368Heiko Stuebner1-0/+384
Add the dt-bindings header for the rk3368, that gets shared between the clock controller and the clock references in the dts. Signed-off-by: Heiko Stuebner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06dt-bindings: add documentation of rk3668 clock controllerHeiko Stuebner1-0/+61
Add the devicetree binding for the cru on the rk3368 which quite similar structured as previous clock controllers. Signed-off-by: Heiko Stuebner <[email protected]> Cc: Rob Herring <[email protected]> Cc: Pawel Moll <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Ian Campbell <[email protected]> Cc: Kumar Gala <[email protected]> Cc: [email protected] Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: rockchip: define the inverters of rk3066/rk3188 and rk3288Heiko Stuebner2-2/+14
Both soc series' have inverters on the hsadc and camera interface clock paths. So define them using the newly added inverter type. Signed-off-by: Heiko Stuebner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: rockchip: fix issues in the mmc-phase clockHeiko Stuebner1-3/+3
The review for the new inverter clock type uncovered some issues (missing headers and name handling) that are also present in the mmc-phase clock type, I got (to much) inspiration from. Fix these there too. Signed-off-by: Heiko Stuebner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: rockchip: add support for phase invertersHeiko Stuebner4-0/+144
Most Rockchip socs have optional phase inverters connected to some clocks that move the clock-phase by 180 degrees. Signed-off-by: Heiko Stuebner <[email protected]> [[email protected]: Dropped lazy part of commit text] Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: rockchip: add COMPOSITE_NOGATE_DIVTBL variantHeiko Stuebner1-0/+20
A clock branch consisting of a mux and divider with non-standard divider values. Signed-off-by: Heiko Stuebner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: rockchip: protect register macros against multipart valuesHeiko Stuebner1-8/+8
The macros calculate the correct offset from the id in the parameter. If this parameter does not consist of a single number, the calculation will return wrong registers in the best case or create unaligned accesses in the worst case. So protect the calculations against such values. Signed-off-by: Heiko Stuebner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: rockchip: fix faulty vip parent name on rk3288Heiko Stuebner1-2/+2
The video input processor (vip) was called camera interface (cif) on older socs which seems to have resulted in a copy'n'paste error when creating the rk3288 camera clocks. Signed-off-by: Heiko Stuebner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: rockchip: rk3288: add CLK_SET_RATE_PARENT to sclk_macHeiko Stuebner1-1/+1
The dwmac ethernet controller on the rk3288 supports phys connected via rgmii and rmii. With rgmii phys it is expected that the mac clock is provided externally while with rmii phys the clock can be external but also generated from the plls. In the later case it of course needs be at 50MHz, which gets set from the dwmac_rk driver. As most devices use a rgmii phy it never surfaced so far that the mac clk mux, doesn't go up one lever to the pll clock in the rmii case with internal clock generation, as it is missing the CLK_SET_RATE_PARENT flag, and thus will not set the correct frequency in most cases. Fixes: b9e4ba541607 ("clk: rockchip: add clock controller for rk3288") Cc: [email protected] Signed-off-by: Heiko Stuebner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06drivers: clk: st: Fix mux bit-setting for Cortex A9 clocksGabriel Fernandez1-1/+1
This patch fixes the mux bit-setting for ClockgenA9. Signed-off-by: Gabriel Fernandez <[email protected]> Fixes: 13e6f2da1ddf ("clk: st: STiH407: Support for A9 MUX Clocks") Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocksPankaj Dev4-6/+8
Add the CLK_GET_RATE_NOCACHE flag to all the clocks with recalc ops, so that they reflect Hw rate after CPS wake-up when a clk_get_rate() is called Signed-off-by: Pankaj Dev <[email protected]> Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06drivers: clk: st: Fix flexgen lock initGiuseppe Cavallaro1-0/+2
While proving lock, the following warning happens and it is fixed after initializing lock in the setup function INFO: trying to register non-static key. the code is fine but needs lockdep annotation. turning off the locking correctness validator. CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.27-02861-g39df285-dirty #33 [<c00154ac>] (unwind_backtrace+0x0/0xf4) from [<c0011b50>] (show_stack+0x10/0x14) [<c0011b50>] (show_stack+0x10/0x14) from [<c00689ac>] (__lock_acquire+0x900/0xb14) [<c00689ac>] (__lock_acquire+0x900/0xb14) from [<c0069394>] (lock_acquire+0x68/0x7c) [<c0069394>] (lock_acquire+0x68/0x7c) from [<c04958f8>] (_raw_spin_lock_irqsave+0x48/0x5c) [<c04958f8>] (_raw_spin_lock_irqsave+0x48/0x5c) from [<c0381e6c>] (clk_gate_endisable+0x28/0x88) [<c0381e6c>] (clk_gate_endisable+0x28/0x88) from [<c0381ee0>] (clk_gate_enable+0xc/0x14) [<c0381ee0>] (clk_gate_enable+0xc/0x14) from [<c0386c68>] (flexgen_enable+0x28/0x40) [<c0386c68>] (flexgen_enable+0x28/0x40) from [<c037f260>] (__clk_enable+0x5c/0x9c) [<c037f260>] (__clk_enable+0x5c/0x9c) from [<c037f558>] (clk_enable+0x18/0x2c) [<c037f558>] (clk_enable+0x18/0x2c) from [<c064a1dc>] (st_lpc_of_register+0xc0/0x248) [<c064a1dc>] (st_lpc_of_register+0xc0/0x248) from [<c0649e44>] (clocksource_of_init+0x34/0x58) [<c0649e44>] (clocksource_of_init+0x34/0x58) from [<c0637ddc>] (sti_timer_init+0x10/0x18) [<c0637ddc>] (sti_timer_init+0x10/0x18) from [<c06343f8>] (time_init+0x20/0x30) [<c06343f8>] (time_init+0x20/0x30) from [<c0632984>] (start_kernel+0x20c/0x2e8) [<c0632984>] (start_kernel+0x20c/0x2e8) from [<40008074>] (0x40008074) Signed-off-by: Giuseppe Cavallaro <[email protected]> Signed-off-by: Gabriel Fernandez <[email protected]> Fixes: b116517055b7 ("clk: st: STiH407: Support for Flexgen Clocks") Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06drivers: clk: st: Fix FSYN channel valuesGabriel Fernandez1-2/+2
This patch fixes the value for disabling the FSYN channel clock. The 'is_enabled' returned value is also fixed. Signed-off-by: Pankaj Dev <[email protected]> Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06drivers: clk: st: Remove unused codeGabriel Fernandez1-4/+0
Remove this duplicated code due to a bad copy / paste. Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2015-07-06clk: qcom: Use parent rate when set rate to pixel RCG clockHai Li1-6/+3
Since the parent rate has been recalculated, pixel RCG clock should rely on it to find the correct M/N values during set_rate, instead of calling __clk_round_rate() to its parent again. Signed-off-by: Hai Li <[email protected]> Tested-by: Archit Taneja <[email protected]> Fixes: 99cbd064b059 ("clk: qcom: Support display RCG clocks") [[email protected]: Silenced unused parent variable warning] Signed-off-by: Stephen Boyd <[email protected]>
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