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2023-08-29Merge branch 'pci/controller/rockchip'Bjorn Helgaas1-3/+3
- Use 64-bit mask on MSI 64-bit PCI address to avoid zeroing out the upper 32 bits (Rick Wertenbroek) * pci/controller/rockchip: PCI: rockchip: Use 64-bit mask on MSI 64-bit PCI address
2023-08-29Merge branch 'pci/controller/qcom-ep'Bjorn Helgaas2-1/+88
- Log unknown Qcom Endpoint IRQ events at error level, not debug level (Manivannan Sadhasivam) - Add DT and driver support for qcom interconnect bandwidth voting for "pcie-mem" and "cpu-pcie" interconnects (Krishna chaitanya chundru) * pci/controller/qcom-ep: PCI: qcom-ep: Add ICC bandwidth voting support dt-bindings: PCI: qcom: ep: Add interconnects path PCI: qcom-ep: Treat unknown IRQ events as an error
2023-08-29Merge branch 'pci/controller/qcom-edma'Bjorn Helgaas3-17/+284
- Pass the Qcom Endpoint 4K alignment requirement for outbound windows to the EPF core so EPF drivers can use it (Manivannan Sadhasivam) - Use alignment restriction from EPF core in Qcom EPF MHI driver (Manivannan Sadhasivam) - Add Qcom Endpoint eDMA support by enabling the eDMA IRQ (Manivannan Sadhasivam) - Add Qcom MHI eDMA support (Manivannan Sadhasivam) - Add Qcom Snapdragon SM8450 support to the EPF MHI driver (Manivannan Sadhasivam) - Use iATU for EPF MHI transfers smaller than 4K to avoid eDMA setup latency (Manivannan Sadhasivam) - Add pci_epc_mem_init() kernel-doc (Manivannan Sadhasivam) * pci/controller/qcom-edma: PCI: endpoint: Add kernel-doc for pci_epc_mem_init() API PCI: epf-mhi: Use iATU for small transfers PCI: epf-mhi: Add support for SM8450 PCI: epf-mhi: Add eDMA support PCI: qcom-ep: Add eDMA support PCI: epf-mhi: Make use of the alignment restriction from EPF core PCI: qcom-ep: Pass alignment restriction to the EPF core
2023-08-29Merge branch 'pci/controller/qcom'Bjorn Helgaas4-6/+37
- Configure controller so MHI bus master clock will be switched off while in ASPM L1.x states (Manivannan Sadhasivam) - Add sa8775p DT binding and driver support (Mrinmay Sarkar) - Fix broken DT SDX65 "compatible" property (Krzysztof Kozlowski) * pci/controller/qcom: dt-bindings: PCI: qcom: Fix SDX65 compatible PCI: qcom: Add support for sa8775p SoC dt-bindings: PCI: qcom: Add sa8775p compatible PCI: qcom-ep: Switch MHI bus master clock off during L1SS
2023-08-29Merge branch 'pci/controller/microchip'Bjorn Helgaas2-162/+233
- Fix DED and SEC interrupt bit offsets so interrupt handlers work correctly (Daire McNamara) - Make driver buildable as a module (Daire McNamara) - Reorganize register #defines to align with hardware docs (Daire McNamara) - Tweak register accessors to simplify callers (Daire McNamara) - Refactor interrupt initialisation (Daire McNamara) - Read FPGA MSI configuration parameters from hardware instead of hard-coding them (Daire McNamara) - Re-partition code between probe() and init() (Daire McNamara) * pci/controller/microchip: PCI: microchip: Re-partition code between probe() and init() PCI: microchip: Gather MSI information from hardware config registers PCI: microchip: Clean up initialisation of interrupts PCI: microchip: Enable event handlers to access bridge and control pointers PCI: microchip: Align register, offset, and mask names with HW docs PCI: microchip: Enable building driver as a module PCI: microchip: Correct the DED and SEC interrupt bit offsets
2023-08-29Merge branch 'pci/controller/layerscape'Bjorn Helgaas1-0/+20
- Add support for link-down notification so the endpoint driver can process LINK_DOWN events (Frank Li) - Save Link Capabilities during probe so they can be restored when handling a link-up event, since the controller loses the Link Width and Link Speed values during reset (Xiaowei Bao) * pci/controller/layerscape: PCI: layerscape: Add workaround for lost link capabilities during reset PCI: layerscape: Add support for link-down notification
2023-08-29Merge branch 'pci/controller/iproc'Bjorn Helgaas1-3/+2
- Use of_property_read_bool() instead of low-level accessors for boolean properties (Rob Herring) * pci/controller/iproc: PCI: iproc: Use of_property_read_bool() for boolean properties
2023-08-29Merge branch 'pci/controller/hv'Bjorn Helgaas1-0/+3
- To avoid a NULL pointer dereference, skip MSI restore after hibernate if MSI/MSI-X hasn't been enabled (Dexuan Cui) * pci/controller/hv: PCI: hv: Fix a crash in hv_pci_restore_msi_msg() during hibernation
2023-08-29Merge branch 'pci/controller/fu740'Bjorn Helgaas1-0/+1
- Set the supported number of MSI vectors so we can use all available MSI interrupts (Yong-Xuan Wang) * pci/controller/fu740: PCI: fu740: Set the number of MSI vectors
2023-08-29Merge branch 'pci/controller/dwc'Bjorn Helgaas5-9/+237
- Add an imx6 .host_deinit() callback so we can clean up things like regulators on probe failure or driver unload (Mark Brown) - Add PCIE_PME_TO_L2_TIMEOUT_US value for controller drivers that need to manually synchronize power removal (Frank Li) - Add generic dwc suspend/resume APIs (dw_pcie_suspend_noirq() and dw_pcie_resume_noirq()) to be called by controller driver suspend/resume ops, and a controller callback to send PME_Turn_Off (Frank Li) - Add layerscape suspend/resume support, including manual PME_Turn_off/PME_TO_Ack handshake (Hou Zhiqiang, Frank Li) * pci/controller/dwc: PCI: layerscape: Add power management support for ls1028a PCI: dwc: Implement generic suspend/resume functionality PCI: Add PCIE_PME_TO_L2_TIMEOUT_US L2 ready timeout value PCI: dwc: Provide deinit callback for i.MX
2023-08-29Merge branch 'pci/controller/brcmstb'Bjorn Helgaas1-1/+5
- Assert PERST# when probing BCM2711 because some bootloaders don't do it (Jim Quinlan) * pci/controller/brcmstb: PCI: brcmstb: Remove stale comment PCI: brcmstb: Assert PERST# on BCM2711
2023-08-29Merge branch 'pci/controller/apple'Bjorn Helgaas1-1/+5
- Initialize pcie->nvecs (number of available MSIs) before use (Sven Peter) * pci/controller/apple: PCI: apple: Initialize pcie->nvecs before use
2023-08-29Merge branch 'pci/vpd'Bjorn Helgaas2-9/+48
- Ensure device is accessible before VPD access via sysfs (Alex Williamson) - Ensure device doesn't go to a low-power state while we're polling for PME (Alex Williamson) * pci/vpd: PCI: Fix runtime PM race with PME polling PCI/VPD: Add runtime power management to sysfs interface
2023-08-29Merge branch 'pci/vga'Bjorn Helgaas2-201/+184
- Correct parameter types for vga_str_to_iostate() and vga_update_device_decodes() (Sui Jingfeng) - Simplify vga_arbiter_notify_clients() (Sui Jingfeng) - Simplify vga_client_register() (Sui Jingfeng) - Replace MIT license text with SPDX identifier (Sui Jingfeng) - Fix lots of comment typos (Sui Jingfeng) * pci/vga: PCI/VGA: Fix typos PCI/VGA: Replace full MIT license text with SPDX identifier PCI/VGA: Simplify vga_client_register() PCI/VGA: Simplify vga_arbiter_notify_clients() PCI/VGA: Correct vga_update_device_decodes() parameter type PCI/VGA: Correct vga_str_to_iostate() io_state parameter type
2023-08-29Merge branch 'pci/virtualization'Bjorn Helgaas1-1/+1
- Avoid bus resets on NVIDIA T4 GPUs because they don't seem to recover (Wu Zongyong) * pci/virtualization: PCI: Mark NVIDIA T4 GPUs to avoid bus reset
2023-08-29Merge branch 'pci/pm'Bjorn Helgaas1-4/+9
- Only read PCI_PM_CTRL register when available, to avoid reading the wrong register and corrupting dev->current_state (Feiyang Chen) * pci/pm: PCI/PM: Only read PCI_PM_CTRL register when available
2023-08-29Merge branch 'pci/pcie-rmw'Bjorn Helgaas15-183/+151
- Add locking for read/modify/write PCIe Capability Register accessors for Link Control and Root Control (Ilpo Järvinen) - Use PCIe RMW accessors for Link Control updates in PCI core, pciehp, amdgpu, radeon, mlx5, ath10k, ath11k, ath12k (Ilpo Järvinen) - Convert PCIBIOS error values in mlx5 to generic errnos (Ilpo Järvinen) - Simplify pcie_capability_clear_and_set_word() control flow (Bjorn Helgaas) * pci/pcie-rmw: PCI: Simplify pcie_capability_clear_and_set_word() control flow net/mlx5: Convert PCI error values to generic errnos PCI: Document the Capability accessor RMW improvements wifi: ath10k: Use RMW accessors for changing LNKCTL wifi: ath12k: Use RMW accessors for changing LNKCTL wifi: ath11k: Use RMW accessors for changing LNKCTL net/mlx5: Use RMW accessors for changing LNKCTL drm/radeon: Use RMW accessors for changing LNKCTL drm/amdgpu: Use RMW accessors for changing LNKCTL PCI/ASPM: Use RMW accessors for changing LNKCTL PCI: pciehp: Use RMW accessors for changing LNKCTL PCI: Make link retraining use RMW accessors for changing LNKCTL PCI: Add locking to RMW PCI Express Capability Register accessors
2023-08-29Merge branch 'pci/ioport'Bjorn Helgaas2-0/+6
- Make I/O resources depend on CONFIG_HAS_IOPORT so inw() and friends can be completely omitted on architectures without I/O port support (Niklas Schnelle) * pci/ioport: PCI/sysfs: Make I/O resource depend on HAS_IOPORT PCI: Make quirk using inw() depend on HAS_IOPORT
2023-08-29Merge branch 'pci/hotplug'Bjorn Helgaas1-5/+5
- Make ibmphp read-only arrays static instead of putting them on the stack (Colin Ian King) * pci/hotplug: PCI: ibmphp: Make read-only arrays static
2023-08-29Merge branch 'pci/aer'Bjorn Helgaas2-25/+1
- Remove pci_disable_pcie_error_reporting() (unused) and unexport pci_enable_pcie_error_reporting(). This all done by the PCI core now (Bjorn Helgaas) * pci/aer: PCI/AER: Unexport pci_enable_pcie_error_reporting() PCI/AER: Drop unused pci_disable_pcie_error_reporting()
2023-08-29PCI: qcom-ep: Add ICC bandwidth voting supportKrishna chaitanya chundru1-0/+72
Add support for voting interconnect (ICC) bandwidth based on the link speed and width. This commit is inspired from the basic interconnect support added to pcie-qcom driver in commit c4860af88d0c ("PCI: qcom: Add basic interconnect support"). The interconnect support is kept optional to be backward compatible with legacy device trees. [kwilczynski: add missing kernel-doc for the icc_mem variable] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Krishna chaitanya chundru <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2023-08-29dt-bindings: PCI: qcom: ep: Add interconnects pathKrishna chaitanya chundru1-0/+15
Some platforms may not boot if a device driver doesn't initialize the interconnect path. Mostly it is handled by the bootloader but we have starting to see cases where bootloader simply ignores them. Add the "pcie-mem" & "cpu-pcie" interconnect path as a required property to the bindings. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Krishna chaitanya chundru <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
2023-08-29PCI: qcom-ep: Treat unknown IRQ events as an errorManivannan Sadhasivam1-1/+1
Sometimes, the Qcom PCIe EP controller can receive some interrupts unknown to the driver, like safety interrupts in newer SoCs. In those cases, if the driver doesn't clear the interrupts, it will end up in an interrupt storm. However, the users will not know about it because the log is treated as a debug message. So let's treat the unknown event log as an error so that it at least makes the user aware, thereby getting fixed eventually. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]>
2023-08-27dt-bindings: PCI: qcom: Fix SDX65 compatibleKrzysztof Kozlowski1-5/+7
Commit c0aba9f32801 ("dt-bindings: PCI: qcom: Add SDX65 SoC") adding SDX65 was never tested and is clearly bogus. The qcom,sdx65-pcie-ep compatible is followed by a fallback in DTS, and there is no driver matched by this compatible. Driver matches by its fallback qcom,sdx55-pcie-ep. This also fixes dtbs_check warnings like: qcom-sdx65-mtp.dtb: pcie-ep@1c00000: compatible: ['qcom,sdx65-pcie-ep', 'qcom,sdx55-pcie-ep'] is too long [kwilczynski: commit log] Fixes: c0aba9f32801 ("dt-bindings: PCI: qcom: Add SDX65 SoC") Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Acked-by: Conor Dooley <[email protected]> Cc: [email protected]
2023-08-26PCI: endpoint: Add kernel-doc for pci_epc_mem_init() APIManivannan Sadhasivam1-0/+10
Add missing kernel-doc for pci_epc_mem_init() API. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Randy Dunlap <[email protected]>
2023-08-26PCI: epf-mhi: Use iATU for small transfersManivannan Sadhasivam1-0/+6
For transfers below 4K, let's use iATU since using eDMA for such small transfers is inefficient. This is mainly because setting up an eDMA transfer and waiting for completion adds some latency. This latency is negligible for large transfers but not for the smaller ones. With using iATU, there is an increase in ~50Mbps throughput on both MHI UL (Uplink) and DL (Downlink) channels. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]>
2023-08-26PCI: epf-mhi: Add support for SM8450Manivannan Sadhasivam1-3/+19
Add support for Qualcomm Snapdragon SM8450 SoC to the EPF driver. SM8450 has the dedicated PID (0x0306) and supports eDMA. Currently, it has no fixed PCI class, so it is being advertised as "PCI_CLASS_OTHERS". Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]>
2023-08-26PCI: epf-mhi: Add eDMA supportManivannan Sadhasivam1-6/+231
Add support for Embedded DMA (eDMA) available in the DesignWare PCIe IP to transfer the MHI buffers between the host and the endpoint. The eDMA use helps achieve greater throughput as the transfers are offloaded from CPUs. For differentiating the iATU and eDMA APIs, the pci_epf_mhi_{read/write} APIs are renamed to pci_epf_mhi_iatu_{read/write} and separate eDMA specific APIs pci_epf_mhi_edma_{read/write} are introduced. Platforms that require eDMA support can pass the MHI_EPF_USE_DMA flag through pci_epf_mhi_ep_info. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]>
2023-08-26PCI: qcom-ep: Add eDMA supportManivannan Sadhasivam1-1/+3
Qualcomm PCIe Endpoint controllers have the in-built Embedded DMA (eDMA) peripheral for offloading the data transfer between the PCIe bus and memory. Let's add support for it by enabling the eDMA IRQ in the driver. The eDMA DMA Engine driver will handle the rest of the functionality. Since the eDMA on Qualcomm platforms only uses a single IRQ for all channels, use 1 for edma.nr_irqs. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]>
2023-08-26PCI: epf-mhi: Make use of the alignment restriction from EPF coreManivannan Sadhasivam1-7/+14
Instead of hardcoding the alignment restriction in the EPF_MHI driver, make use of the info available from the EPF core that reflects the alignment restriction of the endpoint controller. For this purpose, let's introduce the get_align_offset() static function. [kwilczynski: update get_align_offset() to avoid issues on 32-bit architectures] Link: https://lore.kernel.org/linux-pci/[email protected] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]>
2023-08-25PCI/PM: Only read PCI_PM_CTRL register when availableFeiyang Chen1-4/+9
For a device with no Power Management Capability, pci_power_up() previously returned 0 (success) if the platform was able to put the device in D0, which led to pci_set_full_power_state() trying to read PCI_PM_CTRL, even though it doesn't exist. Since dev->pm_cap == 0 in this case, pci_set_full_power_state() actually read the wrong register, interpreted it as PCI_PM_CTRL, and corrupted dev->current_state. This led to messages like this in some cases: pci 0000:01:00.0: Refused to change power state from D3hot to D0 To prevent this, make pci_power_up() always return a negative failure code if the device lacks a Power Management Capability, even if non-PCI platform power management has been able to put the device in D0. The failure will prevent pci_set_full_power_state() from trying to access PCI_PM_CTRL. Fixes: e200904b275c ("PCI/PM: Split pci_power_up()") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Feiyang Chen <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: "Rafael J. Wysocki" <[email protected]> Cc: [email protected] # v5.19+
2023-08-25PCI: qcom: Add support for sa8775p SoCMrinmay Sarkar1-0/+1
Add support for sa8775p SoC that uses controller version 5.90 reusing the 1.9.0 config. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Mrinmay Sarkar <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2023-08-25dt-bindings: PCI: qcom: Add sa8775p compatibleMrinmay Sarkar1-0/+28
Add sa8775p platform to the binding. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Mrinmay Sarkar <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
2023-08-25PCI: qcom-ep: Pass alignment restriction to the EPF coreManivannan Sadhasivam1-0/+1
Qcom PCIe EP controllers have 4K alignment restriction for the outbound window address. Hence, pass this info to the EPF core so that the EPF drivers can make use of this info. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]>
2023-08-25PCI: Simplify pcie_capability_clear_and_set_word() control flowBjorn Helgaas1-12/+10
Return early for errors in pcie_capability_clear_and_set_word_unlocked() and pcie_capability_clear_and_set_dword() to simplify the control flow. No functional change intended. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]>
2023-08-24PCI/VGA: Fix typosSui Jingfeng2-151/+161
Fix typos, rewrap to fill 78 columns, convert to conventional multi-line style. [bhelgaas: squash and add more fixes] Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sui Jingfeng <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2023-08-24PCI: brcmstb: Remove stale commentJim Quinlan1-1/+0
A comment says that Multi-MSI is not supported by the driver. A past commit [1] added this feature, so the comment is incorrect and is removed. [1] commit 198acab1772f22f2 ("PCI: brcmstb: Enable Multi-MSI") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Florian Fainelli <[email protected]>
2023-08-24PCI: brcmstb: Assert PERST# on BCM2711Jim Quinlan1-0/+5
The current PCIe driver assumes PERST# is asserted when probe() is invoked. Some older versions of the 2711/RPi bootloader left PERST# unasserted, as the Raspian OS does assert PERST# on probe(). For this reason, we assert PERST# for BCM2711 SOCs (i.e. RPi). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2023-08-24PCI: layerscape: Add power management support for ls1028aHou Zhiqiang1-9/+131
Add PME_Turn_off/PME_TO_Ack handshake sequence for ls1028a platform. Implemented on top of common dwc dw_pcie_suspend(resume)_noirq() functions to handle system enter/exit suspend states. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Frank Li <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
2023-08-24PCI: dwc: Implement generic suspend/resume functionalityFrank Li2-0/+99
Introduce an helper function (dw_pcie_get_ltssm()) to retrieve SMLH_LTSS_STATE. Add common dw_pcie_suspend(resume)_noirq() API to implement the DWC controller generic suspend/resume functionality. Add a controller specific callback to send the PME_Turn_Off message (ie .pme_turn_off) for controller platform specific PME handling. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Frank Li <[email protected]> [[email protected]: commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
2023-08-24PCI: Add PCIE_PME_TO_L2_TIMEOUT_US L2 ready timeout valueFrank Li1-0/+6
Add the PCIE_PME_TO_L2_TIMEOUT_US macro to define the L2 ready timeout as described in the PCI specifications. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Frank Li <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
2023-08-24PCI: layerscape: Add workaround for lost link capabilities during resetXiaowei Bao1-0/+19
The endpoint controller loses the Maximum Link Width and Supported Link Speed value from the Link Capabilities Register - initially configured by the Reset Configuration Word (RCW) - during a link-down or hot reset event. Address this issue in the endpoint event handler. Link: https://lore.kernel.org/r/[email protected] Fixes: a805770d8a22 ("PCI: layerscape: Add EP mode support") Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Frank Li <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
2023-08-24PCI: layerscape: Add support for link-down notificationFrank Li1-0/+1
Add support to pass link-down notification to the endpoint function driver so that it can process the LINK_DOWN event. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Frank Li <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
2023-08-23PCI/VGA: Replace full MIT license text with SPDX identifierSui Jingfeng1-21/+2
Per Documentation/process/license-rules.rst, the SPDX MIT identifier is equivalent to including the entire MIT license text from LICENSES/preferred/MIT. Replace the MIT license text with the equivalent SPDX identifier. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sui Jingfeng <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Andi Shyti <[email protected]>
2023-08-23PCI/VGA: Simplify vga_client_register()Sui Jingfeng1-12/+7
Reorganize vga_client_register() to avoid the goto and the need to save the return value. Update the kernel-doc to reflect -ENODEV on failure. No functional change intended. [bhelgaas: drop "ret" variable, commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sui Jingfeng <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2023-08-23PCI/VGA: Simplify vga_arbiter_notify_clients()Sui Jingfeng1-4/+2
In vga_arbiter_notify_clients(), "new_state" was computed during every loop iteration even though it doesn't depend on anything that changes during the loop. Move the computation outside the loop. [bhelgaas: drop renames that obscure the purpose, commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sui Jingfeng <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2023-08-23PCI/VGA: Correct vga_update_device_decodes() parameter typeSui Jingfeng1-13/+12
Previously vga_update_device_decodes() took "int new_decodes", but the callers pass "unsigned int new_decodes". Correct the vga_update_device_decodes() parameter type to "unsigned int" to match. In vga_arbiter_notify_clients(), the return from vgadev->set_decode() is "unsigned int" but was stored as "uint32_t new_decodes". Correct the new_decodes type to "unsigned int". [bhelgaas: use correct type for ->set_decode() return, commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sui Jingfeng <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2023-08-23PCI/VGA: Correct vga_str_to_iostate() io_state parameter typeSui Jingfeng1-1/+1
Previously vga_str_to_iostate() took "int *io_state", but vga_arb_write() is the only caller and it passes "unsigned int *". Make the vga_str_to_iostate() parameter type "unsigned int *" to match. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sui Jingfeng <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]>
2023-08-23PCI: fu740: Set the number of MSI vectorsYong-Xuan Wang1-0/+1
The iMSI-RX module of the DW PCIe controller provides multiple sets of MSI_CTRL_INT_i_* registers, and each set is capable of handling 32 MSI interrupts. However, the fu740 PCIe controller driver only enabled one set of MSI_CTRL_INT_i_* registers, as the total number of supported interrupts was not specified. Set the supported number of MSI vectors to enable all the MSI_CTRL_INT_i_* registers on the fu740 PCIe core, allowing the system to fully utilize the available MSI interrupts. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Yong-Xuan Wang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Serge Semin <[email protected]>
2023-08-22PCI: hv: Fix a crash in hv_pci_restore_msi_msg() during hibernationDexuan Cui1-0/+3
When a Linux VM with an assigned PCI device runs on Hyper-V, if the PCI device driver is not loaded yet (i.e. MSI-X/MSI is not enabled on the device yet), doing a VM hibernation triggers a panic in hv_pci_restore_msi_msg() -> msi_lock_descs(&pdev->dev), because pdev->dev.msi.data is still NULL. Avoid the panic by checking if MSI-X/MSI is enabled. Link: https://lore.kernel.org/r/[email protected] Fixes: dc2b453290c4 ("PCI: hv: Rework MSI handling") Signed-off-by: Dexuan Cui <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: [email protected] Reviewed-by: Michael Kelley <[email protected]> Cc: [email protected]
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