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Avoids possibility that info may leak via the uninitialized
_pad element.
Noticed-by: Dan Carpenter <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Need to unlock the mutex on error.
Noticed-by: Dan Carpenter <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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this could prevent mis-understanding, because libdrm side will consider
no bo_list created if handleis zero
Signed-off-by: monk.liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Still need to handle ibs BO and validate them even bo_list is NULL
Signed-off-by: Monk.Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Jack Xiao <[email protected]>
Reviewed-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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amdgpu_bo_create() calls amdgpu_ttm_placement_from_domain()
before ttm_bo_init() is called. amdgpu_ttm_placement_from_domain()
uses the ttm bo size to determine when to select top down
allocation but since the ttm bo is not initialized yet the
check is always false. It only took affect when buffers
were validated later. It also seemed to regress suspend
and resume on some systems possibly due to it not
taking affect in amdgpu_bo_create().
amdgpu_bo_create() and amdgpu_ttm_placement_from_domain()
need to be reworked substantially for this to be optimally
effective. Re-enable it at that point.
Ported from radeon commit:
a239118a24b3bf9089751068e431dfb63dc4168b
Signed-off-by: Alex Deucher <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>
Reviewed-by: Christian König <[email protected]>
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Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This adds initial support for VI asics. This
includes Iceland, Tonga, and Carrizo. Our inital
focus as been Carrizo, so there are still gaps in
support for Tonga and Iceland, notably power
management.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This patch adds support for CIK parts. These parts
are also supported by radeon which is the preferred
option, so there is a config option to enable support
for CIK parts in amdgpu for testing.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Use readb() and memcpy_fromio() accessors instead.
Ported from radeon commit:
f2c9e560b406f2f6b14b345c7da33467dee9cdf2
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This adds the non-asic specific core driver code.
v2: remove extra kconfig option
v3: implement minor fixes from Fengguang Wu
v4: fix cast in amdgpu_ucode.c
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This is the main header file for amdgpu.
v2: remove stable comments
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This header defines asic families and attributes.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This header provides the smc message interface for the driver.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This header provides for format for the GCA blocks
clear state (i.e., default state). Each GCA version
has a specific clear state.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These headers define the atombios table structure and
driver interface.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This header defines the ioctl interface to the driver.
v2: remove stale tiling defines
v3: add appropriate padding
v4: remove executable bits on header
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the VCE (Video Codec Engine)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the VCE (Video Codec Engine)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the UVD (Universal Video Decoder)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the UVD (Universal Video Decoder)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the UVD (Universal Video Decoder)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the SMU (System Management Unit)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the SMU (System Management Unit)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the SMU (System Management Unit)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the SMU (System Management Unit)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the SMU (System Management Unit)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the SMU (System Management Unit)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the OSS (OS Services)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the OSS (OS Services)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the OSS (OS Services)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the OSS (OS Services)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the GMC (Graphics Memory Controller)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the GMC (Graphics Memory Controller)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the GMC (Graphics Memory Controller)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the GMC (Graphics Memory Controller)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the GCA (Graphics and Compute Array)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the GCA (Graphics and Compute Array)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the GCA (Graphics and Compute Array)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the DCE (Display and Composition Engine)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the DCE (Display and Composition Engine)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the DCE (Display and Composition Engine)
block on the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the BIF (Bus InterFace) block on
the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the BIF (Bus InterFace) block on
the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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These are register headers for the BIF (Bus InterFace) block on
the GPU.
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Yay, thanks to Gerd for pull this together.
* 'virtio-gpu-drm-next' of git://git.kraxel.org/linux:
Add MAINTAINERS entry for virtio-gpu.
Add virtio gpu driver.
drm_vblank_get: don't WARN_ON in case vblanks are not initialized
break kconfig dependency loop
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https://github.com/jsarha/linux into drm-next
Please pull the contents of "Use DRM component API in tilcdc to
connect to tda998x" patch series.
* 'linux-4.1.0-rc5-tilcdc-refactor' of https://github.com/jsarha/linux:
drm/tilcdc: Force building of DRM_TILCDC_SLAVE_COMPAT
drm/tilcdc: Add DRM_TILCDC_SLAVE_COMPAT for ti,tilcdc,slave binding support
drm/tilcdc: use pm_runtime_irq_safe()
drm/tilcdc: Add support for external tda998x encoder
drm/tilcdc: Remove tilcdc slave support for tda998x driver
drm/tilcdc: Fix module unloading
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Linux 4.1-rc6
backmerge 4.1-rc6 as some of the later pull reqs are based on newer bases
and I'd prefer to do the fixup myself.
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