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2019-10-17drm/amd/display: handle "18" case in TruncToValidBPPBhawanpreet Lakha1-0/+2
Handle 18 DecimalBPP like other cases Signed-off-by: Bhawanpreet Lakha <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: update odm mode validation to be in line with policyDmytro Laktyushkin1-1/+8
Previously 8k30 worked with dsc and odm combine due to a workaround that ran the formula a second time with dsc support enable should dsc validation fail. This worked when clocks were low enough for formula to enable odm to lower voltage, however now broke due to increased clocks. This change updates the ODM combine policy within the formula to properly reflect our current policy within DC, only enabling ODM when we have to, as well as adding a check for viewport width when dsc is enabled. As a side effect the redundant call to dml when odm is required is now unnecessary. Signed-off-by: Dmytro Laktyushkin <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: add dummy functions to smu for Renoir Silicon DiagsSung Lee1-1/+1
[Why] Previously only dummy functions were added in Diags for FPGA. On silicon, this would lead to a segmentation fault on silicon diags. [How] Check if diags silicon and if so, add dummy functions. Signed-off-by: Sung Lee <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: change PP_SM defs to 8Bhawanpreet Lakha1-2/+2
DPM level is 8 these were incorrect before. Fix them Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: update renoir bounding box and res_capsBhawanpreet Lakha1-11/+13
The values for bounding box and res_caps were incorrect. So Fix them Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: update dcn21 hubbub registersBhawanpreet Lakha1-10/+7
use dcn20 common regs define to share some regs with dcn20 Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: add detile buffer size for renoirBhawanpreet Lakha1-0/+1
Detile buffer size affects dcc caps, it was already added for dcn2. Now add it for dcn21 Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: correct dcn21 NUM_VMID to 16Dmytro Laktyushkin1-1/+1
1 vmid limitation only exists for HOSTVM which is a custom use case anyway. Signed-off-by: Dmytro Laktyushkin <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: use dcn10 version of program tiling on RenoirEric Yang1-1/+3
[Why] Renoir is gfx9, same as dcn10, not dcn20. Signed-off-by: Eric Yang <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: initialize RN gpuvm context programming functionDmytro Laktyushkin1-1/+1
Renoir can use vm contexes as long as HOSTVM is off so this should be initialized. Signed-off-by: Dmytro Laktyushkin <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: Temporary workaround to toggle watermark settingLewis Huang4-0/+15
[Why] Watermarks not propagated to DCHUBP after it is powered on [How] Add temoprary function apply_DEDCN21_147_wa to apply wm settings for Renoir Signed-off-by: Lewis Huang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: fix incorrect page table address for renoirBhawanpreet Lakha1-6/+17
Incorrect page table address and programming sys aperture for stutter gather, so fix it. Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: enable hostvm based on roimmu active for dcn2.1Dmytro Laktyushkin1-15/+25
Enabling hostvm when ROIMMU is not active seems to break GPUVM. This fixes the issue by not enabling hostvm if ROIMMU is not activated. Signed-off-by: Dmytro Laktyushkin <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: move the bounding box patch before calculate wmLewis Huang1-0/+25
[why] driver updateis the dcn2_1_soc into dml before call update_bw_bounding_box [How] Move the patch function before calculate wm. Signed-off-by: Lewis Huang <[email protected]> Signed-off-by: joseph graveno <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: add REFCYC_PER_TRIP_TO_MEMORY programmingBhawanpreet Lakha4-4/+69
it allows us to do urgent latency programming Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: create dcn21_link_encoder filesBhawanpreet Lakha6-4/+555
[Why] DCN20 and DCN21 have different phy programming sequences. [How] Create a separate dcn21_link_encoder for Renoir Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: Add renoir hw_seqBhawanpreet Lakha7-28/+255
This change adds renoir hw_seq, needed to do renoir specific hw programing Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: Add DCN_BASE regsBhawanpreet Lakha1-0/+34
Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: Add DP_DPHY_INTERNAL_CTR regsBhawanpreet Lakha1-0/+10
Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: disable ext aux support for vegaRoman Li1-1/+1
[Why] Earlier changes to support configurable aux timeout caused dc init failure on vega due to missing reg defs. Needs to be disabled until implemented for vega. [How] Set extended aux timeout cap for vega to false. Signed-off-by: Roman Li <[email protected]> Reviewed-By: abdoulaye berthe <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: configurable aux timeout supportabdoulaye berthe15-17/+132
[Description] 1-add configurable timeout support to aux engine. 2-add timeout support field to dc_caps 3-add reg_key to override extended timeout support Signed-off-by: abdoulaye berthe <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: update register field access mechanismabdoulaye berthe10-12/+271
1-add timeout length and multiplier fields to aux_control1 register 2-update access mechanism from macro constructed name to uint32_t defined addresses. 3-define registers and field per asic family Signed-off-by: abdoulaye berthe <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu: No need to check gfxoff status after enable gfxoff featurechen gong1-9/+0
smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff) Just turn on a switch. As to when GPU get into "GFXoff" will be up to drawing load. So we can not sure which state GPU should be in after enable gfxoff feature. Signed-off-by: chen gong <[email protected]> Acked-by: Evan Quan <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/powerplay: bug fix for memory clock request from displayKenneth Feng1-0/+2
In some cases, display fixes memory clock frequency to a high value rather than the natural memory clock switching. When we comes back from s3 resume, the request from display is not reset, this causes the bug which makes the memory clock goes into a low value. Then due to the insuffcient memory clock, the screen flicks. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu: fix S3 failed as RLC safe mode entry stucked in polloing gfx acqPrike Liang2-5/+4
Fix gfx cgpg setting sequence for RLC deadlock at safe mode entry in polling gfx response. The patch can fix VCN IB test failed and DAL get dispaly count failed issue. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu: add GFX_PIPELINE capacity check for updating gfx cgpgPrike Liang1-1/+2
Before disable gfx pipeline power gating need check the flag AMD_PG_SUPPORT_GFX_PIPELINE. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/i915/selftests: Teach requests to use all available enginesChris Wilson1-112/+175
The request selftests straddle the boundary between checking the driver and the hardware. They are subject to the quirks of the underlying HW, but operate on top of the backend abstractions. The tests focus on the scheduler elements and so should check for interactions of the scheduler across all exposed engines. Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-18Merge tag 'drm-fixes-5.4-2019-10-16' of ↵Dave Airlie6-46/+38
git://people.freedesktop.org/~agd5f/linux into drm-fixes drm-fixes-5.4-2019-10-16: amdgpu: - Powerplay fix for SMU7 parts - Bail earlier when cik/si support is not set to 1 - Fix an SDMA issue on navi radeon: - revert a PPC fix which broken x86 Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-18Merge tag 'drm-intel-fixes-2019-10-17' of ↵Dave Airlie7-27/+78
git://anongit.freedesktop.org/drm/drm-intel into drm-fixes - Display fix on handling VBT information. - Important circular locking fix - Fix for preemption vs resubmission on virtual requests - and a prep patch to make this last one to apply cleanly Signed-off-by: Dave Airlie <[email protected]> From: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-17net: dsa: microchip: Add shared regmap mutexMarek Vasut5-9/+28
The KSZ driver uses one regmap per register width (8/16/32), each with it's own lock, but accessing the same set of registers. In theory, it is possible to create a race condition between these regmaps, although the underlying bus (SPI or I2C) locking should assure nothing bad will really happen and the accesses would be correct. To make the driver do the right thing, add one single shared mutex for all the regmaps used by the driver instead. This assures that even if some future hardware is on a bus which does not serialize the accesses the same way SPI or I2C does, nothing bad will happen. Note that the status_mutex was unused and only initied, hence it was renamed and repurposed as the regmap mutex. Signed-off-by: Marek Vasut <[email protected]> Cc: Andrew Lunn <[email protected]> Cc: David S. Miller <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: George McCollister <[email protected]> Cc: Tristram Ha <[email protected]> Cc: Woojung Huh <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-10-17net: dsa: microchip: Do not reinit mutexes on KSZ87xxMarek Vasut1-4/+0
The KSZ87xx driver calls mutex_init() on mutexes already inited in ksz_common.c ksz_switch_register(). Do not do it twice, drop the reinitialization. Signed-off-by: Marek Vasut <[email protected]> Cc: Andrew Lunn <[email protected]> Cc: David S. Miller <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: George McCollister <[email protected]> Cc: Tristram Ha <[email protected]> Cc: Woojung Huh <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-10-17net: stmmac: fix argument to stmmac_pcs_ctrl_ane()Ben Dooks (Codethink)1-1/+1
The stmmac_pcs_ctrl_ane() expects a register address as argument 1, but for some reason the mac_device_info is being passed. Fix the warning (and possible bug) from sparse: drivers/net/ethernet/stmicro/stmmac/stmmac_main.c:2613:17: warning: incorrect type in argument 1 (different address spaces) drivers/net/ethernet/stmicro/stmmac/stmmac_main.c:2613:17: expected void [noderef] <asn:2> *ioaddr drivers/net/ethernet/stmicro/stmmac/stmmac_main.c:2613:17: got struct mac_device_info *hw Signed-off-by: Ben Dooks <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-10-17Merge branch 'dpaa2-eth-misc-fixes'David S. Miller2-2/+53
Ioana Ciornei says: ==================== dpaa2-eth: misc fixes This patch set adds a couple of fixes around updating configuration on MAC change. Depending on when MC connects the DPNI to a MAC, both the MAC address and TX FQIDs should be updated everytime there is a change in configuration. Changes in v2: - used reverse christmas tree ordering in patch 2/2 Changes in v3: - add a missing new line - go back to FQ based enqueueing after a transient error ==================== Signed-off-by: David S. Miller <[email protected]>
2019-10-17dpaa2-eth: Fix TX FQID valuesIoana Radulescu1-0/+44
Depending on when MC connects the DPNI to a MAC, Tx FQIDs may not be available during probe time. Read the FQIDs each time the link goes up to avoid using invalid values. In case an error occurs or an invalid value is retrieved, fall back to QDID-based enqueueing. Fixes: 1fa0f68c9255 ("dpaa2-eth: Use FQ-based DPIO enqueue API") Signed-off-by: Ioana Radulescu <[email protected]> Signed-off-by: Ioana Ciornei <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-10-17dpaa2-eth: add irq for the dpmac connect/disconnect eventFlorin Chiculita2-2/+9
Add IRQ for the DPNI endpoint change event, resolving the issue when a dynamically created DPNI gets a randomly generated hw address when the endpoint is a DPMAC object. Signed-off-by: Florin Chiculita <[email protected]> Signed-off-by: Ioana Ciornei <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-10-17usb: hso: obey DMA rules in tiocmgetOliver Neukum1-4/+9
The serial state information must not be embedded into another data structure, as this interferes with cache handling for DMA on architectures without cache coherence.. That would result in data corruption on some architectures Allocating it separately. v2: fix syntax error Signed-off-by: Oliver Neukum <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-10-17Merge branch 'for-linus' of ↵Linus Torvalds5-44/+97
git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input Pull input fixes from Dmitry Torokhov: "The main change is that we are reverting blanket enablement of SMBus mode for devices with Elan touchpads that report BIOS release date as 2018+ because there are older boxes with updated BIOSes that still do not work well in SMbus mode. We will have to establish whitelist for SMBus mode it looks like" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input: Revert "Input: elantech - enable SMBus on new (2018+) systems" Input: synaptics-rmi4 - avoid processing unknown IRQs Input: soc_button_array - partial revert of support for newer surface devices Input: goodix - add support for 9-bytes reports Input: da9063 - fix capability and drop KEY_SLEEP
2019-10-17drm/i915/huc: improve documentationDaniele Ceraolo Spurio3-21/+45
Better explain the usage of the microcontroller and what i915 is responsible of. While at it, fix the documentation for the auth function, which doesn't do any pinning anymore. v2: add a comment on HuC being optional and descrive how HuC accesses memory (Martin) v3: add extra newline for better text organization (Martin) Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Michal Wajdeczko <[email protected]> Cc: Martin Peres <[email protected]> Acked-by: Anna Karas <[email protected]> Reviewed-by: Martin Peres <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-17drm/i915/guc: improve documentationDaniele Ceraolo Spurio4-13/+49
Add a short description of what we expect from GuC and some minor improvements to existing documentation. Also remove a comment about a difference between GuC and HuC that is not true anymore. v2: add that the GuC is not mandatory (Martin) v3: add extra newline for better text organization (Martin) Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Michal Wajdeczko <[email protected]> Cc: Matthew Brost <[email protected]> Cc: Martin Peres <[email protected]> Acked-by: Anna Karas <[email protected]> Reviewed-by: Martin Peres <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-17drm/i915: Add microcontrollers documentation sectionDaniele Ceraolo Spurio1-0/+18
To better organize the information, add a microcontrollers section and move/link the GuC, HuC and DMC documentation under it. Also add a small intro. Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Michal Wajdeczko <[email protected]> Acked-by: Anna Karas <[email protected]> Reviewed-by: Martin Peres <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-17coccinelle: api/devm_platform_ioremap_resource: remove useless scriptAlexandre Belloni1-60/+0
While it is useful for new drivers to use devm_platform_ioremap_resource, this script is currently used to spam maintainers, often updating very old drivers. The net benefit is the removal of 2 lines of code in the driver but the review load for the maintainers is huge. As of now, more that 560 patches have been sent, some of them obviously broken, as in: https://lore.kernel.org/lkml/[email protected]/ Remove the script to reduce the spam. Signed-off-by: Alexandre Belloni <[email protected]> Acked-by: Julia Lawall <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2019-10-17ALSA: hda - Force runtime PM on Nvidia HDMI codecsLukas Wunner1-0/+2
Przemysław Kopa reports that since commit b516ea586d71 ("PCI: Enable NVIDIA HDA controllers"), the discrete GPU Nvidia GeForce GT 540M on his 2011 Samsung laptop refuses to runtime suspend, resulting in a power regression and excessive heat. Rivera Valdez witnesses the same issue with a GeForce GT 525M (GF108M) of the same era, as does another Arch Linux user named "R0AR" with a more recent GeForce GTX 1050 Ti (GP107M). The commit exposes the discrete GPU's HDA controller and all four codecs on the controller do not set the CLKSTOP and EPSS bits in the Supported Power States Response. They also do not set the PS-ClkStopOk bit in the Get Power State Response. hda_codec_runtime_suspend() therefore does not call snd_hdac_codec_link_down(), which prevents each codec and the PCI device from runtime suspending. The same issue is present on some AMD discrete GPUs and we addressed it by forcing runtime PM despite the bits not being set, see commit 57cb54e53bdd ("ALSA: hda - Force to link down at runtime suspend on ATI/AMD HDMI"). Do the same for Nvidia HDMI codecs. Fixes: b516ea586d71 ("PCI: Enable NVIDIA HDA controllers") Link: https://bbs.archlinux.org/viewtopic.php?pid=1865512 Link: https://bugs.freedesktop.org/show_bug.cgi?id=75985#c81 Reported-by: Przemysław Kopa <[email protected]> Reported-by: Rivera Valdez <[email protected]> Signed-off-by: Lukas Wunner <[email protected]> Cc: Daniel Drake <[email protected]> Cc: [email protected] # v5.3+ Link: https://lore.kernel.org/r/3086bc75135c1e3567c5bc4f3cc4ff5cbf7a56c2.1571324194.git.lukas@wunner.de Signed-off-by: Takashi Iwai <[email protected]>
2019-10-17drm/lima: add __GFP_NOWARN flag to all dma_alloc_wcQiang Yu2-3/+3
This prevent CMA printing dumy "PFNs busy" info which is caused by alloc fail re-try case. Reviewed-by: Vasily Khoruzhick <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-17drm/lima: use drm_gem_(un)lock_reservationsQiang Yu1-58/+6
Simplify the driver code with DRM GEM helper function. v2: improve commit comment. Reviewed-by: Vasily Khoruzhick <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-17drm/lima: use drm_gem_shmem_helpersQiang Yu12-360/+145
Do not need to maintain our own shmem memory management code as drm_gem_shmem_helpers provides it. And we can also benifit from the work of others with shared code. This is also a preparation for implementing buffer madv. Reviewed-by: Vasily Khoruzhick <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-17Merge tag 'platform-drivers-x86-v5.4-3' of ↵Linus Torvalds3-14/+2
git://git.infradead.org/linux-platform-drivers-x86 Pull x86 platform driver fixes from Andy Shevchenko: - Users of Intel P-Unit IPC driver might be surprised by harmless warning. Thus, switch to API which doesn't issue a warning at all. - I²C multi-instantiate driver continues to add slave devices even when IRQ resource is not found. For devices in the market IRQ resource is mandatory, so, fail the ->probe() of the parent driver to avoid slaves being probed. - Avoid compiler warning due to unused variable in Classmate laptop driver. * tag 'platform-drivers-x86-v5.4-3' of git://git.infradead.org/linux-platform-drivers-x86: platform/x86: i2c-multi-instantiate: Fail the probe if no IRQ provided platform/x86: intel_punit_ipc: Avoid error message when retrieving IRQ platform/x86: classmate-laptop: remove unused variable
2019-10-17dm cache: fix bugs when a GFP_NOWAIT allocation failsMikulas Patocka1-26/+2
GFP_NOWAIT allocation can fail anytime - it doesn't wait for memory being available and it fails if the mempool is exhausted and there is not enough memory. If we go down this path: map_bio -> mg_start -> alloc_migration -> mempool_alloc(GFP_NOWAIT) we can see that map_bio() doesn't check the return value of mg_start(), and the bio is leaked. If we go down this path: map_bio -> mg_start -> mg_lock_writes -> alloc_prison_cell -> dm_bio_prison_alloc_cell_v2 -> mempool_alloc(GFP_NOWAIT) -> mg_lock_writes -> mg_complete the bio is ended with an error - it is unacceptable because it could cause filesystem corruption if the machine ran out of memory temporarily. Change GFP_NOWAIT to GFP_NOIO, so that the mempool code will properly wait until memory becomes available. mempool_alloc with GFP_NOIO can't fail, so remove the code paths that deal with allocation failure. Cc: [email protected] Signed-off-by: Mikulas Patocka <[email protected]> Signed-off-by: Mike Snitzer <[email protected]>
2019-10-17Merge tag 'gpio-v5.4-3' of ↵Linus Torvalds5-11/+47
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO fixes from Linus Walleij: "The fixes pertain to a problem with initializing the Intel GPIO irqchips when adding gpiochips. Andy fixed it up elegantly by adding a hardware initialization callback to the struct gpio_irq_chip so let's use this. Tested and verified on the target hardware" * tag 'gpio-v5.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: gpio: lynxpoint: set default handler to be handle_bad_irq() gpio: merrifield: Move hardware initialization to callback gpio: lynxpoint: Move hardware initialization to callback gpio: intel-mid: Move hardware initialization to callback gpiolib: Initialize the hardware with a callback gpio: merrifield: Restore use of irq_base
2019-10-17dt/bindings: display: Add optional property node define for Mali DP500Wen He1-0/+3
Add optional property node 'arm,malidp-arqos-value' for the Mali DP500. This property describe the ARQoS levels of DP500's QoS signaling. Signed-off-by: Wen He <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Liviu Dudau <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-10-17drm/qxl: Fix randbuild errorYueHaibing1-0/+1
If DEM_QXL is y and DRM_TTM_HELPER is m, building fails: drivers/gpu/drm/qxl/qxl_object.o: undefined reference to `drm_gem_ttm_print_info' Select DRM_TTM_HELPER to fix this. Fixes: 78d54f1f6a33 ("drm/qxl: use drm_gem_ttm_print_info") Signed-off-by: YueHaibing <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Gerd Hoffmann <[email protected]>
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