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2018-07-24Merge tag 'fsi-updates-2018-07-24' of ↵Greg Kroah-Hartman13-62/+2252
git://git.kernel.org/pub/scm/linux/kernel/git/benh/linux-fsi into char-misc-testing Ben writes: This adds support for offloading the FSI low level bitbanging to the ColdFire coprocessor of the Aspeed SoCs. All the pre-requisites have already been merged, this is the final piece in the puzzle. This branch also pull gpio/ib-aspeed which is a topic branch already in gpio/for-next (and thus in next) whic contains pre-requisites. Finally, there's also a bug fix to the sbefifo driver for some inconsistent use of a mutex in the error handling code.
2018-07-23fsi: Add support for device-tree provided chip IDsBenjamin Herrenschmidt1-0/+24
They get retrieved from the device-tree and exposed as an attribute in sysfs Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2018-07-23dt-bindings: fsi: Add optional chip-id to CFAMsBenjamin Herrenschmidt1-0/+5
This represents a physical chip in the system and allows a stable numbering scheme to be passed to udev for userspace to recognize which chip is which. Signed-off-by: Benjamin Herrenschmidt <[email protected]> Acked-by: Rob Herring <[email protected]>
2018-07-23fsi: sbefifo: Fix inconsistent use of ffdc mutexBenjamin Herrenschmidt1-4/+9
Some of the exit path missed the unlock. Move the mutex to an outer function to avoid the problem completely Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2018-07-23fsi: master-ast-cf: Add new FSI master using Aspeed ColdFireBenjamin Herrenschmidt5-0/+1755
The Aspeed AST2x00 can contain a ColdFire v1 coprocessor which is currently unused on OpenPower systems. This adds an alternative to the fsi-master-gpio driver that uses that coprocessor instead of bit banging from the ARM core itself. The end result is about 4 times faster. The firmware for the coprocessor and its source code can be found at https://github.com/ozbenh/cf-fsi and is system specific. Signed-off-by: Benjamin Herrenschmidt <[email protected]>
2018-07-23dt-bindings: fsi: Document binding for the fsi-master-ast-cf "device"Benjamin Herrenschmidt1-0/+36
This isn't per-se a real device, it's a pseudo-device that represents the use of the Aspeed built-in ColdFire to implement the FSI protocol by bitbanging the GPIOs instead of doing it from the ARM core. Thus it's a drop-in replacement for the existing fsi-master-gpio pseudo-device for use on systems based on the Aspeed chips. It has most of the same properties, plus some more needed to operate the coprocessor. Signed-off-by: Benjamin Herrenschmidt <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2018-07-23devres: Add devm_of_iomap()Benjamin Herrenschmidt2-0/+40
There are still quite a few cases where a device might want to get to a different node of the device-tree, obtain the resources and map them. We have of_iomap() and of_io_request_and_map() but they both have shortcomings, such as not returning the size of the resource found (which can be useful) and not being "managed". This adds a devm_of_iomap() that provides all of these and should probably replace uses of the above in most drivers. Signed-off-by: Benjamin Herrenschmidt <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Reviewed-by: Joel Stanley <[email protected]>
2018-07-23Merge remote-tracking branch 'gpio/ib-aspeed' into upstream-readyBenjamin Herrenschmidt2554-20955/+29499
Merge the GPIO tree "ib-aspeed" topic branch which contains pre-requisites for subsequent changes. This branch is also in gpio "next".
2018-07-21uio: add SPDX license tagsStephen Hemminger6-10/+6
For those without any license text present or short reference to GPL, add SPDX tag. Signed-off-by: Stephen Hemminger <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-21uio: fix wrong return value from uio_mmap()Hailong Liu1-1/+1
uio_mmap has multiple fail paths to set return value to nonzero then goto out. However, it always returns *0* from the *out* at end, and this will mislead callers who check the return value of this function. Fixes: 57c5f4df0a5a0ee ("uio: fix crash after the device is unregistered") CC: Xiubo Li <[email protected]> Signed-off-by: Hailong Liu <[email protected]> Cc: stable <[email protected]> Signed-off-by: Jiang Biao <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-21uio: add SPDX license tagStephen Hemminger1-2/+1
Replace short statement in comment with proper SPDX license tag. Signed-off-by: Stephen Hemminger <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-21Merge tag 'extcon-next-for-4.19' of ↵Greg Kroah-Hartman3-18/+9
git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/extcon into char-misc-next Chanwoo writes: Update extcon for 4.19 Detailed description for this pull request: 1. Release locking when sending the connector state in extcon_sync() - Previously, extcon used the spinlock before calling the notifier_call_chain to prevent the scheduled out of task and to prevent the notification delay. When spinlock is locked for sending the notification, deadlock issue occured on the side of extcon consumer device. To fix this issue on extcon consumer device, release locking when sending the connector state. 2. Fix minor issues of extcon provider driver - extcon-intel-int3496.c uses 'linux/gpio/consumer.h' instead of 'linux/gpio.h' - extcon-usbc-cors-ec.c adds SPDX license and fix the wrong license information
2018-07-16misc: vexpress/syscfg: Use devm_ioremap_resource() to map memorySudeep Holla1-7/+3
Instead of checking the return value of platform_get_resource(), we can use devm_ioremap_resource() which has the NULL pointer check and the memory region requesting. devm_ioremap_resource is designed to replace calls to devm_request_mem_region followed by devm_ioremap, so let's use the same. Cc: Lorenzo Pieralisi <[email protected]> Signed-off-by: Sudeep Holla <[email protected]> Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-16drivers/misc: Aspeed LPC snoop output using misc chardevRobert Lippert1-10/+74
Provides the data bytes snooped over the LPC snoop bus to userspace as a (blocking) misc character device. Bytes output from the host using LPC I/O transactions to the snooped port can be watched or retrieved from the character device using a simple command like this: ~# od -w1 -A n -t x1 /dev/aspeed-lpc-snoop0 10 de ad c0 ff ee Signed-off-by: Robert Lippert <[email protected]> Signed-off-by: Patrick Venture <[email protected]> Signed-off-by: Benjamin Fair <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-16mei: bus: suppress sign-compare warningsTomas Winkler1-3/+3
Comparison between signed and unsigned warnings and associated type promotion may cause error condition not be detected. The type promotion issue in mei bus was addressed by two patches: commit b40b3e9358fb ("mei: bus: type promotion bug in mei_nfc_if_version()") commit cf1ed2c59b98 ("mei: bus: type promotion bug in mei_fwver()") Now it is possible to suppress the warning, by adding proper casting to move out of radar. Signed-off-by: Tomas Winkler <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-16gnss: fix potential error pointer dereferenceDan Carpenter1-2/+2
The gnss_allocate_device() function returns a mix of NULL and error pointers on error. It should only return one or the other. Since the callers both check for NULL, I've modified it to return NULL on error. Fixes: 2b6a44035143 ("gnss: add GNSS receiver subsystem") Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-16gnss: ubx: make struct ubx_gserial_ops staticColin Ian King1-1/+1
The structure ubx_gserial_ops is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warning: symbol 'ubx_gserial_ops' was not declared. Should it be static? Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-16virtio: virtconsole: Use seq_file for debugfs operationsTuomas Tynkkynen1-38/+22
Simplifies the code and is more conventional to what's used in the rest of the kernel for debugfs ops. Signed-off-by: Tuomas Tynkkynen <[email protected]> Reviewed-by: Amit Shah <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-16vme: ca91cx42: remove redundant variable iColin Ian King1-2/+0
Variable i is being assigned but is never used hence it is redundant and can be removed. Cleans up clang warning: warning: variable 'i' set but not used [-Wunused-but-set-variable] Signed-off-by: Colin Ian King <[email protected]> Reviewed-by: Martyn Welch <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-16Merge 4.18-rc5 into char-misc-nextGreg Kroah-Hartman789-4029/+6632
We want the char-misc fixes in here as well. Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15Linux 4.18-rc5Linus Torvalds1-1/+1
2018-07-15Merge tag 'armsoc-fixes' of ↵Linus Torvalds4-3/+49
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: - A fix for OMAP5 and DRA7 to make the branch predictor hardening settings take proper effect on secondary cores - Disable USB OTG on am3517 since current driver isn't working - Fix thermal sensor register settings on Armada 38x - Fix suspend/resume IRQs on pxa3xx * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: dts: am3517.dtsi: Disable reference to OMAP3 OTG controller ARM: DRA7/OMAP5: Enable ACTLR[0] (Enable invalidates of BTB) for secondary cores ARM: pxa: irq: fix handling of ICMR registers in suspend/resume ARM: dts: armada-38x: use the new thermal binding
2018-07-15parport: ieee1284: mark expected switch fall-throughsGustavo A. R. Silva1-1/+2
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Signed-off-by: Gustavo A. R. Silva <[email protected]> Signed-off-by: Sudip Mukherjee <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15parport: sunbpp: fix error return codeJulia Lawall1-2/+6
Return an error code on failure. Change leading spaces to tab on the first if. Problem found using Coccinelle. Signed-off-by: Julia Lawall <[email protected]> Signed-off-by: Sudip Mukherjee <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15eventpoll.h: wrap casts in () properlyGreg Kroah-Hartman1-4/+4
When importing the latest copy of the kernel headers into Bionic, Christpher and Elliott noticed that the eventpoll.h casts were not wrapped in (). As it is, clang complains about macros without surrounding (), so this makes it a pain for userspace tools. So fix it up by adding another () pair, and make them line up purty by using tabs. Fixes: 65aaf87b3aa2 ("add EPOLLNVAL, annotate EPOLL... and event_poll->event") Reported-by: Christopher Ferris <[email protected]> Reported-by: Elliott Hughes <[email protected]> Cc: stable <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Al Viro <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15nvmem: imx-ocotp: add support for imx6sllAnson Huang1-0/+7
i.MX6SLL is a new SoC of i.MX6 family, enable ocotp driver support for this SoC. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15dt-bindings: nvmem: imx-ocotp: add compatible string for imx6sllAnson Huang1-1/+2
Add new compatible string for i.MX6SLL SOC. Signed-off-by: Anson Huang <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15nvmem: Add Spreadtrum SC27XX efuse supportFreeman Liu3-1/+277
This patch add the efuse driver which is embeded in Spreadtrum SC27XX series PMICs. The sc27xx efuse contains 32 blocks and each block's data width is 16 bits. Signed-off-by: Freeman Liu <[email protected]> Signed-off-by: Baolin Wang <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15dt-bindings: nvmem: Add Spreadtrum SC27XX efuse controller documentationBaolin Wang1-0/+52
This patch adds the binding documentation for Spreadtrum SC27XX series PMICs efuse controller device. Signed-off-by: Baolin Wang <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15MAINTAINERS: add entry for FPGA DFL driversWu Hao1-0/+8
Add entry for FPGA Device Feature List (DFL) drivers. Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls supportWu Hao5-3/+591
DMA memory regions are required for Accelerated Function Unit (AFU) usage. These two ioctls allow user space applications to map user memory regions for dma, and unmap them after use. Iova is returned from driver to user space application via DFL_FPGA_PORT_DMA_MAP ioctl. Application needs to unmap it after use, otherwise, driver will unmap them in device file release operation. Each AFU has its own rb tree to keep track of its mapped DMA regions. Ioctl interfaces: * DFL_FPGA_PORT_DMA_MAP Do the dma mapping per user_addr and length provided by user. Return iova in provided struct dfl_fpga_port_dma_map. * DFL_FPGA_PORT_DMA_UNMAP Unmap the dma region per iova provided by user. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: afu: add afu sub feature supportXiao Guangrong6-7/+508
User Accelerated Function Unit sub feature exposes the MMIO region of the AFU. After valid PR bitstream is programmed and the port is enabled, then this MMIO region could be accessed. This patch adds support to enumerate the AFU MMIO region and expose it to userspace via mmap file operation. Below interfaces are exposed to user: Sysfs interface: * /sys/class/fpga_region/<regionX>/<dfl-port.x>/afu_id Read-only. Indicate which PR bitstream is programmed to this AFU. Ioctl interfaces: * DFL_FPGA_PORT_GET_INFO Provide info to userspace on the number of supported region. Only UAFU region is supported now. * DFL_FPGA_PORT_GET_REGION_INFO Provide region information, including access permission, region size, offset from the start of device fd. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: afu: add DFL_FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls supportWu Hao1-0/+11
DFL_FPGA_GET_API_VERSION and DFL_FPGA_CHECK_EXTENSION ioctls are common ones which need to be supported by all feature devices drivers including FME and AFU. This patch implements above 2 ioctls in FPGA Accelerated Function Unit (AFU) driver. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: afu: add header sub feature supportWu Hao3-1/+102
The port header register set is always present for port, it is mainly for capability, control and status of the ports that AFU connected to. This patch implements header sub feature support. Below user interfaces are created by this patch. Sysfs interface: * /sys/class/fpga_region/<regionX>/<dfl-port.x>/id Read-only. Port ID. Ioctl interface: * DFL_FPGA_PORT_RESET Reset the FPGA Port and its AFU. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: afu: add port ops supportWu Hao1-1/+121
This patch registers the port ops into the global list in the DFL framework, and it allows other modules to use the port ops. And This patch includes the implementation of the get_id and enable_set ops too. Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: add FPGA Accelerated Function Unit driver basic frameworkWu Hao3-0/+173
On DFL FPGA devices, the Accelerated Function Unit (AFU), can be reprogrammed for different functions. It connects to the FPGA infrastructure (static FPGA region) via a Port. Port CSRs are implemented separately from the AFU CSRs to provide control and status of the Port. Once valid PR bitstream is programmed into the AFU, it allows access to the AFU CSRs in the AFU MMIO space. This patch only implements basic driver framework for AFU, including device file operation framework. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: fme-region: add support for compat_idWu Hao1-0/+1
This patch adds compat_id support, it reuses fme manager's compat id, as the per region compat id is actually from the fme manager's register. Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: add fpga region platform driver for FMEWu Hao3-0/+95
This patch adds fpga region platform driver for FPGA Management Engine. It register an fpga region with given fpga manager / bridge device. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: add fpga bridge platform driver for FMEWu Hao3-0/+121
This patch adds fpga bridge platform driver for FPGA Management Engine. It implements the enable_set callback for fpga bridge. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: fme-mgr: add compat_id supportWu Hao1-0/+15
This patch adds compat_id support to fme manager driver, it reads the ID from the hardware register. And it could be used for compatibility check before partial reconfiguration. Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: add fpga manager platform driver for FMEWu Hao3-0/+341
This patch adds fpga manager driver for FPGA Management Engine (FME). It implements fpga_manager_ops for FPGA Partial Reconfiguration function. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Kang Luwei <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: fme: add partial reconfiguration sub feature supportKang Luwei6-2/+671
Partial Reconfiguration (PR) is the most important function for FME. It allows reconfiguration for given Port/Accelerated Function Unit (AFU). It creates platform devices for fpga-mgr, fpga-regions and fpga-bridges, and invokes fpga-region's interface (fpga_region_program_fpga) for PR operation once PR request received via ioctl. Below user space interface is exposed by this sub feature. Ioctl interface: * DFL_FPGA_FME_PORT_PR Do partial reconfiguration per information from userspace, including target port(AFU), buffer size and address info. It returns error code to userspace if failed. For detailed PR error information, user needs to read fpga-mgr's status sysfs interface. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Kang Luwei <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: fme: add DFL_FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls supportWu Hao3-0/+63
DFL_FPGA_GET_API_VERSION and DFL_FPGA_CHECK_EXTENSION ioctls are common ones which need to be supported by all feature devices drivers including FME and AFU. Userspace application can use these ioctl interfaces to get the API info and check if specific extension is supported or not in current driver. This patch implements above 2 ioctls in FPGA Management Engine (FME) driver. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: fme: add header sub feature supportKang Luwei2-0/+91
The Header Register set is always present for FPGA Management Engine (FME), this patch implements init and uinit function for header sub feature and introduces several read-only sysfs interfaces for the capability and status. Sysfs interfaces: * /sys/class/fpga_region/<regionX>/<dfl-fme.x>/ports_num Read-only. Number of ports implemented * /sys/class/fpga_region/<regionX>/<dfl-fme.x>/bitstream_id Read-only. Bitstream (static FPGA region) identifier number. It contains the detailed version and other information of this static FPGA region. * /sys/class/fpga_region/<regionX>/<dfl-fme.x>/bitstream_metadata Read-only. Bitstream (static FPGA region) meta data. It contains the synthesis date, seed and other information of this static FPGA region. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Kang Luwei <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: add FPGA Management Engine driver basic frameworkKang Luwei3-0/+171
The FPGA Management Engine (FME) provides power, thermal management, performance counters, partial reconfiguration and other functions. For each function, it is packaged into a private feature linked to the FME feature device in the 'Device Feature List'. It's a platform device created by DFL framework. This patch adds the basic framework of FME platform driver. It defines sub feature drivers to handle the different sub features, including init, uinit and ioctl. It also registers the file operations for the device file. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Kang Luwei <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl-pci: add enumeration for feature devicesWu Hao1-2/+142
The Device Feature List (DFL) is implemented in MMIO and features are linked via the DFLs. This patch enables pcie driver to prepare enumeration information (e.g. locations of all device feature lists in MMIO) and use common APIs provided by the Device Feature List framework to enumerate each feature device linked. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Zhang Yi <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: add FPGA DFL PCIe device driverZhang Yi3-0/+121
This patch implements the basic framework of the driver for FPGA PCIe device which implements the Device Feature List (DFL) in its MMIO space. This driver is verified on Intel(R) PCIe-based FPGA DFL devices, including both integrated (e.g. Intel Server Platform with In-package FPGA) and discrete (e.g. Intel FPGA PCIe Acceleration Cards) solutions. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Zhang Yi <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: add dfl_fpga_check_port_id function.Wu Hao2-0/+23
This patch adds one common function in DFL framework. It uses port_ops get_id callback to get port id and compare it with given value. This function could be used as match function of the dfl_fpga_cdev_find_port function. Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: add dfl_fpga_port_ops support.Wu Hao2-0/+100
In some cases, other DFL driver modules may need to access some port operations, e.g. disable / enable port for partial reconfiguration in FME module. In order to avoid dependency between port and FME modules, this patch introduces the dfl_fpga_port_ops support in DFL framework. A global dfl_fpga_port_ops list is added in the DFL framework, and it allows other DFL modules to use these port operations registered to this list, even in virtualization case, the port platform device is turned into VF / guest VM and hidden in host, the registered port_ops is still usable. It resolves the dependency issues between modules, but once get port ops API returns a valid port ops, that means related port driver module has been module_get to prevent from unexpected unload, and put port ops API must be invoked after use. These APIs introduced by this patch is listed below: * dfl_fpga_port_ops_add add one port ops to the global list. * dfl_fpga_port_ops_del del one port ops from the global list. * dfl_fpga_port_ops_get / dfl_fpga_port_ops_put get/put the port ops before/after use. Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-07-15fpga: dfl: add feature device infrastructureXiao Guangrong2-1/+152
This patch abstracts the common operations of the sub features and defines the feature_ops data structure, including init, uinit and ioctl function pointers. And this patch adds some common helper functions for FME and AFU drivers, e.g. dfl_feature_dev_use_begin/end which are used to ensure exclusive usage of the feature device file. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Kang Luwei <[email protected]> Signed-off-by: Zhang Yi <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
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