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2017-01-03MIPS: generic/kexec: add support for a DTB passed in a separate bufferMarcin Nowakowski2-0/+45
Signed-off-by: Marcin Nowakowski <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14615/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: kexec: add debug info about the new kexec'ed imageMarcin Nowakowski1-0/+22
Print details of the new kexec image loaded. Based on the original code from commit 221f2c770e10d ("arm64/kexec: Add pr_debug output") Signed-off-by: Marcin Nowakowski <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14614/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: kexec: Do not reserve invalid crashkernel memory on bootMarcin Nowakowski1-0/+5
Do not reserve memory for the crashkernel if the commandline argument points to a wrong location. This can happen if the location is specified wrong or if the same commandline is reused when starting the crashkernel - in the latter case the reserved memory would point to the location from which the crashkernel is executing. Signed-off-by: Marcin Nowakowski <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14612/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: fix mem=X@Y commandline processingMarcin Nowakowski1-0/+4
When a memory offset is specified through the commandline, add the memory in range PHYS_OFFSET:Y as reserved memory area. Otherwise the bootmem allocator is initialised with low page equal to min_low_pfn = PHYS_OFFSET, and in free_all_bootmem will process pages starting from min_low_pfn instead of PFN(Y). Signed-off-by: Marcin Nowakowski <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14613/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: relocate: Optionally relocate the DTBMarcin Nowakowski1-2/+36
If the DTB is located in the target memory area for the relocated kernel it needs to be relocated as well before kernel relocation takes place. After copying the DTB use the new plat_fdt_relocated() API from the relocated kernel to ensure the relocated kernel updates any information that it may have cached about the location of the DTB. plat_fdt_relocated is declared as a weak symbol so that platforms that do not require it do not need to implement the method. Signed-off-by: Marcin Nowakowski <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14616/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: platform: Allow for DTB to be moved during kernel relocationMarcin Nowakowski2-0/+26
Add plat_fdt_relocated(void*) API to allow the kernel relocation code to update platform's information about the DTB location if the DTB had to be moved due to being placed in a location used by the relocated kernel. Signed-off-by: Marcin Nowakowski <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14611/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Use early_init_fdt_reserve_self to protect DTB locationMarcin Nowakowski2-0/+11
early_init_fdt_reserve_self is used to tell the boot memory allocator that a memory is occupied by the DTB, so add it in the MIPS init code to ensure information about the DTB is added to the boot memory array. Signed-off-by: Marcin Nowakowski <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14610/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: init: Ensure bootmem does not corrupt reserved memoryMarcin Nowakowski1-3/+71
Current init code initialises bootmem allocator with all of the low memory that it assumes is available, but does not check for reserved memory block, which can lead to corruption of data that may be stored there. Move bootmem's allocation map to a location that does not cross any reserved regions Signed-off-by: Marcin Nowakowski <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14609/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: init: Ensure reserved memory regions are not added to bootmemMarcin Nowakowski1-0/+4
Memories managed through boot_mem_map are generally expected to define non-crossing areas. However, if part of a larger memory block is marked as reserved, it would still be added to bootmem allocator as an available block and could end up being overwritten by the allocator. Prevent this by explicitly marking the memory as reserved it if exists in the range used by bootmem allocator. Signed-off-by: Marcin Nowakowski <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14608/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Do not request resources for crashkernel if one isn't definedMarcin Nowakowski1-0/+3
When KEXEC is enabled but crashkernel details are not passed through the kernel commandline unnecessary resources are requested (start==end==0) Signed-off-by: Marcin Nowakowski <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14607/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: elfcore: add correct copy_regs implementationsMarcin Nowakowski1-0/+6
MIPS does not currently define ELF_CORE_COPY_REGS macros and as a result the generic implementation is used. The generic version attempts to do directly map (struct pt_regs) into (elf_gregset_t), which isn't correct for MIPS platforms and also triggers a BUG() at runtime in include/linux/elfcore.h:16 (BUG_ON(sizeof(*elfregs) != sizeof(*regs))) [[email protected]: Add semicolons to the macro definitions as I do not apply https://patchwork.linux-mips.org/patch/14588/ for now.] Signed-off-by: Marcin Nowakowski <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14586/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Move register dump routines out of ptrace codeMarcin Nowakowski3-32/+49
Current register dump methods for MIPS are implemented inside ptrace methods, but there will be other uses in the kernel for them, so keep them separately in process.c and use those definitions for ptrace instead. Signed-off-by: Marcin Nowakowski <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14587/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Kconfig: Fix indentation for kexec-related entriesMarcin Nowakowski1-7/+7
Kconfig entries are not aligned properly, so remove incorrect whitespace. Signed-off-by: Marcin Nowakowski <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14631/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: kexec: remove SMP_DUMPMarcin Nowakowski3-25/+2
SMP_DUMP has been added as a new IPI signal when kexec support was added for Cavium Octeon CPUs ('commit 7aa1c8f47e7e ("MIPS: kdump: Add support")'. However, the new signal doesn't appear to ever have a proper handler added (octeon_message_functions[] array has an empty handler for it), and generic IPI handlers now trigger a BUG() on unhandled signal. As the method is unused remove it completely and replace its only invocation with a smp_call_function(). [[email protected]: Renumber SMP_ASK_C0COUNT to avoid numbering gaps.] Signed-off-by: Marcin Nowakowski <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14630/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Add support for ARCH_MMAP_RND_{COMPAT_}BITSMatt Redfearn2-5/+21
arch_mmap_rnd() uses hard-coded limits of 16MB for the randomisation of mmap within 32bit processes and 256MB in 64bit processes. Since v4.4 other arches support tuning this value in /proc/sys/vm/mmap_rnd_bits. Add support for this to MIPS. Set the minimum(default) number of bits randomisation for 32bit to 8 - which with 4k pagesize is unchanged from the current 16MB total randomness. The minimum(default) for 64bit is 12bits, again with 4k pagesize this is the same as the current 256MB. This patch is necessary for MIPS32 to pass the Android CTS tests, with the number of random bits set to 15. Signed-off-by: Matt Redfearn <[email protected]> Reviewed-by: Kees Cook <[email protected]> Cc: Paul Gortmaker <[email protected]> Cc: Daniel Cashman <[email protected]> Cc: Andrew Morton <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14617/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Lantiq: Activate more drivers in default configurationHauke Mehrtens1-1/+12
This activates the following functionalities: * SMP support (used on xRX200) * PCI support * NAND driver * PHY driver * UART * Watchdog * USB 2.0 controller These driver are driving different IP cores found on the supported SoCs. Signed-off-by: Hauke Mehrtens <[email protected]> Acked-by: John Crispin <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14628/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: lantiq: Refresh default configurationHauke Mehrtens1-7/+1
Just generate a configuration based on this default configuration and store it again. This removed some old configuration options. Signed-off-by: Hauke Mehrtens <[email protected]> Acked-by: John Crispin <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14629/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03of: Add check to of_scan_flat_dt() before accessing initial_boot_paramsTobias Wolf1-3/+6
An empty __dtb_start to __dtb_end section might result in initial_boot_params being null for arch/mips/ralink. This showed that the boot process hangs indefinitely in of_scan_flat_dt(). Signed-off-by: Tobias Wolf <[email protected]> Cc: Sergei Shtylyov <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14605/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03ralink: Introduce fw_passed_dtb to arch/mips/ralinkTobias Wolf1-2/+10
This patch adds fw_passed_dtb to arch/mips/ralink to support CONFIG_MIPS_RAW_APPENDED_DTB. Furthermore it adds a check that __dtb_start is not the same address as __dtb_end. Signed-off-by: Tobias Wolf <[email protected]> Acked-by: John Crispin <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14662/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Loongson1: Add watchdog support for Loongson1 boardYang Ling6-10/+37
The patch adds watchdog support for Loongson1 board. Signed-off-by: Yang Ling <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14644/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Loongson1: Remove several redundant RTC-related macrosYang Ling3-19/+38
Move the RTC-related macros to regs-rtc.h. Signed-off-by: Yang Ling <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14642/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Remove RESTORE_ALL_AND_RETPaul Burton1-8/+0
The RESTORE_ALL_AND_RET macro is never used. Remove the dead code. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14411/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Allow pre-r6 emulation on SMP MIPSr6 kernelsPaul Burton1-3/+1
There's no reason for the pre-r6 instruction emulation code to be limited to uniprocessor kernels. We already emulate atomic memory access instructions in a way that works for SMP systems, and nothing else should be affected. Remove the artificial limitation, allowing pre-r6 instruction emulation to be used with SMP kernels. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14410/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Cleanup LLBit handling in switch_toPaul Burton1-6/+12
Commit 7c151d3d5d7a ("MIPS: Make use of the ERETNC instruction on MIPS R6") began clearing LLBit during context switches, but did so on all systems where it is writable for unclear reasons & did so from a macro with "software_ll_bit" in its name, which is intended to operate on the ll_bit variable used by ll/sc emulation for old CPUs. We do now need to clear LLBit on MIPSr6 systems where we'll use eretnc to return to userland, but we don't need to do so on MIPSr5 systems with a writable LLBit. Move the clear to its own appropriately named macro, do it only for MIPSr6 systems & comment about why. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14409/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Remove r2_emul_return from struct thread_infoPaul Burton5-22/+4
The r2_emul_return field in struct thread_info was used in order to take an alternate codepath when returning to userland, which (besides not implementing certain features) effectively used the eretnc instruction in place of eret. The difference is that eretnc doesn't clear LLBit, and therefore doesn't cause a linked load & store sequence to fail due to emulation like eret would. The reason eret would usually be used to clear LLBit is so that after context switching we ensure that a load performed by one task doesn't influence another task. However commit 7c151d3d5d7a ("MIPS: Make use of the ERETNC instruction on MIPS R6") which introduced the r2_emul_return field and conditional use of eretnc also for some reason began explicitly clearing LLBit during context switches - despite retaining the use of eret for everything but returns from the pre-r6 instruction emulation code. As LLBit is cleared upon context switches anyway, simplify this by using eretnc unconditionally for MIPSr6 kernels. This allows us to remove the 4 byte r2_emul_return boolean from struct thread_info, simplify the return to user code in entry.S and avoid the overhead of tracking & checking state which we don't need. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14408/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: DTS: img: add device tree for Marduk boardRahul Bedarkar4-0/+188
Add support for Imagination Technologies' Marduk board which is based on Pistachio SoC. It is also known as Creator Ci40. Marduk is legacy name and will be there for decades. Documentation for this board can be found on https://docs.creatordev.io/ci40/ This patch adds initial support for board with following peripherals: * PWM based heartbeat LED * GPIO based buttons * SPI NOR flash on SPI1 * UART0 and UART1 * SD card * Ethernet * USB * PWM * ADC * I2C Signed-off-by: Rahul Bedarkar <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: James Hartley <[email protected]> Cc: Mark Rutland <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14394/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: DTS: Add base device tree for Pistachio SoCRahul Bedarkar2-1/+925
Add support for the base Device Tree for Imagination Technologies' Pistachio SoC. This commit supports the following peripherals: * Clocks * Pinctrl and GPIO * UART * SPI * I2C * PWM * ADC * Watchdog * Ethernet * MMC * DMA engine * Crypto * I2S * SPDIF * Internal DAC * Timer * USB * IR * Interrupt Controller Signed-off-by: Rahul Bedarkar <[email protected]> Acked-by: James Hartley <[email protected]> Cc: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14393/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: traps: Ensure L1 & L2 ECC checking match for CM3 systemsPaul Burton2-3/+67
On systems with CM3, we must ensure that the L1 & L2 ECC enables are set to the same value. This is presumed by the hardware & cache corruption can occur when it is not the case. Support enabling & disabling the L2 ECC checking on CM3 systems where this is controlled via a GCR, and ensure that it matches the state of L1 ECC checking. Remove I6400 from the switch statement it will no longer hit, and which was incorrect since the L2 ECC enable bit isn't in the CP0 ErrCtl register. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14413/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: R2-on-R6 MULTU/MADDU/MSUBU emulation bugfixLeonid Yegoshin1-6/+6
MIPS instructions MULTU, MADDU and MSUBU emulation requires registers HI/LO to be converted to signed 32bits before 64bit sign extension on MIPS64. Bug was found on running MIPS32 R2 test application on MIPS64 R6 kernel. Fixes: b0a668fb2038 ("MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6") Signed-off-by: Leonid Yegoshin <[email protected]> Reported-by: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14043/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Loongson1B: Modify DEFAULT_MEMSIZEKelvin Cheung1-1/+1
This patch changes DEFAULT_MEMSIZE to 64MB which is the memory size of latest EVB. Signed-off-by: Kelvin Cheung <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/13856/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Loongson1C: Remove ARCH_WANT_OPTIONAL_GPIOLIBKelvin Cheung1-1/+0
This patch removes ARCH_WANT_OPTIONAL_GPIOLIB due to upstream changes. Signed-off-by: Kelvin Cheung <[email protected]> Acked-by: Linus Walleij <[email protected]> Cc: Yang Ling <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/13855/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: BMIPS: Migrate interrupts during bmips_cpu_disableFlorian Fainelli1-0/+1
While we properly disabled the per-CPU timer interrupt, we also need to make sure that all interrupts that can possibly have this CPU in their smp_affinity mask also have a chance to see this interrupt migrated to a CPU not being taken offline. [[email protected]: Fix merge conflict.] Fixes: 230b6ff57552 ("MIPS: BMIPS: Mask off timer IRQs when hot-unplugging a CPU") Signed-off-by: Florian Fainelli <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14488/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: xilfpga: Update defconfigZubair Lutfullah Kakakhel1-1/+36
Update defconfig to enable emaclite, i2c and temp sensor on the xilfpga platform Signed-off-by: Zubair Lutfullah Kakakhel <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14595/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: xilfpga: Add DT node for AXI emacliteZubair Lutfullah Kakakhel1-0/+26
The xilfpga platform has a Xilinx AXI emaclite block. Add the DT node to use it. Signed-off-by: Zubair Lutfullah Kakakhel <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14596/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: xilfpga: Add DT node for AXI I2CZubair Lutfullah Kakakhel1-0/+22
The xilfpga platform has an AXI I2C Bus master with a temperature sensor connected to it. Add the device tree node to use them. Signed-off-by: Zubair Lutfullah Kakakhel <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14594/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: xilfpga: Update DT node and specify uart irqZubair Lutfullah Kakakhel1-0/+3
Update the DT node with the UART irq Signed-off-by: Zubair Lutfullah Kakakhel <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14593/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: xilfpga: Use Xilinx Interrupt ControllerZubair Lutfullah Kakakhel2-0/+13
IRQs from peripherals such as i2c/uart/ethernet come via the AXI Interrupt controller. Select it in Kconfig for xilfpga and add the DT node Signed-off-by: Zubair Lutfullah Kakakhel <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14592/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: xilfpga: Use irqchip instead of the legacy wayZubair Lutfullah Kakakhel1-5/+2
This prepares the code to use the Xilinx Interrupt Controller driver in drivers/irqchip/irq-xilinx-intc.c Signed-off-by: Zubair Lutfullah Kakakhel <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14591/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: ath79: Fix error handlingChristophe JAILLET1-1/+1
'clk_register_fixed_rate()' returns an error pointer in case of error, not NULL. So test it with IS_ERR. Signed-off-by: Christophe JAILLET <[email protected]> Acked-by: Aban Bedel <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14464/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: SMP-CPS: Don't BUG if a CPU fails to startMatt Redfearn1-1/+5
If there is no online CPU within a core which could receive the IPI to start another VP in that core, a BUG() is triggered. Instead print a warning and gracefully handle the failure such that the system remains usable, albeit without the requested secondary CPU. Signed-off-by: Matt Redfearn <[email protected]> Cc: Masahiro Yamada <[email protected]> Cc: James Hogan <[email protected]> Cc: Paul Burton <[email protected]> Cc: Qais Yousef <[email protected]> Cc: Andrew Morton <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14504/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: SMP: Remove cpu_callin_mapMatt Redfearn6-8/+0
The previous commit made cpu_callin_map redundant, since it is no longer used to signal secondary CPUs starting, or going offline. Remove it now. Signed-off-by: Matt Redfearn <[email protected]> Cc: Sebastian Andrzej Siewior <[email protected]> Cc: Qais Yousef <[email protected]> Cc: Masahiro Yamada <[email protected]> Cc: Huacai Chen <[email protected]> Cc: Kevin Cernekee <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Andrew Morton <[email protected]> Cc: James Hogan <[email protected]> Cc: Paul Burton <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: Anna-Maria Gleixner <[email protected]> Cc: Adam Buchbinder <[email protected]> Cc: Yang Shi <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14503/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: SMP: Use a completion event to signal CPU upMatt Redfearn2-9/+10
If a secondary CPU failed to start, for any reason, the CPU requesting the secondary to start would get stuck in the loop waiting for the secondary to be present in the cpu_callin_map. Rather than that, use a completion event to signal that the secondary CPU has started and is waiting to synchronise counters. Since the CPU presence will no longer be marked in cpu_callin_map, remove the redundant test from arch_cpu_idle_dead(). Signed-off-by: Matt Redfearn <[email protected]> Cc: Maciej W. Rozycki <[email protected]> Cc: Jiri Slaby <[email protected]> Cc: Paul Gortmaker <[email protected]> Cc: Chris Metcalf <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Qais Yousef <[email protected]> Cc: James Hogan <[email protected]> Cc: Paul Burton <[email protected]> Cc: Marcin Nowakowski <[email protected]> Cc: Andrew Morton <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14502/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Netlogic: Exclude netlogic,xlp-pic code from XLR buildsPaul Burton1-2/+2
Code in arch/mips/netlogic/common/irq.c which handles the XLP PIC fails to build in XLR configurations due to cpu_is_xlp9xx not being defined, leading to the following build failure: arch/mips/netlogic/common/irq.c: In function ‘xlp_of_pic_init’: arch/mips/netlogic/common/irq.c:298:2: error: implicit declaration of function ‘cpu_is_xlp9xx’ [-Werror=implicit-function-declaration] if (cpu_is_xlp9xx()) { ^ Although the code was conditional upon CONFIG_OF which is indirectly selected by CONFIG_NLM_XLP_BOARD but not CONFIG_NLM_XLR_BOARD, the failing XLR with CONFIG_OF configuration can be configured manually or by randconfig. Fix the build failure by making the affected XLP PIC code conditional upon CONFIG_CPU_XLP which is used to guard the inclusion of asm/netlogic/xlp-hal/xlp.h that provides the required cpu_is_xlp9xx function. [[email protected]: Fixed up as per Jayachandran's suggestion.] Signed-off-by: Paul Burton <[email protected]> Cc: Jayachandran C <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14524/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Remove unused HIGHMEM_DEBUG macroPaul Burton1-3/+0
We have a HIGHMEM_DEBUG macro defined in asm/highmem.h with a comment stating that it should be removed for production, and no users... Kill it. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14523/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Use Makefile.postlink to insert relocations into vmlinuxMatt Redfearn2-12/+35
When relocatable support for MIPS was merged, there was no support for an architecture to add a postlink step for vmlinux. This meant that only invoking a target within the boot directory, such as uImage, caused the relocations to be inserted into vmlinux. Building just the vmlinux target would result in a relocatable kernel with no relocation information present. Commit fbe6e37dab97 ("kbuild: add arch specific post-link Makefile") recified this situation, so MIPS can now define a postlink step to add relocation information into vmlinux, and remove the additional steps tacked onto boot targets. Signed-off-by: Matt Redfearn <[email protected]> Tested-by: Steven J. Hill <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/14554/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Handle microMIPS jumps in the same way as MIPS32/MIPS64 jumpsPaul Burton1-0/+2
is_jump_ins() checks for plain jump ("j") instructions since commit e7438c4b893e ("MIPS: Fix sibling call handling in get_frame_info") but that commit didn't make the same change to the microMIPS code, leaving it inconsistent with the MIPS32/MIPS64 code. Handle the microMIPS encoding of the jump instruction too such that it behaves consistently. Signed-off-by: Paul Burton <[email protected]> Fixes: e7438c4b893e ("MIPS: Fix sibling call handling in get_frame_info") Cc: Tony Wu <[email protected]> Cc: [email protected] Cc: <[email protected]> # v3.10+ Patchwork: https://patchwork.linux-mips.org/patch/14533/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Calculate microMIPS ra properly when unwinding the stackPaul Burton1-20/+63
get_frame_info() calculates the offset of the return address within a stack frame simply by dividing a the bottom 16 bits of the instruction, treated as a signed integer, by the size of a long. Whilst this works for MIPS32 & MIPS64 ISAs where the sw or sd instructions are used, it's incorrect for microMIPS where encodings differ. The result is that we typically completely fail to unwind the stack on microMIPS. Fix this by adjusting is_ra_save_ins() to calculate the return address offset, and take into account the various different encodings there in the same place as we consider whether an instruction is storing the ra/$31 register. With this we are now able to unwind the stack for kernels targetting the microMIPS ISA, for example we can produce: Call Trace: [<80109e1f>] show_stack+0x63/0x7c [<8011ea17>] __warn+0x9b/0xac [<8011ea45>] warn_slowpath_fmt+0x1d/0x20 [<8013fe53>] register_console+0x43/0x314 [<8067c58d>] of_setup_earlycon+0x1dd/0x1ec [<8067f63f>] early_init_dt_scan_chosen_stdout+0xe7/0xf8 [<8066c115>] do_early_param+0x75/0xac [<801302f9>] parse_args+0x1dd/0x308 [<8066c459>] parse_early_options+0x25/0x28 [<8066c48b>] parse_early_param+0x2f/0x38 [<8066e8cf>] setup_arch+0x113/0x488 [<8066c4f3>] start_kernel+0x57/0x328 ---[ end trace 0000000000000000 ]--- Whereas previously we only produced: Call Trace: [<80109e1f>] show_stack+0x63/0x7c ---[ end trace 0000000000000000 ]--- Signed-off-by: Paul Burton <[email protected]> Fixes: 34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.") Cc: Leonid Yegoshin <[email protected]> Cc: [email protected] Cc: <[email protected]> # v3.10+ Patchwork: https://patchwork.linux-mips.org/patch/14532/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Fix is_jump_ins() handling of 16b microMIPS instructionsPaul Burton1-3/+8
is_jump_ins() checks 16b instruction fields without verifying that the instruction is indeed 16b, as is done by is_ra_save_ins() & is_sp_move_ins(). Add the appropriate check. Signed-off-by: Paul Burton <[email protected]> Fixes: 34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.") Cc: Leonid Yegoshin <[email protected]> Cc: [email protected] Cc: <[email protected]> # v3.10+ Patchwork: https://patchwork.linux-mips.org/patch/14531/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Fix get_frame_info() handling of microMIPS function sizePaul Burton1-7/+5
get_frame_info() is meant to iterate over up to the first 128 instructions within a function, but for microMIPS kernels it will not reach that many instructions unless the function is 512 bytes long since we calculate the maximum number of instructions to check by dividing the function length by the 4 byte size of a union mips_instruction. In microMIPS kernels this won't do since instructions are variable length. Fix this by instead checking whether the pointer to the current instruction has reached the end of the function, and use max_insns as a simple constant to check the number of iterations against. Signed-off-by: Paul Burton <[email protected]> Fixes: 34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.") Cc: Leonid Yegoshin <[email protected]> Cc: [email protected] Cc: <[email protected]> # v3.10+ Patchwork: https://patchwork.linux-mips.org/patch/14530/ Signed-off-by: Ralf Baechle <[email protected]>
2017-01-03MIPS: Prevent unaligned accesses during stack unwindingPaul Burton1-35/+35
During stack unwinding we call a number of functions to determine what type of instruction we're looking at. The union mips_instruction pointer provided to them may be pointing at a 2 byte, but not 4 byte, aligned address & we thus cannot directly access the 4 byte wide members of the union mips_instruction. To avoid this is_ra_save_ins() copies the required half-words of the microMIPS instruction to a correctly aligned union mips_instruction on the stack, which it can then access safely. The is_jump_ins() & is_sp_move_ins() functions do not correctly perform this temporary copy, and instead attempt to directly dereference 4 byte fields which may be misaligned and lead to an address exception. Fix this by copying the instruction halfwords to a temporary union mips_instruction in get_frame_info() such that we can provide a 4 byte aligned union mips_instruction to the is_*_ins() functions and they do not need to deal with misalignment themselves. Signed-off-by: Paul Burton <[email protected]> Fixes: 34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.") Cc: Leonid Yegoshin <[email protected]> Cc: [email protected] Cc: <[email protected]> # v3.10+ Patchwork: https://patchwork.linux-mips.org/patch/14529/ Signed-off-by: Ralf Baechle <[email protected]>
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