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2019-04-05spi: tegra114: avoid reset call in atomic contextSowjanya Komatineni1-4/+5
This patch moves SPI controller reset out of spin lock. Signed-off-by: Sowjanya Komatineni <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-04-05spi: tegra114: de-assert CS before SPI mode changeSowjanya Komatineni1-6/+16
With SW CS, during the transfer completion CS is de-asserted by writing default command1 register value to SPI_COMMAND1 register. With this both mode and CS state are set at the same time and if current transfer mode is different to default SPI mode and if mode change happens prior to CS de-assert, clock polarity can change while CS is active before transfer finishes. This causes Slave to see spurious clock edges resulting in data mismatch. This patch fixes this by de-asserting CS before writing SPI_COMMAND1 to its default value so through out the transfer it will be in same SPI mode. Signed-off-by: Sowjanya Komatineni <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-04-04spi: Add missing error handling for CS GPIOsGeert Uytterhoeven1-0/+2
While devm_gpiod_get_index_optional() returns NULL if the GPIO is not present (i.e. -ENOENT), it may still return other error codes, like -EPROBE_DEFER. Currently these are not handled, leading to unrecoverable failures later in case of probe deferral: gpiod_set_consumer_name: invalid GPIO (errorpointer) gpiod_direction_output: invalid GPIO (errorpointer) gpiod_set_value_cansleep: invalid GPIO (errorpointer) gpiod_set_value_cansleep: invalid GPIO (errorpointer) gpiod_set_value_cansleep: invalid GPIO (errorpointer) Detect and propagate errors to fix this. Fixes: f3186dd876697e69 ("spi: Optionally use GPIO descriptors for CS GPIOs") Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-04-04spi: spi-gpio: Remove spi->controller_data commentGeert Uytterhoeven1-1/+0
The conversion from GPIO numbers to GPIO descriptors removed the use of spi->controller_data, but forgot to update a comment referring to it. Fixes: 9b00bc7b901ff672 ("spi: spi-gpio: Rewrite to use GPIO descriptors") Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-04-01spi: tegra114: reset controller on probeSowjanya Komatineni1-14/+18
Fixes: SPI driver can be built as module so perform SPI controller reset on probe to make sure it is in valid state before initiating transfer. Signed-off-by: Sowjanya Komatineni <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-04-01spi: tegra114: configure dma burst size to fifo trig levelSowjanya Komatineni1-22/+30
Fixes: Configure DMA burst size to be same as SPI TX/RX trigger levels to avoid mismatch. SPI FIFO trigger levels are calculated based on the transfer length. So this patch moves DMA slave configuration to happen before start of DMAs. Signed-off-by: Sowjanya Komatineni <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-04-01spi: tegra114: flush fifosSowjanya Komatineni1-9/+30
Fixes: Flush TX and RX FIFOs before start of new transfer and on FIFO overflow or underrun errors. Signed-off-by: Sowjanya Komatineni <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-04-01spi: tegra114: terminate dma and reset on transfer timeoutSowjanya Komatineni1-0/+9
Fixes: terminate DMA and perform controller reset on transfer timeout to clear the FIFO's and errors. Signed-off-by: Sowjanya Komatineni <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-04-01spi: tegra114: fix for unpacked mode transfersSowjanya Komatineni1-7/+36
Fixes: computation of actual bytes to fill/receive in/from FIFO in unpacked mode when transfer length is not a multiple of requested bits per word. unpacked mode transfers fails when the transfer includes partial bytes in the last word. Total words to be written/read to/from FIFO is computed based on transfer length and bits per word. Unpacked mode includes 0 padding bytes for partial words to align with bits per word and these extra bytes are also accounted for calculating bytes left to transfer in the current driver. This causes extra bytes access of tx/rx buffers along with buffer index position crossing actual length where remain_len becomes negative and due to unsigned type, negative value is a 32 bit representation of signed value and transferred bytes never meets the actual transfer length resulting in transfer timeout and a hang. This patch fixes this with proper computation of the actual bytes to fill in FIFO during transmit and the actual bytes to read from FIFO during receive ignoring 0 padded bytes. Signed-off-by: Sowjanya Komatineni <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-04-01spi: tegra114: clear packed bit for unpacked modeSowjanya Komatineni1-0/+2
Fixes: Clear packed bit when not using packed mode. Packed bit is not cleared when not using packed mode. This results in transfer timeouts for the unpacked mode transfers followed by the packed mode transfers. Signed-off-by: Sowjanya Komatineni <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-04-01spi: pic32: fix dma channels terminationCezary Gapinski1-1/+1
When timeout occurs DMA TX and RX channels should be stopped instead of stopping RX channel twice time. Signed-off-by: Cezary Gapinski <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-27spi: tegra20-slink: change chip select action orderRandolph Maaßen1-3/+9
To transfer via SPI the tegra20-slink driver first sets the command register, which contains the chip select value, and after that the command2 register, which contains the chip select line. This leads to a small spike in the chip selct 0 line between the set of the value and the selection of the chip select line. This commit changes the order of the register writes so that first the chip select line is chosen and then the value is set, removing the spike. Signed-off-by: Randolph Maaßen <[email protected]> Reviewed-by: Sowjanya Komatineni <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-21spi: lpspi: fix dataloss when SS is inactivated between every wordsClark Wang1-2/+2
If we don't use CONT to keep SS activated or use DMA mode without cs-gpio, SS will be inactivated between every words. The word here means the data sent once which length can be set as 1/2/4 bytes. In the isr function, we read the FSR_RXCOUNT just behind the fsl_lpspi_read_rx_fifo. This causes the value of FSR_RXCOUNT cannot reflect whether there is still data not sent timely. So do this judgement by FSR_TXCOUNT. Signed-off-by: Clark Wang <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-18spi : spi-topcliff-pch: Fix to handle empty DMA buffersAditya Pakki1-2/+13
pch_alloc_dma_buf allocated tx, rx DMA buffers which can fail. Further, these buffers are used without a check. The patch checks for these failures and sends the error upstream. Signed-off-by: Aditya Pakki <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-15spi: spi-mem: stm32-qspi: avoid memory corruption at low frequencyLudovic Barre1-3/+1
This patch solves a memory corruption seen at 8 MHz. To avoid such issue, timeout counter is disabled. Signed-off-by: Ludovic Barre <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-15spi: rspi: Fix sequencer reset during initializationGeert Uytterhoeven1-3/+6
While the sequencer is reset after each SPI message since commit 880c6d114fd79a69 ("spi: rspi: Add support for Quad and Dual SPI Transfers on QSPI"), it was never reset for the first message, thus relying on reset state or bootloader settings. Fix this by initializing it explicitly during configuration. Fixes: 0b2182ddac4b8837 ("spi: add support for Renesas RSPI") Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-15spi: rspi: Fix register initialization while runtime-suspendedGeert Uytterhoeven1-23/+16
The Renesas RSPI/QSPI driver performs SPI controller register initialization in its spi_operations.setup() callback, without calling pm_runtime_get_sync() first, which may cause spurious failures. So far this went unnoticed, as this SPI controller is typically used with a single SPI NOR FLASH containing the boot loader: 1. If the device's module clock is still enabled (left enabled by the bootloader, and not yet disabled by the clk_disable_unused() late initcall), register initialization succeeds, 2. If the device's module clock is disabled, register writes don't seem to cause lock-ups or crashes. Data received in the first SPI message may be corrupted, though. Subsequent SPI messages seem to be OK. E.g. on r8a7791/koelsch, one bit is lost while receiving the 6th byte of the JEDEC ID for the s25fl512s FLASH, corrupting that byte and all later bytes. But until commit a2126b0a010905e5 ("mtd: spi-nor: refine Spansion S25FL512S ID"), the 6th byte was not considered for FLASH identification. Fix this by moving all initialization from the .setup() to the .prepare_message() callback. The latter is always called after the device has been runtime-resumed by the SPI core. This also makes the driver follow the rule that .setup() must not change global driver state or register values, as that might break a transfer in progress. Fixes: 490c97747d5dc77d ("spi: rspi: Add runtime PM support, using spi core auto_runtime_pm") Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-13spi: imx: stop buffer overflow in RX FIFO flushTrent Piepho1-1/+1
Commit 71abd29057cb ("spi: imx: Add support for SPI Slave mode") added an RX FIFO flush before start of a transfer. In slave mode, the master may have sent more data than expected and this data will still be in the RX FIFO at the start of the next transfer, and so needs to be flushed. However, the code to do the flush was accidentally saving this data into the previous transfer's RX buffer, clobbering the contents of whatever followed that buffer. Change it to empty the FIFO and throw away the data. Every one of the RX functions for the different eCSPI versions and modes reads the RX FIFO data using the same readl() call, so just use that, rather than using the spi_imx->rx function pointer and making sure all the different rx functions have a working "throw away" mode. There is another issue, which affects master mode when switching from DMA to PIO. There can be extra data in the RX FIFO which triggers this flush code, causing memory corruption in the same manner. I don't know why this data is unexpectedly in the FIFO. It's likely there is a different bug or erratum responsible for that. But regardless of that, I think this is proper fix the for bug at hand here. Fixes: 71abd29057cb ("spi: imx: Add support for SPI Slave mode") Cc: Jiada Wang <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Stefan Agner <[email protected]> Cc: Shawn Guo <[email protected]> Signed-off-by: Trent Piepho <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-11spi: Fix zero length xfer bugChris Lesiak1-0/+2
This fixes a bug for messages containing both zero length and unidirectional xfers. The function spi_map_msg will allocate dummy tx and/or rx buffers for use with unidirectional transfers when the hardware can only do a bidirectional transfer. That dummy buffer will be used in place of a NULL buffer even when the xfer length is 0. Then in the function __spi_map_msg, if he hardware can dma, the zero length xfer will have spi_map_buf called on the dummy buffer. Eventually, __sg_alloc_table is called and returns -EINVAL because nents == 0. This fix prevents the error by not using the dummy buffer when the xfer length is zero. Signed-off-by: Chris Lesiak <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-03-04spi: sh-msiof: Restrict bits per word to 8/16/24/32 on R-Car Gen2/3Geert Uytterhoeven1-1/+7
While the MSIOF variants in older SuperH and SH/R-Mobile SoCs support bits-per-word values in the full range 8..32, the variants present in R-Car Gen2 and Gen3 SoCs are restricted to 8, 16, 24, or 32. Obtain the value from family-specific sh_msiof_chipdata to fix this. Reported-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-22spi: sifive: Remove redundant dev_err call in sifive_spi_probe()Wei Yongjun1-1/+0
There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Wei Yongjun <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-22spi: sifive: Remove spi_master_put in sifive_spi_remove()Wei Yongjun1-1/+0
The call to spi_master_put() in sifive_spi_remove() is redundant since the master is registered using devm_spi_register_master() and no reference hold by using spi_master_get() in sifive_spi_remove(). This is detected by Coccinelle semantic patch. Fixes: 484a9a68d669 ("spi: sifive: Add driver for the SiFive SPI controller") Signed-off-by: Wei Yongjun <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-20Merge branch 'for-5.0' of ↵Mark Brown10-74/+89
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-5.1
2019-02-20spi: pxa2xx: Setup maximum supported DMA transfer lengthAndy Shevchenko1-0/+1
When the commit b6ced294fb61 ("spi: pxa2xx: Switch to SPI core DMA mapping functionality") switches to SPI core provided DMA helpers, it missed to setup maximum supported DMA transfer length for the controller and thus users mistakenly try to send more data than supported with the following warning: ili9341 spi-PRP0001:01: DMA disabled for transfer length 153600 greater than 65536 Setup maximum supported DMA transfer length in order to make users know the limit. Fixes: b6ced294fb61 ("spi: pxa2xx: Switch to SPI core DMA mapping functionality") Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Mark Brown <[email protected]> Cc: [email protected]
2019-02-19spi: sifive: Add driver for the SiFive SPI controllerYash Shah3-0/+457
Add driver for the SiFive SPI controller on the HiFive Unleashed board. Signed-off-by: Palmer Dabbelt <[email protected]> Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Yash Shah <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-19spi: sifive: Add DT documentation for SiFive SPI controllerYash Shah1-0/+37
DT documentation for SPI controller added. Signed-off-by: Palmer Dabbelt <[email protected]> Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Yash Shah <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-13spi: sprd: Add a prefix for SPI DMA channel macrosBaolin Wang1-21/+21
Add a prefix for SPI DMA channel macros to avoid namespace conflicts, and no functional changes. Signed-off-by: Baolin Wang <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-13spi: sprd: spi: sprd: Add DMA mode supportLanqing Liu1-3/+290
Add DMA mode support for the Spreadtrum SPI controller, and we will enable SPI interrupt to help to complete the SPI transfer work in DMA mode. Signed-off-by: Lanqing Liu <[email protected]> Signed-off-by: Baolin Wang <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-13dt-bindings: spi: Add the DMA properties for the SPI dma modeLanqing Liu1-0/+7
Add the DMA properties for the SPI dma mode. Signed-off-by: Lanqing Liu <[email protected]> Signed-off-by: Baolin Wang <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-13spi: sprd: Add the SPI irq function for the SPI DMA modeLanqing Liu1-0/+51
The SPI irq event will use to complete the SPI work in the SPI DMA mode, so this patch is a preparation for the following DMA mode support. Moreover the SPI interrupt can be fired when removing the SPI controller, so we should make sure the SPI controller has stopped the queue in remove function before freeing the SPI irq. Signed-off-by: Lanqing Liu <[email protected]> Signed-off-by: Baolin Wang <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-12dt-bindings: spi: imx: Add an entry for the i.MX8QM compatibleFabio Estevam1-0/+1
Add an entry for the "fsl,imx8mq-ecspi" compatible to describe the ECSPI version present on i.MX8M. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-12spi: use gpio[d]_set_value_cansleep for setting chipselect GPIOFelix Fietkau1-2/+3
Sleeping is safe inside spi_transfer_one_message, and some GPIO chips are running on slow busses (such as I2C GPIO expanders) and need to sleep for setting values. Signed-off-by: Felix Fietkau <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-12spi: gpio: Advertise support for SPI_CS_HIGHJonathan Neuschäfer1-1/+2
The spi-gpio driver already handles different chip select polarities, but so far this was not advertised in master->mode_bits. This patch fixes mmc_spi on top of spi_gpio, which is useful in some testing scenarios. Signed-off-by: Jonathan Neuschäfer <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-08spi: sh-msiof: Replace spi_master by spi_controllerGeert Uytterhoeven1-85/+83
As of commit 8caab75fd2c2a926 ('spi: Generalize SPI "master" to "controller"'), the old master-centric names are compatibility wrappers for the new controller-centric names. Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-08spi: sh-hspi: Replace spi_master by spi_controllerGeert Uytterhoeven1-18/+18
As of commit 8caab75fd2c2a926 ('spi: Generalize SPI "master" to "controller"'), the old master-centric names are compatibility wrappers for the new controller-centric names. Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-08spi: rspi: Replace spi_master by spi_controllerGeert Uytterhoeven1-85/+85
As of commit 8caab75fd2c2a926 ('spi: Generalize SPI "master" to "controller"'), the old master-centric names are compatibility wrappers for the new controller-centric names. Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-06spi: atmel-quadspi: add support for sam9x60 qspi controllerTudor Ambarus1-35/+128
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register access, the other for the qspi core and phy. Both are mandatory. It uses different transfer type bits in IFR register. It has dedicated registers to specify a read or a write instruction: Read Instruction Code Register (RICR) and Write Instruction Code Register (WICR). ICR/RICR/WICR have identical fields. Tested with sst26vf064b jedec,spi-nor flash. Backward compatibility test done on sama5d2 qspi controller and mx25l25635e jedec,spi-nor flash. Signed-off-by: Tudor Ambarus <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-06dt-bindings: spi: atmel-quadspi: QuadSPI driver for Microchip SAM9X60Tudor Ambarus1-3/+7
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register access, the other for the qspi core and phy. Both are mandatory. Signed-off-by: Tudor Ambarus <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-06spi: atmel-quadspi: add support for named peripheral clockTudor Ambarus1-15/+18
Naming clocks is a good practice. Keep supporting unnamed peripheral clock, to be backward compatible with old DTs. While here, rename clk to pclk, to indicate that it is a peripheral clock. Suggested-by: Boris Brezillon <[email protected]> Signed-off-by: Tudor Ambarus <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-06dt-bindings: spi: atmel-quadspi: make "pclk" mandatoryTudor Ambarus1-0/+2
Naming clocks is a good practice. Make "pclk" madatory even if we support unnamed clock in the driver, to be backward compatible with old DTs. Suggested-by: Boris Brezillon <[email protected]> Signed-off-by: Tudor Ambarus <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-06dt-bindings: spi: atmel-quadspi: update example to new clock bindingTudor Ambarus1-1/+1
Introduced in: commit b60557876849 ("ARM: dts: at91: sama5d2: switch to new clock binding") Signed-off-by: Tudor Ambarus <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-06spi: atmel-quadspi: rework transfer macrosTudor Ambarus1-9/+4
Split the TFRTYP_TRSFR_ bitfields in 2: one bit encoding the mem/reg transfer type and one bit encoding the direction of the transfer (read/write). Remove NOP when setting read transfer type. Remove useless setting of write transfer type when op->data.dir == SPI_MEM_DATA_IN && !op->data.nbytes. QSPI_IFR_TFRTYP_TRSFR_WRITE is specific just to sama5d2 qspi, rename it to QSPI_IFR_SAMA5D2_WRITE_TRSFR. Signed-off-by: Tudor Ambarus <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-06spi: atmel-quadspi: switch to SPDX license identifiersTudor Ambarus1-12/+1
Adopt the SPDX license identifiers to ease license compliance management. Signed-off-by: Tudor Ambarus <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-06spi: atmel-quadspi: return appropriate error codeTudor Ambarus1-2/+2
Return -ENOTSUPP when atmel_qspi_find_mode() fails. Propagate the error in atmel_qspi_exec_op(). Signed-off-by: Tudor Ambarus <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-06spi: atmel-quadspi: remove unnecessary castTudor Ambarus1-1/+1
The cast is done implicitly. Signed-off-by: Tudor Ambarus <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-06spi: atmel-quadspi: fix naming schemeTudor Ambarus1-8/+8
Let general names to core drivers. Signed-off-by: Tudor Ambarus <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-06spi: atmel-quadspi: drop wrappers for iomem accessesTudor Ambarus1-28/+17
The wrappers hid that the accesses are relaxed. Drop them. Suggested-by: Boris Brezillon <[email protected]> Signed-off-by: Tudor Ambarus <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-06spi: atmel-quadspi: order header files inclusion alphabeticallyTudor Ambarus1-5/+4
Cosmetic change, no functional change. Signed-off-by: Tudor Ambarus <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-06spi: atmel-quadspi: cache MR value to avoid a write accessTudor Ambarus1-1/+13
Set the controller by default in Serial Memory Mode (SMM) at probe. Cache Mode Register (MR) value to avoid write access when setting the controller in serial memory mode at exec_op(). Signed-off-by: Tudor Ambarus <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2019-02-06spi: spi-fsl-dspi: Provide support for DSPI slave mode operation (Vybryd vf610)Lukasz Majewski1-10/+30
The NXP's Vybryd vf610 can work as a SPI slave device (the CS and clock signals are provided by master). It is possible to specify a single device to work in that mode. As we do use DMA for transferring data, the RX channel must be prepared for incoming data. Moreover, in slave mode we just set a subset of control fields in configuration registers (CTAR0, PUSHR). For testing the spidev_test program has been used. Test script for this patch can be found here: https://github.com/lmajewski/tests-spi/blob/master/tests/spi/spi_tests.sh Signed-off-by: Lukasz Majewski <[email protected]> Signed-off-by: Mark Brown <[email protected]>
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