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This function simply returns the number of VPEs present in the current
core, or 1 if the core does not implement the MT ASE. In SMP kernels
this will typically equal smp_num_siblings, however it will also be
usable in UP kernels and helps prepare for the possibility of a
heterogenous system where the VPE count is not the same across all
cores.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/6665/
Signed-off-by: Ralf Baechle <[email protected]>
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Both the CONFIG_MIPS_CPS & CONFIG_MIPS_CMP SMP implementations call
mips_mt_set_cpuoptions when preparing to start secondary CPUs. However
both may be used without MT. Provide an empty inline function to prevent
a link error in this case.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/6647/
Signed-off-by: Ralf Baechle <[email protected]>
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Use del_timer_sync to ensure that the timer is stopped on all CPUs before
the driver exists.
This change was suggested by Thomas Gleixner
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@r@
declarer name module_exit;
identifier ex;
@@
module_exit(ex);
@@
identifier r.ex;
@@
ex(...) {
<...
- del_timer
+ del_timer_sync
(...)
...>
}
// </smpl>
Signed-off-by: Julia Lawall <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/6663/
Signed-off-by: Ralf Baechle <[email protected]>
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This patch ensures that the kernel sets a sane base address for the
PIIX4 PM I/O register region during boot. Without this the kernel may
not successfully claim the region as a resource if the bootloader didn't
configure the region. With this patch the kernel will always succeed
with:
pci 0000:00:0a.3: quirk: [io 0x1000-0x103f] claimed by PIIX4 ACPI
The lack of the resource claiming is easily reproducible without this
patch using current versions of QEMU.
Signed-off-by: Paul Burton <[email protected]>
Tested-by: James Hogan <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/6641/
Signed-off-by: Ralf Baechle <[email protected]>
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Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Hongliang Tao <[email protected]>
Signed-off-by: Hua Yan <[email protected]>
Tested-by: Alex Smith <[email protected]>
Reviewed-by: Alex Smith <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: Aurelien Jarno <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6640
Signed-off-by: Ralf Baechle <[email protected]>
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Tips of Loongson's CPU hotplug:
1, To fully shutdown a core in Loongson 3, the target core should go to
CKSEG1 and flush all L1 cache entries at first. Then, another core
(usually Core 0) can safely disable the clock of the target core. So
play_dead() call loongson3_play_dead() via CKSEG1 (both uncached and
unmmaped).
2, The default clocksource of Loongson is MIPS. Since clock source is a
global device, timekeeping need the CP0' Count registers of each core
be synchronous. Thus, when a core is up, we use a SMP_ASK_C0COUNT IPI
to ask Core-0's Count.
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Hongliang Tao <[email protected]>
Signed-off-by: Hua Yan <[email protected]>
Tested-by: Alex Smith <[email protected]>
Reviewed-by: Alex Smith <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: Aurelien Jarno <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6639
Signed-off-by: Ralf Baechle <[email protected]>
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IPI registers of Loongson-3 include IPI_SET, IPI_CLEAR, IPI_STATUS,
IPI_EN and IPI_MAILBOX_BUF. Each bit of IPI_STATUS indicate a type of
IPI and IPI_EN indicate whether the IPI is enabled. The sender write 1
to IPI_SET bits generate IPIs in IPI_STATUS, and receiver write 1 to
bits of IPI_CLEAR to clear IPIs. IPI_MAILBOX_BUF are used to deliver
more information about IPIs.
Why we change code in arch/mips/loongson/common/setup.c?
If without this change, when SMP configured, system cannot boot since
it hang at printk() in cgroup_init_early(). The root cause is:
console_trylock()
\-->down_trylock(&console_sem)
\-->raw_spin_unlock_irqrestore(&sem->lock, flags)
\-->_raw_spin_unlock_irqrestore()(SMP/UP have different versions)
\-->__raw_spin_unlock_irqrestore() (following is the SMP case)
\-->do_raw_spin_unlock()
\-->arch_spin_unlock()
\-->nudge_writes()
\-->mb()
\-->wbflush()
\-->__wbflush()
In previous code __wbflush() is initialized in plat_mem_setup(), but
cgroup_init_early() is called before plat_mem_setup(). Therefore, In
this patch we make changes to avoid boot failure.
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Hongliang Tao <[email protected]>
Signed-off-by: Hua Yan <[email protected]>
Tested-by: Alex Smith <[email protected]>
Reviewed-by: Alex Smith <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: Aurelien Jarno <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6638
Signed-off-by: Ralf Baechle <[email protected]>
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Added Kconfig options include: Loongson-3 CPU and machine definition,
CPU cache features, UEFI-like firmware interface (LEFI), HT-linked PCI,
and swiotlb support.
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Hongliang Tao <[email protected]>
Signed-off-by: Hua Yan <[email protected]>
Tested-by: Alex Smith <[email protected]>
Reviewed-by: Alex Smith <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: Aurelien Jarno <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6637
Signed-off-by: Ralf Baechle <[email protected]>
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Loongson doesn't support DMA address above 4GB traditionally. If memory
is more than 4GB, CONFIG_SWIOTLB and ZONE_DMA32 should be selected. In
this way, DMA pages are allocated below 4GB preferably. However, if low
memory is not enough, high pages are allocated and swiotlb is used for
bouncing.
Moreover, we provide a platform-specific dma_map_ops::set_dma_mask() to
set a device's dma_mask and coherent_dma_mask. We use these masks to
distinguishes an allocated page can be used for DMA directly, or need
swiotlb to bounce.
Recently, we found that 32-bit DMA isn't a hardware bug, but a hardware
configuration issue. So, latest firmware has enable the DMA support as
high as 40-bit. To support all-memory DMA for all devices (besides the
Loongson platform limit, there are still some devices have their own
DMA32 limit), and also to be compatible with old firmware, we keep use
swiotlb.
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Hongliang Tao <[email protected]>
Signed-off-by: Hua Yan <[email protected]>
Tested-by: Alex Smith <[email protected]>
Reviewed-by: Alex Smith <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: Aurelien Jarno <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6636
Signed-off-by: Ralf Baechle <[email protected]>
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Loongson family machines has three types of serial port: PCI UART, LPC
UART and CPU internal UART. Loongson-2E and parts of Loongson-2F based
machines use PCI UART; most Loongson-2F based machines use LPC UART;
Loongson-2G/3A has both LPC and CPU UART but usually use CPU UART.
Port address of UARTs:
CPU UART: REG_BASE + OFFSET;
LPC UART: LIO1_BASE + OFFSET;
PCI UART: PCIIO_BASE + OFFSET.
Since LPC UART are linked in "Local Bus", both CPU UART and LPC UART
are called "CPU provided serial port".
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Hongliang Tao <[email protected]>
Signed-off-by: Hua Yan <[email protected]>
Tested-by: Alex Smith <[email protected]>
Reviewed-by: Alex Smith <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: Aurelien Jarno <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6635
Signed-off-by: Ralf Baechle <[email protected]>
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IRQ routing path of Loongson-3:
Devices(most) --> I8259 --> HT Controller --> IRQ Routing Table --> CPU
^
|
Device(legacy devices such as UART) --> Bonito ---|
IRQ Routing Table route 32 INTs to CPU's INT0~INT3(IP2~IP5 of CP0), 32
INTs include 16 HT INTs(mostly), 4 PCI INTs, 1 LPC INT, etc. IP6 is used
for IPI and IP7 is used for internal MIPS timer. LOONGSON_INT_ROUTER_*
are IRQ Routing Table registers.
I8259 IRQs are 1:1 mapped to HT1 INTs. LOONGSON_HT1_* are configuration
registers of HT1 controller.
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Hongliang Tao <[email protected]>
Signed-off-by: Hua Yan <[email protected]>
Tested-by: Alex Smith <[email protected]>
Reviewed-by: Alex Smith <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: Aurelien Jarno <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6634
Signed-off-by: Ralf Baechle <[email protected]>
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Loongson family machines use Hyper-Transport bus for inter-core
connection and device connection. The PCI bus is a subordinate
linked at HT1.
With LEFI firmware interface, We don't need fixup for PCI irq routing
(except providing a VBIOS of the integrated GPU).
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Hongliang Tao <[email protected]>
Signed-off-by: Hua Yan <[email protected]>
Tested-by: Alex Smith <[email protected]>
Reviewed-by: Alex Smith <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: Aurelien Jarno <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6633
Signed-off-by: Ralf Baechle <[email protected]>
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The new UEFI-like firmware interface (LEFI, i.e. Loongson Unified
Firmware Interface) has 3 advantages:
1, Firmware export a physical memory map which is similar to X86's
E820 map, so prom_init_memory() will be more elegant that #ifdef
clauses can be removed.
2, Firmware export a pci irq routing table, we no longer need pci
irq routing fixup in kernel's code.
3, Firmware has a built-in vga bios, and its address is exported,
the linux kernel no longer need an embedded blob.
With the LEFI interface, Loongson-3A/2G and all their successors can use
a unified kernel. All Loongson-based machines support this new interface
except 2E/2F series.
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Hongliang Tao <[email protected]>
Signed-off-by: Hua Yan <[email protected]>
Tested-by: Alex Smith <[email protected]>
Reviewed-by: Alex Smith <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: Aurelien Jarno <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6632
Signed-off-by: Ralf Baechle <[email protected]>
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Add four Loongson-3 based machine types:
MACH_LEMOTE_A1004/MACH_LEMOTE_A1201 are laptops;
MACH_LEMOTE_A1101 is mini-itx;
MACH_LEMOTE_A1205 is all-in-one machine.
The most significant differrent between A1004/A1201 and A1101/A1205 is
the laptops have EC but others don't.
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Hongliang Tao <[email protected]>
Signed-off-by: Hua Yan <[email protected]>
Tested-by: Alex Smith <[email protected]>
Reviewed-by: Alex Smith <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: Aurelien Jarno <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6631
Signed-off-by: Ralf Baechle <[email protected]>
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Basic Loongson-3 CPU support include CPU probing and TLB/cache
initializing.
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Hongliang Tao <[email protected]>
Signed-off-by: Hua Yan <[email protected]>
Tested-by: Alex Smith <[email protected]>
Reviewed-by: Alex Smith <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: Aurelien Jarno <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6630
Signed-off-by: Ralf Baechle <[email protected]>
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Loongson-3 is a multi-core MIPS family CPU, it support MIPS64R2 fully.
Loongson-3 has the same IMP field (0x6300) as Loongson-2.
Loongson-3 has a hardware-maintained cache, system software doesn't
need to maintain coherency.
Loongson-3A is the first revision of Loongson-3, and it is the quad-
core version of Loongson-2G. Loongson-3A has a simplified version named
Loongson-2Gq, the main difference between Loongson-3A/2Gq is 3A has two
HyperTransport controller but 2Gq has only one. HT0 is used for cross-
chip interconnection and HT1 is used to link PCI bus. Therefore, 2Gq
cannot support NUMA but 3A can. For software, Loongson-2Gq is simply
identified as Loongson-3A.
Exsisting Loongson family CPUs:
Loongson-1: Loongson-1A, Loongson-1B, they are 32-bit MIPS CPUs.
Loongson-2: Loongson-2E, Loongson-2F, Loongson-2G, they are 64-bit
single-core MIPS CPUs.
Loongson-3: Loongson-3A(including so-called Loongson-2Gq), they are
64-bit multi-core MIPS CPUs.
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Hongliang Tao <[email protected]>
Signed-off-by: Hua Yan <[email protected]>
Tested-by: Alex Smith <[email protected]>
Reviewed-by: Alex Smith <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: Aurelien Jarno <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6629/
Signed-off-by: Ralf Baechle <[email protected]>
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And there are more CPUs or configurations that want to provide special
per-CPU information in /proc/cpuinfo. So I think there needs to be a
hook mechanism, such as a notifier.
This is a first cut only; I need to think about what sort of looking
the notifier needs to have. But I'd appreciate testing on MT hardware!
Signed-off-by: Ralf Baechle <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/6066/
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Signed-off-by: Rafał Miłecki <[email protected]>
Cc: [email protected]
Cc: Hauke Mehrtens <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6627/
Signed-off-by: Ralf Baechle <[email protected]>
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When an IRQ is started on a GPIO line, mark this GPIO as IRQ in
the gpiolib so we can keep track of the usage centrally.
Signed-off-by: Linus Walleij <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Alexandre Courbot <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6417/
Signed-off-by: Ralf Baechle <[email protected]>
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All architecturally defined bits in the FPU implementation register
are read only & unchanging. It contains some implementation-defined
bits but the architecture manual states "This bits are explicitly not
intended to be used for mode control functions" which seems to provide
justification for viewing the register as a whole as unchanging. This
being the case we can simply re-use the value we read at boot rather
than having to re-read it later, and avoid the complexity which that
read entails.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/6147/
Signed-off-by: Ralf Baechle <[email protected]>
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All architecturally defined bits in the FPU implementation register
are read only & unchanging. It contains some implementation-defined
bits but the architecture manual states "This bits are explicitly not
intended to be used for mode control functions" which seems to provide
justification for viewing the register as a whole as unchanging. This
being the case we can simply re-use the value we read at boot rather
than having to re-read it later, and avoid the complexity which that
read entails.
Signed-off-by: Paul Burton <[email protected]>
Reviewed-by: Qais Yousef <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/6144/
Signed-off-by: Ralf Baechle <[email protected]>
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If current_cpu_type() is pre-defined in cpu-feature-overrides.h, This
may save about 10k for the compressed kernel image(vmlinuz).
Signed-off-by: Wu Zhangjin <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/1901/
Signed-off-by: Ralf Baechle <[email protected]>
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This adds an ad-hoc error injection method. Octeon II doesn't have
hardware support for injection, so this simulates it.
Signed-off-by: Daniel Walker <[email protected]>
Cc: David Daney <[email protected]>
Cc: Doug Thompson <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/5873/
Signed-off-by: Ralf Baechle <[email protected]>
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If the opstate_init() isn't called the driver won't start properly.
I just added it in what appears to be an appropriate place.
Signed-off-by: Daniel Walker <[email protected]>
Cc: David Daney <[email protected]>
Cc: Doug Thompson <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/5872/
Signed-off-by: Ralf Baechle <[email protected]>
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The symbol is an orphan, get rid of it.
Signed-off-by: Richard Weinberger <[email protected]>
Cc: [email protected] (open list:MIPS)
Cc: [email protected] (open list)
Patchwork: https://patchwork.linux-mips.org/patch/6523/
Signed-off-by: Ralf Baechle <[email protected]>
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The sead3-mtd.o is built for obj-y -- and hence this code is always
present. It will never be modular, so using module_init as an alias
for __initcall can be somewhat misleading.
Fix this up now, so that we can relocate module_init from
init.h into module.h in the future. If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.
Note that direct use of __initcall is discouraged, vs. one
of the priority categorized subgroups. As __initcall gets
mapped onto device_initcall, our use of device_initcall
directly in this change means that the runtime impact is
zero -- it will remain at level 6 in initcall ordering.
We also fix a missing semicolon, which this change uncovers.
Signed-off-by: Paul Gortmaker <[email protected]>
Reported-by: kbuild test robot <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/6412/
Signed-off-by: Ralf Baechle <[email protected]>
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Don't depend on CONFIG_IDE to make this more robust.
Signed-off-by: Ralf Baechle <[email protected]>
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Loongson-1 is a 32-bit MIPS CPU and Loongson-2/3 are 64-bit MIPS CPUs,
and both Loongson-2/3 has the same PRID IMP filed (0x6300). As a
result, renaming PRID_IMP_LOONGSON1 and PRID_IMP_LOONGSON2 to
PRID_IMP_LOONGSON_32 and PRID_IMP_LOONGSON_64 will make more sense.
Signed-off-by: Huacai Chen <[email protected]>
Tested-by: Alex Smith <[email protected]>
Reviewed-by: Alex Smith <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: Aurelien Jarno <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6552/
Signed-off-by: Ralf Baechle <[email protected]>
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Commit c24a8a7a9988 ("MIPS: Netlogic: Add MSI support for XLP") added
"select ARCH_SUPPORTS_MSI". But the Kconfig symbol ARCH_SUPPORTS_MSI was
already removed in v3.12, so that select is a nop. Drop it.
Signed-off-by: Paul Bolle <[email protected]>
Cc: Jayachandran C <[email protected]>
Cc: John Crispin <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/6521/
Signed-off-by: Ralf Baechle <[email protected]>
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Choose event/cache maps and handle raw event mapping for interAptiv. Update
code comments.
Signed-off-by: Deng-Cheng Zhu <[email protected]>
Reviewed-by: Markos Chandras <[email protected]>
Reviewed-by: James Hogan <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/6528/
Signed-off-by: Ralf Baechle <[email protected]>
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Choose event/cache maps and handle raw event mapping for proAptiv. Update
code comments.
Signed-off-by: Deng-Cheng Zhu <[email protected]>
Reviewed-by: Markos Chandras <[email protected]>
Reviewed-by: James Hogan <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/6527/
Signed-off-by: Ralf Baechle <[email protected]>
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74K/proAptiv share the same event/cache maps. So it's better to change the
names of the existing mipsxx74Kcore_[event|cache]_map.
Signed-off-by: Deng-Cheng Zhu <[email protected]>
Reviewed-by: Markos Chandras <[email protected]>
Reviewed-by: James Hogan <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/6526/
Signed-off-by: Ralf Baechle <[email protected]>
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Signed-off-by: Geert Uytterhoeven <[email protected]>
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Anyone using a system based on an AMD Elan SC520 processor would be
building a dedicated kernel for it, so we can make the sc520_wdt
driver depend on MELAN. SC520_CPUFREQ already depends on MELAN so it
makes things more consistent. It also makes kernel configuration for
every other x86 user easier.
Signed-off-by: Jean Delvare <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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Using platform_driver_probe instead of platform_driver_register has
two benefits:
* The driver will fail to load if device probing fails.
* The probe function can be marked __init.
Signed-off-by: Jean Delvare <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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Using platform_driver_probe instead of platform_driver_register has
two benefits:
* The driver will fail to load if device probing fails.
* The probe function can be marked __init.
Signed-off-by: Jean Delvare <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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Using platform_driver_probe instead of platform_driver_register has
two benefits:
* The driver will fail to load if device probing fails.
* The probe function can be marked __init.
Signed-off-by: Jean Delvare <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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Using platform_driver_probe instead of platform_driver_register has
two benefits:
* The driver will fail to load if device probing fails.
* The probe function can be marked __init.
Signed-off-by: Jean Delvare <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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The watchdog's parent is iTCO_wdt (the platform device) not lpc_ich
(the PCI device.) Setting the parent right makes it much easier for
the user to figure out which driver/module is handling the watchdog
device node.
Signed-off-by: Jean Delvare <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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On some hardware platforms, the it87_wdt watchdog resets the machine
despite the watchdog daemon running and writing to /dev/watchdog.
This is due to Consumer IR buffer underrun interrupts being used as
triggers to reset the timer. On some buggy hardware implementations
such as the iEi AFL-12A-N270 single-board computer, this method does
not work.
However, resetting the timer by writing its original timeout value in
its configuration register over and over again suppresses the unwanted
reboots.
Add a module option (nocir), 0 by default in order not to break existing
setups. Setting it to 1 enables the workaround.
Fixes bug #42801 <https://bugzilla.kernel.org/show_bug.cgi?id=42801>.
Tested primarily on Linux 3.5.7, applies cleanly on Linux 3.13.5.
Signed-off-by: Marc van der Wal <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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Use more the applicable ARCH_BCM_MOBILE option instead of ARCH_BCM as
dependency for bcm_kona_wdt.c.
Signed-off-by: Markus Mayer <[email protected]>
Acked-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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clk_prepare_enable can fail. Check its return value.
Signed-off-by: Sachin Kamat <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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Initializing clk to NULL as a reset/error condition does not
help as NULL is not an invalid condition w.r.t clk. Remove this
initialization altogether as there is no state retention.
Signed-off-by: Sachin Kamat <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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The Allwinner A10 and A31 compatibles were following a slightly different
compatible patterns than the rest of the SoCs for historical reasons. Change
the compatibles to match the other pattern in the watchdog controller driver
for consistency.
Signed-off-by: Maxime Ripard <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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DT-enabled Dove will move over from ARCH_DOVE in mach-dove to MACH_DOVE in
mach-mvebu. As non-DT ARCH_DOVE will stay to rot for a while, add a new
DT-only MACH_DOVE Kconfig.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
Acked-by: Jason Cooper <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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Fix the following checkpatch warnings and error:
WARNING: quoted string split across lines
WARNING: braces {} are not necessary for single statement blocks
WARNING: __initdata should be placed after ibmasr_id_table[]
WARNING: please, no space before tabs
ERROR: do not initialise statics to 0 or NULL
Signed-off-by: Jingoo Han <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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Add a driver for the hardware watchdogs in NVIDIA Tegra SoCs (Tegra30 and
later). This driver will configure one watchdog timer that will reset the
system in the case of a watchdog timeout.
This driver binds to the nvidia,tegra30-timer device node and gets its
register base from there.
Signed-off-by: Andrew Chew <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Tested-by: Stephen Warren <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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Remove no_timeout variable and check variables
directly.
Suggested-by: Rob Herring <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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Enable this driver for Zynq.
Move it to architecture independent Kconfig part.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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Document current driver binding.
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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