aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2011-05-20Merge branch 'master' of ↵David S. Miller6-9/+32
master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
2011-05-16sparc32,leon: Remove unnecessary page_address calls in LEON DMA API.Kristoffer Glembo1-26/+16
The function mmu_inval_dma_area takes a virtual address as a parameter which is problematic in case the buffer is located in highmem and the mapping currently is unavailable. Since the function was only implemented for LEON this patch removes calls to it in non LEON code paths and renames it to dma_make_coherent which instead takes a physical address (which for now is unused since we flush the whole cache). This way it is possible to remove several unnecessary calls to page_address which will fail if the virtual mapping is unavailable. Signed-off-by: Kristoffer Glembo <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-05-16sparc: convert old cpumask API into new oneKOSAKI Motohiro16-105/+115
Adapt new API. Almost change is trivial, most important change are to remove following like =operator. cpumask_t cpu_mask = *mm_cpumask(mm); cpus_allowed = current->cpus_allowed; Because cpumask_var_t is =operator unsafe. These usage might prevent kernel core improvement. No functional change. Signed-off-by: KOSAKI Motohiro <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-05-16sparc32, sun4d: Implemented SMP IPIs support for SUN4D machinesDaniel Hellstrom3-0/+94
The sun4d does not seem to have a distingstion between soft and hard IRQs. When generating IPIs the generated IRQ looks like a hard IRQ, this patch adds a "IPI check" in the sun4d irq trap handler at a predefined IRQ number (SUN4D_IPI_IRQ). Before generating an IPI a per-cpu memory structure is modified for the "IPI check" to successfully detect a IPI request to a specific processor, the check clears the IPI work requested. All three IPIs (resched, single and cpu-mask) use the same IRQ number. The IPI IRQ should preferrably be on a separate IRQ and definitly not shared with IRQ handlers requesting IRQ with IRQF_SHARED. Signed-off-by: Daniel Hellstrom <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-05-16sparc32, sun4m: Implemented SMP IPIs support for SUN4M machinesDaniel Hellstrom3-9/+54
Implement the three IPIs (resched, single and cpu-mask) generation and interrupt handler catch. The sun4m has 15 soft-IRQs and three of them is used with this patch, the three IPIs was previously implemented with the cross-call IRQ15 which does not work with locking routines such as spinlocks because IRQ15 is NMI, it may cause deadlock. The IRQ trap handler code assumes (in the same spritit as the old it seems) that hard interrupts will be generated until handled (level), when a IRQ happens the IRQ pending register is checked for pending soft-IRQs. When both hard and soft IRQ happens at the same time only soft-IRQs are handled. The old code implemented a soft-IRQ traphandler at IRQ14 which called smp_reschedule_irq which in turn called set_need_resched. It seems to be an old relic and is replaced with the interrupt traphander exit code RESTORE_ALL, it calls schedule() when appropriate. Signed-off-by: Daniel Hellstrom <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-05-16sparc32,leon: Implemented SMP IPIs for LEON CPUDaniel Hellstrom3-3/+126
This patch implements SMP IPIs on LEON using software generated IRQs to signal between CPUs. The IPI IRQ number is set by using the ipi_num property in the device tree, or defaults to 13. LEON SMP systems should reserve IRQ 13 (and IRQ 15) to Linux in order for the defaults to work. Signed-off-by: Daniel Hellstrom <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-05-16sparc32: implement SMP IPIs using the generic functionsDaniel Hellstrom5-16/+71
The current sparc32 SMP IPI generation is implemented the cross call function. The cross call function uses IRQ15 the NMI, this is has the effect that IPIs will interrupt IRQ critical areas and hang the system. Typically on/after spin_lock_irqsave calls can be aborted. The cross call functionality must still exist to flush cache/TLBS. This patch provides CPU models a custom way to implement generation of IPIs on the generic code's request. The typical approach is to generate an IRQ for each IPI case. After this patch each sparc32 SMP CPU model needs to implement IPIs in order to function properly. Signed-off-by: Daniel Hellstrom <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-05-16sparc32,leon: SMP power down implementationDaniel Hellstrom1-2/+10
Signed-off-by: Daniel Hellstrom <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-05-16sparc32,leon: added some SMP commentsDaniel Hellstrom2-0/+14
Signed-off-by: Daniel Hellstrom <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-05-12sparc: add {read,write}*_be routinesJan Andersson1-0/+13
This patch adds {read,write}*_be big endian memory access routines to the io.h header used on SPARC32 and SPARC64. Tested on SPARC32 (LEON) Signed-off-by: Jan Andersson <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-05-11sparc32: Fixed unaligned memory copying in function ↵Tkhai Kirill1-3/+9
__csum_partial_copy_sparc_generic When we are in the label cc_dword_align, registers %o0 and %o1 have the same last 2 bits, but it's not guaranteed one of them is zero. So we can get unaligned memory access in label ccte. Example of parameters which lead to this: %o0=0x7ff183e9, %o1=0x8e709e7d, %g1=3 With the parameters I had a memory corruption, when the additional 5 bytes were rewritten. This patch corrects the error. One comment to the patch. We don't care about the third bit in %o1, because cc_end_cruft stores word or less. Signed-off-by: Tkhai Kirill <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-21sparc32,leon: don't rely on bootloader to mask IRQsDaniel Hellstrom2-0/+7
Signed-off-by: Daniel Hellstrom <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-21sparc32,leon: operate on boot-cpu IRQ controller registersDaniel Hellstrom3-25/+21
* proper initialization of boot_cpu_id (no hardcoding to 0) * use boot_cpu_id index to address into the IRQ controller where appropriate Each CPU has a separate set of IRQ controller registers, this patch makes sure that the boot-cpu registers are used instead of CPU0's. Signed-off-by: Daniel Hellstrom <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-21sparc32: always define boot_cpu_idDaniel Hellstrom5-14/+35
Define boot_cpu_id in single-processor kernels as well. This is to support architectures which can boot on other than CPU0. Sam Ravnborg has written the cleanup parts by extracting boot_cpu_id from smp_32.c into setup_32.c and cleaned up sun4d_irq.c. boot_cpu_id was initialized before BSS was cleared in sun4c_continue_boot, instead boot_cpu_id is set to 0xff to avoid BSS. If boot_cpu_id is untouched (0xff) by bootup code it will be overwritten to 0. boot_cpu_id4 is automatically calculated in common code. Signed-off-by: Daniel Hellstrom <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-21sparc32: removed unused code, implemented by generic codeDaniel Hellstrom2-205/+0
Signed-off-by: Daniel Hellstrom <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-21sparc32: fix sparcstation 5 bootSam Ravnborg1-3/+7
The sparcstation 5 I have available has no MID property for the CPU. This resulted in a panic when booting a SMP kernel on this box. The assigned field in cpu_data is never used, so if we fail to read the MID property then inform user and continue booting. Signed-off-by: Sam Ravnborg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-21sparc32: avoid build warning at mm/percpu.c:1647Sam Ravnborg1-2/+4
Fix following warning: mm/percpu.c: In function 'pcpu_embed_first_chunk': mm/percpu.c:1647:3: warning: format '%lx' expects type 'long unsigned int', but argument 3 has type 'unsigned int' Signed-off-by: Daniel Hellstrom <[email protected]> [sam: added warning message to changelog, use _AC()] Signed-off-by: Sam Ravnborg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-21sparc32: always register a PROM based early consoleSam Ravnborg3-8/+9
Do not require user to add "-p" to boot arguments to see early info printed to prom console. This is similar to the sparc64 functionality - which was added with: 3c62a2d3477ff7725210db57aec3d2806fa10c20 ("[SPARC64]: Always register a PROM based early console.") Signed-off-by: Sam Ravnborg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-21sparc32: probe for cpu info only during startupSam Ravnborg6-13/+8
We did a cpu_probe() call each time a CPU got online - which only effect was to save latest CPU/FPU info for use by show_cpuinfo(). Use same setup as for sparc64 where we probe for this info during startup, and only once. This allowed us to annotate a few functions __init which again fixed the following section mismatch warnings: WARNING: vmlinux.o(.text+0x65f0): Section mismatch in reference from the function set_cpu_and_fpu() to the (unknown reference) .init.rodata:(unknown) WARNING: vmlinux.o(.text+0x65f8): Section mismatch in reference from the function set_cpu_and_fpu() to the (unknown reference) .init.rodata:(unknown) WARNING: vmlinux.o(.text+0x664c): Section mismatch in reference from the function set_cpu_and_fpu() to the variable .init.rodata:manufacturer_info WARNING: vmlinux.o(.text+0x6650): Section mismatch in reference from the function set_cpu_and_fpu() to the variable .init.rodata:manufacturer_info Signed-off-by: Sam Ravnborg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-21sparc: consolidate show_cpuinfo in cpu.cSam Ravnborg8-157/+133
We have all the cpu related info in cpu.c - so move the remaining functions to support /proc/cpuinfo to this file. Signed-off-by: Sam Ravnborg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-21sparc32: fix section mismatch warnings in apc, pmc and time_32Sam Ravnborg3-3/+3
In all cases there were a struct of_device_id variable defined __initdata. But it was referenced from struct platform_driver.of_match_table which is not guaranteed to be used during init only. So drop the __initdata annotation. This fixes following warnings: WARNING: arch/sparc/kernel/built-in.o(.data+0x810): Section mismatch in reference from the variable clock_driver to the variable .init.data:clock_match The variable clock_driver references the variable __initdata clock_match If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: arch/sparc/kernel/built-in.o(.data+0xcec): Section mismatch in reference from the variable apc_driver to the variable .init.data:apc_match The variable apc_driver references the variable __initdata apc_match If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: arch/sparc/kernel/built-in.o(.data+0xd60): Section mismatch in reference from the variable pmc_driver to the variable .init.data:pmc_match The variable pmc_driver references the variable __initdata pmc_match If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Signed-off-by: Sam Ravnborg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-21sparc32,leon: implement genirq CPU affinityDaniel Hellstrom1-10/+54
A simple implementation of CPU affinity, the first CPU in the affinity CPU mask always takes the IRQ. Signed-off-by: Daniel Hellstrom <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-21sparc32, leon: code cleanup of timer/IRQ controller initializationDaniel Hellstrom1-84/+72
Cleaned up leon_init_timers() by removing unnecessary double checking and one indentation level. Changed LEON_IMASK to LEON_IMASK(cpu). Signed-off-by: Daniel Hellstrom <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-21sparc32,leon: cleaned away code from the LEON2 daysDaniel Hellstrom2-24/+1
Signed-off-by: Daniel Hellstrom <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-21sparc32,leon: per-cpu ticker use genirq per-cpu handlerDaniel Hellstrom4-51/+22
Signed-off-by: Daniel Hellstrom <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-21sparc32,leon: add support for extended interrupt controllerDaniel Hellstrom2-28/+74
The extended IRQ controller gives the LEON 16 more IRQs. The patch installs a custom handler for the exetended controller IRQ, where a register is read and the "real" IRQ causing IRQ is determined. Signed-off-by: Daniel Hellstrom <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-21sparc32, leon: must protect IRQ controller register with spinlockDaniel Hellstrom1-7/+7
The LEON interrupt controller has one single mask register for all IRQs per CPU, even though the genirq layer protects us from accessing the same IRQ at the same time other IRQs share the same mask register and may thus interfere. Some other IRQ controllers has a mask register or similar per IRQ instead which makes spinlocks unncessary. Signed-off-by: Daniel Hellstrom <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-19sparc32: genirq supportSam Ravnborg14-935/+636
The conversion of sparc32 to genirq is based on original work done by David S. Miller. Daniel Hellstrom has helped in the conversion and implemented the shutdowm functionality. Marcel van Nies <[email protected]> has tested this on Sparc Station 20 Test status: sun4c - not tested sun4m,pci - not tested sun4m,sbus - tested (Sparc Classic, Sparc Station 5, Sparc Station 20) sun4d - not tested leon - tested on various combinations of leon boards, including SMP variants generic Introduce use of GENERIC_HARDIRQS and GENERIC_IRQ_SHOW Allocate 64 IRQs - which is enough even for SS2000 Use a table of irq_bucket to maintain uses IRQs irq_bucket is also used to chain several irq's that must be called when the same intrrupt is asserted Use irq_link to link a interrupt source to the irq All plafforms must now supply their own build_device_irq method handler_irq rewriten to use generic irq support floppy Read FLOPPY_IRQ from platform device Use generic request_irq to register the floppy interrupt Rewrote sparc_floppy_irq to use the generic irq support pcic: Introduce irq_chip Store mask in chip_data for use in mask/unmask functions Add build_device_irq for pcic Use pcic_build_device_irq in pci_time_init allocate virtual irqs in pcic_fill_irq sun4c: Introduce irq_chip Store mask in chip_data for use in mask/unmask functions Add build_device_irq for sun4c Use sun4c_build_device_irq in sun4c_init_timers sun4m: Introduce irq_chip Introduce dedicated mask/unmask methods Introduce sun4m_handler_data that allow easy access to necessary data in the mask/unmask functions Add a helper method to enable profile_timer (used from smp) Added sun4m_build_device_irq Use sun4m_build_device_irq in sun4m_init_timers TODO: There is no replacement for smp_rotate that always scheduled next CPU as interrupt target upon an interrupt sun4d: Introduce irq_chip Introduce dedicated mask/unmask methods Introduce sun4d_handler_data that allow easy access to necessary data in mask/unmask fuctions Rewrote sun4d_handler_irq to use generic irq support TODO: The original implmentation of enable/disable had: if (irq < NR_IRQS) return; The new implmentation does not distingush between SBUS and cpu interrupts. I am no sure what is right here. I assume we need to do something for the cpu interrupts. I have not succeeded booting my sun4d box (with or without this patch) and my understanding of this platfrom is limited. So I would be a bit suprised if this works. leon: Introduce irq_chip Store mask in chip_data for use in mask/unmask functions Add build_device_irq for leon Use leon_build_device_irq in leon_init_timers Signed-off-by: Sam Ravnborg <[email protected]> Acked-by: Daniel Hellstrom <[email protected]> Tested-by: Daniel Hellstrom <[email protected]> Tested-by: Marcel van Nies <[email protected]> Cc: Thomas Gleixner <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-19sparc32: cleanup code for pci initSam Ravnborg3-16/+15
Move the ifdeffery to a header file to make the logic more obvious where we decide between PCI or SBUS init Signed-off-by: Sam Ravnborg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-19sparc32,sun4d: rename sbus_tid to board_to_cpu in irq supportSam Ravnborg1-5/+9
The new name reflects the actual usage much better. Signed-off-by: Sam Ravnborg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2011-04-19Merge branch 'drm-fixes' of ↵Linus Torvalds16-92/+102
git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 * 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/radeon/kms: pll tweaks for r7xx drm/nouveau: fix allocation of notifier object drm/nouveau: fix notifier memory corruption bug drm/nouveau: fix pinning of notifier block drm/nouveau: populate ttm_alloced with false, when it's not drm/nouveau: fix nv30 pcie boards drm/nouveau: split ramin_lock into two locks, one hardirq safe drm/radeon/kms: adjust evergreen display watermark setup drm/radeon/kms: add connectors even if i2c fails drm/radeon/kms: fix bad shift in atom iio table parser
2011-04-20drm/radeon/kms: pll tweaks for r7xxAlex Deucher1-5/+1
Prefer min m to max p only on pre-r7xx asics. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=36197 Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]>
2011-04-20Merge remote branch 'nouveau/drm-nouveau-fixes' of /ssd/git/drm-nouveau-next ↵Dave Airlie11-22/+36
into drm-fixes * 'nouveau/drm-nouveau-fixes' of /ssd/git/drm-nouveau-next: drm/nouveau: fix allocation of notifier object drm/nouveau: fix notifier memory corruption bug drm/nouveau: fix pinning of notifier block drm/nouveau: populate ttm_alloced with false, when it's not drm/nouveau: fix nv30 pcie boards drm/nouveau: split ramin_lock into two locks, one hardirq safe
2011-04-20drm/nouveau: fix allocation of notifier objectMarcin Slusarz1-1/+1
Commit 73412c3854c877e5f37ad944ee8977addde4d35a ("drm/nouveau: allocate kernel's notifier object at end of block") intended to align end of notifier block to page boundary, but start of block was miscalculated to be off by -16 bytes. Fix it. Signed-off-by: Marcin Slusarz <[email protected]> Cc: Ben Skeggs <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2011-04-20drm/nouveau: fix notifier memory corruption bugMarcin Slusarz1-2/+2
nouveau_bo_wr32 expects offset to be in words, but we pass value in bytes, so after commit 73412c3854c877e5f37ad944ee8977addde4d35a ("drm/nouveau: allocate kernel's notifier object at end of block") we started to overwrite some memory after notifier buffer object (previously m2mf_ntfy was always 0, so it didn't matter it was a value in bytes). Reported-by: Dominik Brodowski <[email protected]> Reported-by: Nigel Cunningham <[email protected]> Signed-off-by: Marcin Slusarz <[email protected]> Cc: Ben Skeggs <[email protected]> Cc: Pekka Paalanen <[email protected]> Cc: [email protected] [2.6.38] Signed-off-by: Ben Skeggs <[email protected]>
2011-04-20drm/nouveau: fix pinning of notifier blockBen Skeggs1-4/+7
Problem introduced with commit 6ba9a68317781537d6184d3fdb2d0f20c97da3a4 Reported-by: Bob Gleitsmann <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2011-04-20drm/nouveau: populate ttm_alloced with false, when it's notBen Skeggs1-0/+1
Caught with kmemcheck on unrelated business. Signed-off-by: Ben Skeggs <[email protected]>
2011-04-20drm/nouveau: fix nv30 pcie boardsBen Skeggs2-3/+3
Wasn't aware they even existed, apparently they do! They're actually AGP chips with a bridge as far as I can tell, which puts them in the same boat as nv40/nv45. Signed-off-by: Ben Skeggs <[email protected]>
2011-04-20drm/nouveau: split ramin_lock into two locks, one hardirq safeBen Skeggs6-12/+22
Fixes a possible lock ordering reversal between context_switch_lock and ramin_lock. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
2011-04-19Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6Linus Torvalds64-203/+330
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (51 commits) netfilter: ipset: Fix the order of listing of sets ip6_pol_route panic: Do not allow VLAN on loopback bnx2x: Fix port identification problem r8169: add Realtek as maintainer. ip: ip_options_compile() resilient to NULL skb route bna: fix memory leak during RX path cleanup bna: fix for clean fw re-initialization usbnet: Fix up 'FLAG_POINTTOPOINT' and 'FLAG_MULTI_PACKET' overlaps. iwlegacy: fix tx_power initialization Revert "tcp: disallow bind() to reuse addr/port" qlcnic: limit skb frags for non tso packet net: can: mscan: fix build breakage in mpc5xxx_can netfilter: ipset: set match and SET target fixes netfilter: ipset: bitmap:ip,mac type requires "src" for MAC sctp: fix oops while removed transport still using as retran path sctp: fix oops when updating retransmit path with DEBUG on net: Disable NETIF_F_TSO_ECN when TSO is disabled net: Disable all TSO features when SG is disabled sfc: Use rmb() to ensure reads occur in order ieee802154: Remove hacked CFLAGS in net/ieee802154/Makefile ...
2011-04-19Merge branch 'for-linus' of ↵Linus Torvalds2-3/+5
git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6 * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: PCI: pci-label: Fix build failure when CONFIG_NLS is set to 'm' by allmodconfig
2011-04-19Merge branch 'master' of ↵David S. Miller3-10/+30
git://git.kernel.org/pub/scm/linux/kernel/git/kaber/nf-2.6
2011-04-19Merge branch 'x86-fixes-for-linus' of ↵Linus Torvalds3-14/+21
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, gart: Make sure GART does not map physmem above 1TB x86, gart: Set DISTLBWALKPRB bit always x86, gart: Convert spaces to tabs in enable_gart_translation
2011-04-19Merge branch 'timer-fixes-for-linus' of ↵Linus Torvalds3-18/+13
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'timer-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: RTC: rtc-omap: Fix a leak of the IRQ during init failure posix clocks: Replace mutex with reader/writer semaphore
2011-04-19Merge branch 'perf-fixes-for-linus' of ↵Linus Torvalds11-49/+64
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: perf, x86: Fix AMD family 15h FPU event constraints perf, x86: Fix pre-defined cache-misses event for AMD family 15h cpus perf evsel: Fix use of inherit perf hists browser: Fix seg fault when annotate null symbol
2011-04-19Revert "[media] V4L: videobuf, don't use dma addr as physical"Linus Torvalds1-1/+1
This reverts commit 35d9f510b67b10338161aba6229d4f55b4000f5b. Quoth Jiri Slaby: "It fixes mmap when IOMMU is used on x86 only, but breaks architectures like ARM or PPC where virt_to_phys(dma_alloc_coherent) doesn't work. We need there dma_mmap_coherent or similar (the trickery what snd_pcm_default_mmap does but in some saner way). But this cannot be done at this phase." Requested-by: Jiri Slaby <[email protected]> Cc: Russell King - ARM Linux <[email protected]> Cc: Janusz Krzysztofik <[email protected]> Acked-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2011-04-19Merge git://git.kernel.org/pub/scm/linux/kernel/git/steve/gfs2-2.6-fixesLinus Torvalds9-34/+111
* git://git.kernel.org/pub/scm/linux/kernel/git/steve/gfs2-2.6-fixes: GFS2: filesystem hang caused by incorrect lock order GFS2: Don't try to deallocate unlinked inodes when mounted ro GFS2: directly write blocks past i_size GFS2: write_end error path fails to unlock transaction lock
2011-04-19netfilter: ipset: Fix the order of listing of setsJozsef Kadlecsik1-8/+10
A restoreable saving of sets requires that list:set type of sets come last and the code part which should have taken into account the ordering was broken. The patch fixes the listing order. Signed-off-by: Jozsef Kadlecsik <[email protected]> Signed-off-by: Patrick McHardy <[email protected]>
2011-04-19perf, x86: Fix AMD family 15h FPU event constraintsRobert Richter1-3/+17
Depending on the unit mask settings some FPU events may be scheduled only on cpu counter #3. This patch fixes this. Signed-off-by: Robert Richter <[email protected]> Signed-off-by: Peter Zijlstra <[email protected]> Cc: Stephane Eranian <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
2011-04-19perf, x86: Fix pre-defined cache-misses event for AMD family 15h cpusAndre Przywara1-1/+1
With AMD cpu family 15h a unit mask was introduced for the Data Cache Miss event (0x041/L1-dcache-load-misses). We need to enable bit 0 (first data cache miss or streaming store to a 64 B cache line) of this mask to proper count data cache misses. Now we set this bit for all families and models. In case a PMU does not implement a unit mask for event 0x041 the bit is ignored. Signed-off-by: Andre Przywara <[email protected]> Signed-off-by: Robert Richter <[email protected]> Signed-off-by: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.