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Use correct value for rtl phy support.
(rtl phy are in AX88178 devices like NWU220G and USB2-ET1000).
Signed-off-by: Allan Chou <[email protected]>
Tested-by: Grant Grundler <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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As per the comments added by this commit, %g2 turns out to not be a
usable place to save away orig_i0 for syscall restart handling.
In fact all of %g2, %g3, %g4, and %g5 are assumed to be saved across
a system call by various bits of code in glibc.
%g1 can't be used because that holds the syscall number, which would
need to be saved and restored for syscall restart handling too, and
that would only compound our problems :-)
This leaves us with %g6 and %g7 which are for "system use". %g7 is
used as the "thread register" by glibc, but %g6 is used as a compiler
and assembler temporary scratch register. And in no instance is %g6
used to hold a value across a system call.
Therefore %g6 is safe for storing away orig_i0, at least for now.
Signed-off-by: David S. Miller <[email protected]>
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There may be an issue when the user issue "reboot/shutdown" command, then
the device has shut down its hardware, after that, this runtime-pm featured
device's driver will probably be scheduled to do its suspend routine,
and at its suspend routine, it may access hardware, but the device has
already shutdown physically, then the system hang may be occurred.
I ran out this issue using an auto-suspend supported USB devices, like
3G modem, keyboard. The usb runtime suspend routine may be scheduled
after the usb controller has been shut down, and the usb runtime suspend
routine will try to suspend its roothub(controller), it will access
register, then the system hang occurs as the controller is shutdown.
Signed-off-by: Peter Chen <[email protected]>
Acked-by: Ming Lei <[email protected]>
Acked-by: Greg Kroah-Hartman <[email protected]>
Cc: [email protected]
Signed-off-by: Rafael J. Wysocki <[email protected]>
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The doalloc arg in xfs_qm_dqattach_one() is a flag that indicates
whether a new area to handle quota information will be allocated
if needed. Originally, it was passed to xfs_qm_dqget(), but has
been removed by the following commit (probably by mistake):
commit 8e9b6e7fa4544ea8a0e030c8987b918509c8ff47
Author: Christoph Hellwig <[email protected]>
Date: Sun Feb 8 21:51:42 2009 +0100
xfs: remove the unused XFS_QMOPT_DQLOCK flag
As the result, xfs_qm_dqget() called from xfs_qm_dqattach_one()
never allocates the new area even if it is needed.
This patch gives the doalloc arg to xfs_qm_dqget() in
xfs_qm_dqattach_one() to fix this problem.
Signed-off-by: Mitsuo Hayasaka <[email protected]>
Cc: Alex Elder <[email protected]>
Cc: Christoph Hellwig <[email protected]>
Reviewed-by: Christoph Hellwig <[email protected]>
Signed-off-by: Ben Myers <[email protected]>
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The crisv10.c and the atmel_serial.c serial drivers intepret the fields of the
serial_rs485 structure in a different way.
In particular, crisv10.c uses SER_RS485_RTS_AFTER_SEND and
SER_RS485_RTS_ON_SEND for the voltage of the RTS pin; atmel_serial.c,
instead, uses these values to know if a delay must be set before and
after sending. This patch makes the usage of these variables consistent
across all drivers and fixes the Documentation as well.
From now on, SER_RS485_RTS_AFTER_SEND and SER_RS485_RTS_ON_SEND will be
used to set the voltage of the RTS pin (as in the crisv10.c driver); the
delay will be understood by looking only at the value of
delay_rts_before_send and delay_rts_after_send.
Signed-off-by: Claudio Scordino <[email protected]>
Signed-off-by: Darron Black <[email protected]>
Acked-by: Jesper Nilsson <[email protected]>
Acked-by: Nicolas Ferre <[email protected]>
Acked-by: Alan Cox <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Changing UART mode PIO->DMA->PIO->DMA like below, pch_uart driver can't get
DMA channel resource.
setserial /dev/ttyPCH0 ^low_latency
setserial /dev/ttyPCH0 low_latency
CAUSE:
Changing mode using setserial command, ".startup" function which gets DMA
channel is called before ".verify_port" function which sets
dma-flag(use_dma/use_dma_flag) as 1.
PIO->DMA
.startup: Since dma-flag is 0, DMA channel is not requested.
.verify_port: dma-flag is set as 1.
.shutdown: N/A
DMA->PIO
.startup: Since dma-flag is 1, DMA channel is requested.
.verify_port: dma-flag is set as 0.
.shutdown: Since dma-flag is 0, DMA channel is not released.
This means DMA channel resource leak occurs.
Next time, this driver can't get DMA channel resource forever.
MODIFICATION:
Currently, when release DMA channel resource, this driver checks dma-flag.
However, this specification occurs the above issue.
This driver must check whether dma_request_channel is executed or not.
The values are saved in private data variable "chan_tx/chan_tx".
These variables mean if the value is NULL, DMA channel is not requested,
if not NULL, DMA channel is requested.
This patch fixes the issue.
Signed-off-by: Tomoya MORINAGA <[email protected]>
Acked-by: Alan Cox <[email protected]>
Cc: stable <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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This is referenced the wrong way. Mika Westerberg added some checks to the
tty to support multiple console, but the real problem is simply referencing the
termios object via the wrong path.
Signed-off-by: Alan Cox <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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On Tegra UARTs (except UART1), the DTR / DCD / DSR lines are not
externally accessible. Instead, the DTR line internally appears to be
looped back to be the input to the DCD and DSR lines. The net effect
of this is that when we drop DTR (like when we suspend), we'll see DCD
drop too. ...and when we see DCD drop, we treat that as a hangup.
In order to prevent this hangup from occurring at every sleep, we need
to force DTR to remain high on Tegra UARTs.
This patch uses the mcr_mask / mcr_force fields, which were originally
added for the kludge ALPHA_KLUDGE_MCR. Using these fields does not
prevent us from removing ALPHA_KLUDGE_MCR--we can just remove the "if"
tests I have added and always init mcr_mask / mcr_force from the
serial8250_config.
NOTE: If we have people that are using UARTA on a Tegra and need to
control DTR, we'll need to either add a separate port type for UARTA
or we'll need to add some tegra-specific code to detect whether the
DTR needs to be left high.
Signed-off-by: Doug Anderson <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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On October 1 in 2011,
OKI SEMICONDUCTOR Co., Ltd. changed the company name in to LAPIS Semiconductor Co., Ltd.
Signed-off-by: Tomoya MORINAGA <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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ML7831 is companion chip for Intel Atom E6xx series.
Signed-off-by: Tomoya MORINAGA <[email protected]>
Acked-by: Alan Cox <[email protected]>
Cc: stable <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Using hardware flow control,
currently, register of the control-bit(AFE) is not set.
This patch fixes the issue.
Signed-off-by: Tomoya MORINAGA <[email protected]>
Acked-by: Alan Cox <[email protected]>
Cc: stable <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Reading from the DCC grabs a character from the buffer and
clears the status bit. Since this is a context-changing
operation, instructions following the character read that rely on
the status bit being accurate need to be synchronized with an
ISB.
In this case, the status bit check needs to execute after the
character read otherwise we run the risk of reading the character
and checking the status bit before the read can clear the status
bit in the first place. When this happens, the user will see the
same character they typed twice, instead of once.
Add an ISB after the read and the write, so that the status check
is synchronized with the read/write operations.
Signed-off-by: Stephen Boyd <[email protected]>
Cc: stable <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Breno Leitao has passed the maintainership on to me.
Signed-off-by: Lucas Kannebley Tavares <[email protected]>
Acked-by: Breno Leitao <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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Fixes i2c test failures when i2c_algo_bit.bit_test=1.
The hw doesn't actually require a mask, so just set it
to the default mask bits for r1xx-r4xx radeon ddc.
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]
Cc: Jean Delvare <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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Noticed by Egbert.
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]
Cc: Egbert Eich <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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The 'name' attribute of struct uio_mem wasn't documented, and the note
about 'kobj' is stale and needs to be changed to 'map'.
Signed-off-by: Geoff Thorpe <[email protected]>
Signed-off-by: "Hans J. Koch" <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Fix warning of make xmldocs of documention of the struct member iommu_ops from struct bus_type.
Signed-off-by: Marcos Paulo de Souza <[email protected]>
Acked-by: Randy Dunlap <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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ISSUE:
Using ML7831, MAC address writing doesn't work well.
CAUSE:
ML7831 and EG20T have the same register map for MAC address access.
However, this driver processes the writing the same as ML7223.
This is not true.
This driver must process the writing the same as EG20T.
This patch fixes the issue.
Signed-off-by: Tomoya MORINAGA <[email protected]>
Cc: Masayuki Ohtak <[email protected]>
Cc: Alexander Stein <[email protected]>
Cc: Denis Turischev <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Cc: stable <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Currently, external ROM access is enabled/disabled in probe()/remove().
So, when a buggy software access unanticipated memory area,
in case of enabling this ADE bit,
external ROM memory area can be broken.
This patch enables the ADE bit only accessing external ROM area.
Signed-off-by: Tomoya MORINAGA <[email protected]>
Cc: Masayuki Ohtak <[email protected]>
Cc: Alexander Stein <[email protected]>
Cc: Denis Turischev <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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On October 1 in 2011,
OKI SEMICONDUCTOR Co., Ltd. changed the company name in to LAPIS Semiconductor Co., Ltd.
Signed-off-by: Tomoya MORINAGA <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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ML7831 is companion chip for Intel Atom E6xx series.
Signed-off-by: Tomoya MORINAGA <[email protected]>
Cc: stable <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Lockdep reports there is potential deadlock for slub node list_lock.
discard_slab() is called with the lock hold in unfreeze_partials(),
which could trigger a slab allocation, which could hold the lock again.
discard_slab() doesn't need hold the lock actually, if the slab is
already removed from partial list.
Acked-by: Christoph Lameter <[email protected]>
Reported-and-tested-by: Yong Zhang <[email protected]>
Reported-and-tested-by: Julie Sullivan <[email protected]>
Signed-off-by: Shaohua Li <[email protected]>
Signed-off-by: Pekka Enberg <[email protected]>
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unfreeze_partials() needs add the page to partial list tail, since such page
hasn't too many free objects. We now explictly use DEACTIVATE_TO_TAIL for this,
while DEACTIVATE_TO_TAIL != 1. This will cause performance regression (eg, more
lock contention in node->list_lock) without below fix.
Signed-off-by: Shaohua Li <[email protected]>
Acked-by: Christoph Lameter <[email protected]>
Acked-by: David Rientjes <[email protected]>
Signed-off-by: Pekka Enberg <[email protected]>
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Now that all platforms are converted to MULTI_IRQ_HANDLER, remove the
legacy support.
Tested-by: Thomas Abraham <[email protected]>
Signed-off-by: Jamie Iles <[email protected]>
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Now that there is a generic IRQ handler for multiple VIC devices use it
for picoxcell to help building multi platform kernels.
Signed-off-by: Jamie Iles <[email protected]>
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Now that there is a generic IRQ handler for multiple VIC devices use it
for samsung to help building multi platform kernels.
Cc: Kukjin Kim <[email protected]>
Tested-by: Thomas Abraham <[email protected]>
Signed-off-by: Jamie Iles <[email protected]>
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Now that there is a generic IRQ handler for multiple VIC devices use it
for versatile to help building multi platform kernels.
Cc: Russell King <[email protected]>
Tested-by: Marc Zyngier <[email protected]>
Signed-off-by: Jamie Iles <[email protected]>
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Now that there is a generic IRQ handler for multiple VIC devices use it
for u300 to help building multi platform kernels.
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Jamie Iles <[email protected]>
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Now that there is a generic IRQ handler for multiple VIC devices use it
for spear to help building multi platform kernels.
Acked-by: Viresh Kumar <[email protected]>
Cc: Rajeev Kumar <[email protected]>
Signed-off-by: Jamie Iles <[email protected]>
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Now that there is a generic IRQ handler for multiple VIC devices use it
for s3c64xx to help building multi platform kernels.
Cc: Ben Dooks <[email protected]>
Tested-by: Thomas Abraham <[email protected]>
Signed-off-by: Jamie Iles <[email protected]>
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Now that there is a generic IRQ handler for multiple VIC devices use it
for nomadik to help building multi platform kernels.
Cc: Alessandro Rubini <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Cc: STEricsson <[email protected]>
Tested-by: Thomas Abraham <[email protected]>
Signed-off-by: Jamie Iles <[email protected]>
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Now that there is a generic IRQ handler for multiple VIC devices use it
for netx to help building multi platform kernels.
Signed-off-by: Jamie Iles <[email protected]>
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Now that there is a generic IRQ handler for multiple VIC devices use it
for ep93xx to help building multi platform kernels.
Cc: Hartley Sweeten <[email protected]>
Cc: Ryan Mallon <[email protected]>
Signed-off-by: Jamie Iles <[email protected]>
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Add a handler for the VIC that is suitable for MULTI_IRQ_HANDLER
platforms. This can replace the ASM entry macros for platforms that use
the VIC.
v4: - rebase ontop of move __exception and friends to
asm/exception.h
- rework polling loop to handle as many irqs as possible in one go
v3: - simplify irq handling loop as suggested by Grant
- service interrupts from msb->lsb order
v2: - allow the handler be used for !CONFIG_OF
- use irq_domain_to_irq()
Cc: Rob Herring <[email protected]>
Acked-by: Grant Likely <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Tested-by: Thomas Abraham <[email protected]>
Signed-off-by: Jamie Iles <[email protected]>
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This adds a device tree binding for the VIC based on the of_irq_init()
support. This adds an irqdomain to the vic and always registers all
vics in the static vic array rather than for pm only to keep track of
the irq domain. struct irq_data::hwirq is used where appropriate rather
than runtime masking.
v3: - include linux/export.h for THIS_MODULE
v2: - use irq_domain_simple_ops
- remove stub implementation of vic_of_init for !CONFIG_OF
- Make VIC select IRQ_DOMAIN
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Grant Likely <[email protected]>
Tested-by: Thomas Abraham <[email protected]>
Signed-off-by: Jamie Iles <[email protected]>
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Now that MULTI_IRQ_HANDLER is selected by all the in-tree
GIC users, make it mandatory and remove the unused macros.
Signed-off-by: Marc Zyngier <[email protected]>
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After the MULTI_IRQ_HANDLER conversion, a couple of global
variables can be removed.
Signed-off-by: Marc Zyngier <[email protected]>
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Convert the omap2plus platforms to be using CONFIG_MULTI_IRQ_HANDLER.
Each machine is modified to provide either omap2_intc_handle_irq(),
omap3_intc_handle_irq() or gic_handle_irq().
This allows for a major cleanup, removing the MULTI_OMAP setup
from the interrupt path.
Tested on both Panda and IGEPv2 (single kernel image)
Tested-by: Tony Lindgren <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Provide the OMAP2/3 IRQ code with low level handlers that can be used
by platforms using CONFIG_MULTI_IRQ_HANDLER. Though the handlers are
written in C, the compiled code looks very similar to its assembly
counterpart (at least with my gcc 4.4.1).
Tested-by: Tony Lindgren <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Convert the zynq platform to be using the gic_handle_irq
function as its primary interrupt handler.
Acked-by: John Linn <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Convert the cns3xxx platform to be using the gic_handle_irq
function as its primary interrupt handler.
Acked-by: Anton Vorontsov <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Convert the SMP shmobile platforms to use gic_handle_irq() instead
of the assembly macro.
Cc: Paul Mundt <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Convert the ux500 platforms to be using the gic_handle_irq
function as their primary interrupt handler.
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Convert the tegra2 platforms to be using the gic_handle_irq
function as their primary interrupt handler.
Tested on harmony.
Cc: Colin Cross <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Acked-by: Olof Johansson <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Convert the Exynos4 platforms to be using the gic_handle_irq
function as their primary interrupt handler.
Cc: Ben Dooks <[email protected]>
Cc: Kukjin Kim <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Convert the SMP msm platforms to be using the gic_handle_irq
function as their primary interrupt handler.
Tested-by: David Brown <[email protected]>
Acked-by: David Brown <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Convert the VExpress platform to be using the gic_handle_irq
function as its primary interrupt handler.
Signed-off-by: Marc Zyngier <[email protected]>
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Convert the RealView platforms to be using the gic_handle_irq
function as their primary interrupt handler.
Signed-off-by: Marc Zyngier <[email protected]>
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Convert the highbank platform to be using the gic_handle_irq
function as its primary interrupt handler.
Cc: Rob Herring <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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