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2014-12-02drm/nv50/kms: use sclass() instead of trial-and-errorBen Skeggs1-6/+20
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nv50/kms: remove a couple of cursor-related stub functionsBen Skeggs2-12/+2
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: fix pin refcnt leak in failure pathBen Skeggs1-12/+12
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: synchronize BOs when requiredAlexandre Courbot3-0/+56
On architectures for which access to GPU memory is non-coherent, caches need to be flushed and invalidated explicitly when BO control changes between CPU and GPU. This patch adds buffer synchronization functions which invokes the correct API (PCI or DMA) to ensure synchronization is effective. Based on the TTM DMA cache helper patches by Lucas Stach. Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: allocate GPFIFOs and fences coherentlyAlexandre Courbot2-3/+3
Specify TTM_PL_FLAG_UNCACHED when allocating GPFIFOs and fences to allow them to be safely accessed by the kernel without being synced on non-coherent architectures. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: implement explicitly coherent BOsAlexandre Courbot2-8/+73
Allow nouveau_bo_new() to recognize the TTM_PL_FLAG_UNCACHED flag, which means that we want the allocated BO to be perfectly coherent between the CPU and GPU. This is useful on non-coherent architectures for which we do not want to manually sync some rarely-accessed buffers: typically, fences and pushbuffers. A TTM BO allocated with the TTM_PL_FLAG_UNCACHED on a non-coherent architecture will be populated using the DMA API, and accesses to it performed using the coherent mapping performed by dma_alloc_coherent(). Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: introduce nv_device_is_cpu_coherent()Alexandre Courbot1-0/+6
Add a function allowing us to know whether a device is CPU-coherent, i.e. accesses performed by the CPU on GPU-mapped buffers will be immediately visible on the GPU side and vice-versa. For now, a device is considered to be coherent if it uses the PCI bus on a non-ARM architecture. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: warn when moving a pinned objectAlexandre Courbot1-2/+9
Pinned BOs are supposed to remain in their current location until unpinned. Display a warning for the supposedly-erroneous case where we are trying to move such objects. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/disp: clear notify intr status when enabling, to prevent racesBen Skeggs2-0/+4
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nv50-/disp: rename class members to match nvidia channel namesBen Skeggs11-206/+206
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/core: remove some dead code that got forgottenBen Skeggs3-135/+0
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/pwr/fuc: Fix thinko in nouveau_memx_wait()Roy Spliet1-1/+1
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nva3/clock: Allow user reclockingRoy Spliet1-1/+1
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/fb/ramnva3: Reclocking script for GDDR3Roy Spliet2-10/+92
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/fb/ramnva3: Reclocking script for DDR2Roy Spliet1-15/+42
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/fb/ramnva3: Reclocking script for DDR3Roy Spliet3-75/+219
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/fb/ramnva3: Ressurect timing calculation codeRoy Spliet3-14/+132
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/fb/ramnva3: Link training for DDR3Roy Spliet10-1415/+2259
V2: fix whitespace errors in memx.fuc Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/fb/gddr3: Generate MR valuesRoy Spliet3-0/+119
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios/ramcfg: 10_02_40 -> DLLoffRoy Spliet4-4/+4
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: move the (far too many...) different s/r paths to the same placeBen Skeggs2-138/+144
No code changes. Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/gk104-/fifo: handle copy engine class errorsBen Skeggs1-6/+42
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: stop after NV+NPDS+ISBN imageBen Skeggs1-4/+9
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: add some more signatures as seen on my gtx660Ben Skeggs2-0/+2
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: add support for gm204Ben Skeggs3-11/+16
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/device: recognise GM204Ben Skeggs2-1/+45
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/gm204/disp: some magic that fixes bringup of uninitialised outputsBen Skeggs5-3/+24
Probably missing something here, doesn't make a lot of sense to write or+link data into a register whose offset is calculated by the same or+link info.. This is the all I've witnessed the binary driver and vbios doing so far, so it'll do. Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/gm204/disp: initial supportBen Skeggs8-1/+255
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/gf110-/disp: magic that might help some tmds issuesBen Skeggs1-2/+10
The binary driver has been doing this since GF119, and we've somehow gotten away with it. But, TMDS that hasn't been initialised already by the x86 vbios code is distorted without it on GM204. Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: support for opcodes 0x47/0x48Ben Skeggs1-0/+36
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: add support for udisp 2.2Ben Skeggs1-0/+1
Not entirely sure why this got bumped at all yet. Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: add support for dp 4.1Ben Skeggs1-1/+9
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/i2c: add support for DCB_I2C_PMGR port typeBen Skeggs1-0/+12
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: add support for ccb 4.1Ben Skeggs2-7/+25
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: add support for dcb 4.1Ben Skeggs1-12/+15
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/gm204/i2c: add aux channel driverBen Skeggs7-3/+233
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/gm204/i2c: add pad driverBen Skeggs3-0/+88
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/i2c: segregate aux channel adapter indices from bit-banged i2cBen Skeggs5-3/+15
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: store aux addr independently of i2cBen Skeggs4-41/+73
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nv50-/i2c: kill some unused struct membersBen Skeggs3-15/+0
Left-over from before a rework a while back. Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: log if auxch accesses fail, also return 0x00 from rd when ↵Ben Skeggs1-7/+11
it does Logging at trace level, rather than as en error, as it seems conceivable that failure could be normal under certain circumstances (new bios, older sink that doesn't support a particular DPCD address) Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/gm204/devinit: initial implementationBen Skeggs5-1/+178
Starting from GM204, certain registers are no longer accessible by the host (or unsigned PMU firmware). This commit implements devinit on PMU, using a signed microcode image, and devinit data, from the VBIOS. Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/devinit: allow impl to select its own cold-boot methodBen Skeggs14-3/+15
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: add parsing of pmu image tablesBen Skeggs3-0/+173
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: recognise nv-specific rom/pcir signaturesBen Skeggs2-0/+2
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: use NPDE to locate images beyond those defined by PCIRBen Skeggs1-0/+7
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: add NPDE parsingBen Skeggs3-0/+72
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: fetch images beyond the first one in the romBen Skeggs1-4/+7
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: use size/type from pci data structureBen Skeggs1-2/+8
The field at +0x2 is technically processor specific, though I don't know that it's ever mattered in practice (yet). Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: add pci data structure parsingBen Skeggs3-0/+86
Signed-off-by: Ben Skeggs <[email protected]>
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