aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2021-10-15ARM: dts: stm32: fix STUSB1600 Type-C irq level on stm32mp15xx-dkxFabrice Gasnier1-1/+1
STUSB1600 IRQ (Alert pin) is active low (open drain). Interrupts may get lost currently, so fix the IRQ type. Fixes: 83686162c0eb ("ARM: dts: stm32: add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx") Signed-off-by: Fabrice Gasnier <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2021-10-15ARM: dts: stm32: set the DCMI pins on stm32mp157c-odysseyGrzegorz Szymaszek1-0/+6
The Seeed Odyssey-STM32MP157C board has a 20-pin DVP camera output. The DCMI pins used on this output are defined in the pin state definition &pinctrl/dcmi-1, AKA &dcmi_pins_b (added in mainline commit 02814a41529a55dbfb9fbb2a3728e78e70646ea6). Set these pins as the default pinctrl of the DCMI peripheral in the board device tree. The pins are not used for any other purpose, so it seems safe to assume most users will not need to override (delete) what this patch provides. status defaults to "disabled", so the peripheral will not be unnecessarily started. And the users who actually intend to make use of a camera on the DVP port will have this little part of the configuration ready. Signed-off-by: Grzegorz Szymaszek <[email protected]> Reviewed-by: Ahmad Fatoum <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2021-10-15ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHzMarek Vasut1-1/+1
The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM, which causes additional signal delay. At 108 MHz, this delay triggers a sporadic issue where the first bit of RX data is not received by the QSPI controller. There are two options of addressing this problem, either by using the DLYB block to compensate the extra delay, or by reducing the QSPI bus clock frequency. The former requires calibration and that is overly complex, so opt for the second option. Fixes: 76045bc457104 ("ARM: dts: stm32: Add QSPI NOR on AV96") Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2021-10-15ARM: dts: stm32: add initial support of stm32mp135f-dk boardAlexandre Torgue3-0/+121
Add support of stm32mp135f discovery board (part number: STM32MP135F-DK). It embeds a STM32MP135F SOC with 512 MB of DDR3. Several connections are available on this board: 4*USB2.0, 1*USB2.0 typeC DRD, SDcard, 2*RJ45, HDMI, Combo Wifi/BT, ... Only SD card, uart4 (console) and watchdog IPs are enabled in this commit. Signed-off-by: Alexandre Torgue <[email protected]> Acked-by: Arnd Bergmann <[email protected]>
2021-10-15dt-bindings: stm32: document stm32mp135f-dk boardAlexandre Torgue1-0/+4
Add new entry for stm32mp135f-dk board. Signed-off-by: Alexandre Torgue <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Acked-by: Rob Herring <[email protected]>
2021-10-15ARM: dts: stm32: add STM32MP13 SoCs supportAlexandre Torgue5-0/+366
Add initial support of STM32MP13 family. The STM32MP13 SoC diversity is composed by: -STM32MP131: -core: 1*CA7, 17*TIMERS, 5*LPTIMERS, DMA/MDMA/DMAMUX -storage: 3*SDMCC, 1*QSPI, FMC -com: USB (OHCI/EHCI, OTG), 5*I2C, 5*SPI/I2S, 8*U(S)ART -audio: 2*SAI -network: 1*ETH(GMAC) -STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1 -STM32MP135: STM32MP133 + DCMIPP, LTDC A second diversity layer exists for security features: -STM32MP13xY, "Y" gives information: -Y = A/D means no cryp IP and no secure boot. -Y = C/F means cryp IP + secure boot. This commit adds basic peripheral. Signed-off-by: Alexandre Torgue <[email protected]> Acked-by: Arnd Bergmann <[email protected]>
2021-10-15dt-bindings: interconnect: sunxi: Add R40 MBUS compatibleMaxime Ripard1-0/+1
The R40 MBUS compatible was introduced recently but it was never documented. Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-10-15mailmap: Fix text encoding for Niklas SöderlundNiklas Söderlund1-0/+1
There are commits that mess up the encoding of 'ö' in Söderlund, add a correct entry to .mailmap. Signed-off-by: Niklas Söderlund <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-10-15ARM: dts: ls1021a-tsn: use generic "jedec,spi-nor" compatible for flashLi Yang1-1/+1
We cannot list all the possible chips used in different board revisions, just use the generic "jedec,spi-nor" compatible instead. This also fixes dtbs_check error: ['jedec,spi-nor', 's25fl256s1', 's25fl512s'] is too long Signed-off-by: Li Yang <[email protected]> Reviewed-by: Kuldeep Singh <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: ls1021a: move thermal-zones node out of soc/Li Yang1-33/+33
This fixes dtbs-check error from simple-bus schema: soc: thermal-zones: {'type': 'object'} is not allowed for {'cpu-thermal': ..... } From schema: /home/leo/.local/lib/python3.8/site-packages/dtschema/schemas/simple-bus.yaml Signed-off-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: ls1021a-tsn: remove undocumented property "position" from mma8452 nodeLi Yang1-1/+0
Property "postion" is not documented in the mma8452 binding. Remove it to resolve the error in "make dtbs_check" Signed-off-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: ls1021a-qds: change fpga to simple-mfd deviceLi Yang1-1/+1
The FPGA is not really a bus but more like an MFD device. Change the compatible string from "simple-bus" to "simple-mfd". This also fix a node name issue with simple-bus schema. Signed-off-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: ls1021a: add #power-domain-cells for power-controller nodeLi Yang1-0/+1
Add the #power-domain-cells for power-controller node as required by the schema. Signed-off-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: ls1021a: add #dma-cells to qdma nodeLi Yang1-0/+1
Add the #dma-cells to align with the dma schema. Signed-off-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: ls1021a: fix memory node for schema checkLi Yang1-1/+1
Fix the following error from "make dtbs_check" memory: False schema does not allow ... Signed-off-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: ls1021a: remove regulators simple-busLi Yang2-26/+12
There is no regulator bus in hardware. So move the regulator nodes out and remove the regulators simple-bus. This also make the dts align with the simple-bus schema. Signed-off-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: ls1021a: disable ifc node by defaultLi Yang2-3/+4
Disable the bus in the SoC dtsi file to be enabled only in board dts files. Also breakup long values in the ifc node to fix dtbs_check. Signed-off-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: ls1021a: breakup long values in thermal nodeLi Yang1-36/+36
Breakup long values to pass the schema check. Signed-off-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: ls1021a: fix board compatible to follow binding schemaLi Yang2-1/+1
Align the compatible strings with the board binding defined in schema file. Signed-off-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: ls1021a: update pcie nodes for dt-schema checkLi Yang1-8/+8
Break up long values to pass dt-schema checks. Signed-off-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: ls1021a-qds: Add node for QSPI flashLi Yang1-0/+14
Add the missing node for qspi flash. Signed-off-by: Li Yang <[email protected]> Reviewed-by: Kuldeep Singh <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: ls1021a: change to use SPDX identifiersLi Yang3-129/+3
Replace the license text with SPDX identifiers. Signed-off-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: ls1021a: change dma channels order to match schemaLi Yang1-6/+6
Although the ordering of DMA channels was not relevant in the txt binding, it is defined as ordered in the converted yaml schema. Update the dts to match the order. Signed-off-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: ls1021a: remove clock-names property for i2c nodesLi Yang1-3/+0
The property is optional and not used in matching the clock in driver. Remove it to avoid dtbs_check issues. Signed-off-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15dt-bindings: arm: fsl: add ls1021a-tsn boardLi Yang1-0/+1
Add the missing board in the binding docuemnt. Signed-off-by: Li Yang <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: imx6dl-prtrvt: drop undocumented TRF7970A NFC propertiesKrzysztof Kozlowski1-2/+0
Neither the bindings nor the device driver use/document "vin-voltage-override" and "t5t-rmb-extra-byte-quirk" properties. Cc: Oleksij Rempel <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Oleksij Rempel <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15arm64: dts: imx8mm-venice-gw7901.dts: disable pgc_gpumixTim Harvey1-0/+24
Since commit b21269b12e48 ("arm64: dts: imx8mm: add GPC node") the GW7901 will hang during kernel init because it does not power the unused GPU voltage rails on the IMX8MM. Disable pgc_gpumix to work around this. We also disable the GPU devices that depend on the gpumix power domain and pgc_gpu to avoid them staying in a probe deferred state forever. Additionally as the MIPI voltage rail is also not connected on this board we disable pgc_mipi and disp_blk_ctrl. Signed-off-by: Tim Harvey <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15arm64: dts: imx8mq-librem5: set debounce interval of volume buttons to 50msSebastian Krzyszkowiak1-0/+2
The default of 5ms is too low. Signed-off-by: Sebastian Krzyszkowiak <[email protected]> Signed-off-by: Martin Kepplinger <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15arm64: dts: imx8mq-librem5: Limit the max sdio frequencyAngus Ainslie1-0/+1
This is needed for the 1LV Cyress WiFi module to probe correctly. It also helps improve GNSS sensitivity. Signed-off-by: Angus Ainslie <[email protected]> Signed-off-by: Martin Kepplinger <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15arm64: dts: imx8mq-librem5: add power sequencing for M.2 cardsAngus Ainslie1-0/+23
Some wifi cards need reset asserted until after the power supplies have been enabled. So wire up the W_DISABLE signal for the SDIO port (WIFI_REG_ON net) and the BT_REG_ON net to use it for power sequencing. Signed-off-by: Angus Ainslie <[email protected]> Signed-off-by: Martin Kepplinger <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15arm64: dts: imx8mq-librem5: delay the startup of the SDIOAngus Ainslie1-0/+1
The redpine wifi card takes some time to wake up. Wait for it. Signed-off-by: Angus Ainslie <[email protected]> Signed-off-by: Martin Kepplinger <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15arm64: dts: imx8mq-librem5: wire up the wifi regulatorGuido Günther1-0/+12
Connect the wifi power regulator to the corresponding GPIO. Signed-off-by: Guido Günther <[email protected]> Signed-off-by: Martin Kepplinger <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15arm64: dts: imx8mq-librem5: Fix led_r and led_g pinctrl assignmentsSebastian Krzyszkowiak1-2/+2
Fix wrong pinctrl assignments. Signed-off-by: Sebastian Krzyszkowiak <[email protected]> Suggested-by: Eric Kuzmenko <[email protected]> Signed-off-by: Martin Kepplinger <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15arm64: dts: imx8mq-librem5: add reset gpio to mantix panel descriptionMartin Kepplinger1-0/+1
Add the missing description for the reset gpio to the panels DT description. Signed-off-by: Martin Kepplinger <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-15ARM: dts: imx6: phytec: Add gpio pinctrl for i2c bus recoveryYunus Bas3-7/+47
Make use of the i2c bus recovery feature and enable it on PHYTEC phyCORE-based modules and boards. Signed-off-by: Yunus Bas <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-14ARM: dts: ux500: Switch battery nodes to standardLinus Walleij10-18/+44
This force-converts the per-device battery node into the standard properties using "simple-battery" for the HREF machines and the corresponding Samsung battery for the mobile phones. This is fine to do since the battery data in the DTS files has never been deployed or used. In commit a1149ae97554 "ARM: ux500: Disable Power Supply and Battery Management by default" it was turned off and has not been switched back on since. In the meantime standardized bindings for batteries have appeared making the old AB8500 battery bindings obsolete. The battery node which is now in the middle of an included file is obviously a per-device piece of information so push this down to each board. The HREF machines all have the same battery and can share a single node in the HREF dtsi file. Signed-off-by: Linus Walleij <[email protected]>
2021-10-14arm64: dts: renesas: rcar-gen3e: Add Cortex-A57 2 GHz oppsGeert Uytterhoeven3-0/+27
Add operating points for running the Cortex-A57 CPU cores on R-Car H3e-2G, M3e-2G, and M3Ne-2G at 2 GHz. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/08a0f27f50b8ad4a78c05186190bebcfb364fe8f.1634200489.git.geert+renesas@glider.be
2021-10-14arm64: dts: renesas: rzg2l-smarc-som: Enable EthernetBiju Das2-1/+97
Enable Ethernet{0,1} interfaces on RZ/G2L SMARC EVK. Signed-off-by: Biju Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-10-14arm64: dts: renesas: r9a07g044: Add GbEthernet nodesBiju Das1-0/+40
Add Gigabit Ethernet{0,1} nodes to SoC DTSI. Signed-off-by: Biju Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-10-14arm64: dts: renesas: Add ports node to all adv7482 nodesNiklas Söderlund2-45/+49
The different port@ entries of the adv7482 nodes shall be encapsulated in a ports node, add one. This change does not change how the driver parses the DT and no driver change is needed. The change however makes it possible to validate the source files with a correct json-schema. Signed-off-by: Niklas Söderlund <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-10-14arm64: dts: renesas: r8a779a0: Add and connect all CSI-2, ISP and VIN nodesNiklas Söderlund1-0/+1332
The V3U have 32 VIN, 4 CSI-2 and 4 ISP nodes that interact with each other for video capture. Add all nodes and record how they are interconnected. Signed-off-by: Niklas Söderlund <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-10-14ARM: dts: aspeed: fp5280g2: Use the 64M layoutJohn Wang1-1/+1
Use the 64M layout since the flash on the board is 64M Signed-off-by: John Wang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joel Stanley <[email protected]>
2021-10-14arm64: dts: allwinner: NanoPi R1S H5: Add generic compatible string for I2C ↵Chukun Pan1-1/+8
EEPROM The 'microchip,24c02' compatible does not match the at24 driver, so add this generic fallback to the device node compatible string to make the device to match the driver using the OF device ID table. Also set this eeprom to read-only mode because it stores the mac address of the onboard usb network card. Signed-off-by: Chukun Pan <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-10-13arm64: dts: marvell: add Globalscale MOCHAbinRobert Marko2-0/+459
Globalscale MOCHAbin is a Armada 7040 based development board. Specifications: * Armada 7040 Quad core ARMv8 Cortex A-72 @ 1.4GHz * 2 / 4 / 8 GB of DDR4 DRAM * 16 GB eMMC * 4MB SPI-NOR (Bootloader) * 1x M.2-2280 B-key socket (for SSD expansion, SATA3 only) * 1x M.2-2250 B-key socket (for modems, USB2.0 and I2C only) * 1x Mini-PCIe 3.0 (x1, USB2.0 and I2C) * 1x SATA 7+15 socket (SATA3) * 1x 16-pin (2×8) MikroBus Connector * 1x SIM card slot (Connected to the mini-PCIe and both M.2 slots) * 2x USB3.0 Type-A ports via SMSC USB5434B hub * Cortex 2x5 JTAG * microUSB port for UART (PL2303GL/PL2303SA onboard) * 1x 10G SFP+ * 1x 1G SFP (Connected to 88E1512 PHY) * 1x 1G RJ45 with PoE PD (Connected to 88E1512 PHY) * 4x 1G RJ45 ports via Topaz 88E6141 switch * RTC with battery holder (SoC provided, requires CR2032 battery) * 1x 12V DC IN * 1x Power switch * 1x 12V fan header (3-pin, power only) * 1x mini-PCIe LED header (2x0.1" pins) * 1x M.2-2280 LED header (2x0.1" pins) * 6x Bootstrap jumpers * 1x Power LED (Green) * 3x Tri-color RGB LEDs (Controllable) * 1x Microchip ATECC608B secure element Note that 1G SFP and 1G WAN cannot be used at the same time as they are in parallel connected to the same PHY. Signed-off-by: Robert Marko <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2021-10-13ARM: dts: mvebu: add device tree for netgear gs110emx switchMarcel Ziswiler2-0/+296
Add the device tree for a Netgear GS110EMX switch featuring 8 Gigabit ports and 2 Multi-Gig ports (100M/1G/2.5G/5G/10G). An 88E6390X switch sits at its core connecting to two 88X3310P 10G PHYs. The control plane is handled by an 88F6811 Armada 381 SoC. The following functionality is tested: - 8 gigabit Ethernet ports connecting via 88E6390X to the 88F6811 - serial console UART - 128 MB commercial grade DDR3L SDRAM - 16 MB serial SPI NOR flash The two 88X3310P 10G PHYs while detected during boot seem neither to detect any link nor pass any traffic. Signed-off-by: Marcel Ziswiler <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2021-10-12Merge tag 'tags/bcm2835-dt-fixes-2021-10-06' into devicetree/fixesFlorian Fainelli4-15/+24
A series of devicetree fixes for the Raspberry Pi 4: - Fix VEC reg address - Fix MDIO address/size cells - Fix regulator states - Fix PCIe address formatting Signed-off-by: Florian Fainelli <[email protected]>
2021-10-12ARM: dts: bcm2711-rpi-4-b: Fix usb's unit addressNicolas Saenz Julienne1-2/+2
The unit address is supposed to represent '<device>,<function>'. Which are both 0 for RPi4b's XHCI controller. On top of that although OpenFirmware states bus number goes in the high part of the last reg parameter, FDT doesn't seem to care for it[1], so remove it. [1] https://patchwork.kernel.org/project/linux-arm-kernel/patch/[email protected]/#24414633 Fixes: 258f92d2f840 ("ARM: dts: bcm2711: Add reset controller to xHCI node") Suggested-by: Rob Herring <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Nicolas Saenz Julienne <[email protected]>
2021-10-12ARM: dts: bcm2711-rpi-4-b: Fix pcie0's unit address formattingNicolas Saenz Julienne1-1/+2
dtbs_check currently complains that: arch/arm/boot/dts/bcm2711-rpi-4-b.dts:220.10-231.4: Warning (pci_device_reg): /scb/pcie@7d500000/pci@1,0: PCI unit address format error, expected "0,0" Unsurprisingly pci@0,0 is the right address, as illustrated by its reg property: &pcie0 { pci@0,0 { /* * As defined in the IEEE Std 1275-1994 document, * reg is a five-cell address encoded as (phys.hi * phys.mid phys.lo size.hi size.lo). phys.hi * should contain the device's BDF as 0b00000000 * bbbbbbbb dddddfff 00000000. The other cells * should be zero. */ reg = <0 0 0 0 0>; }; }; The device is clearly 0. So fix it. Also add a missing 'device_type = "pci"'. Fixes: 258f92d2f840 ("ARM: dts: bcm2711: Add reset controller to xHCI node") Suggested-by: Rob Herring <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Nicolas Saenz Julienne <[email protected]>
2021-10-12Merge tag 'ti-k3-dt-for-v5.16' of ↵Arnd Bergmann27-125/+1665
git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux into arm/dt Devicetree changes for TI K3 platforms for v5.16 merge window: * New Platforms: - AM654: Siemens IOT2050 PG2 boards - J721E: Low cost SK board * New features: - mmc aliases introduced - AM64 ICSSG nodes, mcu pinctrl added * Fixes: - Schema fixups for pcie, thermal zones - Fixup to include board specific property for J721e-evm and j7200-evm - Misc fixups including cleaning up order in Makefile * tag 'ti-k3-dt-for-v5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux: (24 commits) arm64: dts: ti: k3-j721e-sk: Add DDR carveout memory nodes arm64: dts: ti: k3-j721e-sk: Add IPC sub-mailbox nodes arm64: dts: ti: Add support for J721E SK dt-bindings: arm: ti: Add compatible for J721E SK arm64: dts: ti: iot2050: Add support for product generation 2 boards arm64: dts: ti: iot2050: Prepare for adding 2nd-generation boards dt-bindings: arm: ti: Add bindings for Siemens IOT2050 PG2 boards arm64: dts: ti: iot2050: Add/enabled mailboxes and carve-outs for R5F cores arm64: dts: ti: iot2050: Disable SR2.0-only PRUs arm64: dts: ti: iot2050: Flip mmc device ordering on Advanced devices arm64: dts: ti: k3-j7200-common-proc-board: Add j7200-evm compatible arm64: dts: ti: k3-j721e-common-proc-board: Add j721e-evm compatible dt-bindings: arm: ti: Add missing compatibles for j721e/j7200 evms arm64: dts: ti: Makefile: Collate AM64 platforms together arm64: dts: ti: k3-am64-main: Add ICSSG nodes arm64: dts: ti: k3-am65: Relocate thermal-zones to SoC specific location arm64: dts: ti: ti-k3*: Introduce aliases for mmc nodes arm64: dts: ti: k3-am65-main: Cleanup "ranges" property in "pcie" DT node arm64: dts: ti: j7200-main: Add *max-virtual-functions* for pcie-ep DT node arm64: dts: ti: j7200-main: Fix "bus-range" upto 256 bus number for PCIe ... Link: https://lore.kernel.org/r/20211012120817.beqhp4tygnf3xyi5@wireless Signed-off-by: Arnd Bergmann <[email protected]>
2021-10-12arm64: dts: exynos: add minimal support for exynosautov9 sadk boardChanho Park3-1/+64
SADK(Samsung Automotive Development Kit) is the development kit to evaluate Exynos Auto v9 SoC. It has 16GB LPDDR4 DRAM and two 256GB Samsung UFS. This patch enables only serial console and ufs0 device. Signed-off-by: Chanho Park <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.