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2017-02-21Merge branch 'pci/host-xgene' into nextBjorn Helgaas1-6/+5
* pci/host-xgene: PCI: xgene: Configure PCIe MPS settings PCI: xgene: Fix double free on init error
2017-02-21Merge branch 'pci/host-versatile' into nextBjorn Helgaas1-1/+3
* pci/host-versatile: PCI: versatile: Configure PCIe MPS settings
2017-02-21Merge branch 'pci/host-thunder' into nextBjorn Helgaas1-5/+20
* pci/host-thunder: PCI: thunder-pem: Add support for cn81xx and cn83xx SoCs
2017-02-21Merge branch 'pci/host-rockchip' into nextBjorn Helgaas2-39/+138
* pci/host-rockchip: PCI: rockchip: Set vendor ID from local core config space PCI: rockchip: Fix rockchip_pcie_probe() error path to free resource list PCI: rockchip: Mark PM functions as __maybe_unused PCI: rockchip: Use readl_poll_timeout() instead of open-coding it PCI: rockchip: Disable RC's ASPM L0s based on DT "aspm-no-l0s" PCI: rockchip: Add system PM support
2017-02-21Merge branch 'pci/host-rcar' into nextBjorn Helgaas2-7/+3
* pci/host-rcar: PCI: rcar: Use of_device_get_match_data() to simplify probe PCI: rcar: Add compatible string for r8a7796 PCI: rcar: Return -ENODEV from host bridge probe when no card present
2017-02-21Merge branch 'pci/host-mvebu' into nextBjorn Helgaas2-43/+63
* pci/host-mvebu: PCI: mvebu: Change delay after reset to the PCIe spec mandated 100ms PCI: mvebu: Handle changes to the bridge windows while enabled
2017-02-21Merge branch 'pci/host-layerscape' into nextBjorn Helgaas1-6/+1
* pci/host-layerscape: PCI: layerscape: Use of_device_get_match_data() to simplify probe Conflicts: drivers/pci/dwc/pci-layerscape.c
2017-02-21Merge branch 'pci/host-iproc' into nextBjorn Helgaas3-7/+26
* pci/host-iproc: PCI: Add Broadcom Northstar2 PAXC quirk for device class and MPSS PCI: iproc: Configure PCIe MPS settings PCI: iproc: Use of_device_get_match_data() to simplify probe
2017-02-21Merge branch 'pci/host-imx6' into nextBjorn Helgaas1-35/+2
* pci/host-imx6: PCI: imx6: Fix a typo in error message PCI: imx6: Remove LTSSM disable workaround PCI: imx6: Remove redundant "Link never came up" message Conflicts: drivers/pci/dwc/pci-imx6.c
2017-02-21Merge branch 'pci/host-hv' into nextBjorn Helgaas1-3/+17
* pci/host-hv: PCI: hv: Use device serial number as PCI domain PCI: hv: Fix wslot_to_devfn() to fix warnings on device removal
2017-02-21Merge branch 'pci/host-hisi' into nextBjorn Helgaas5-12/+112
* pci/host-hisi: PCI: generic: Call pci_fixup_irqs() only on ARM PCI: Disable MSI for HiSilicon Hip06/Hip07 Root Ports PCI: hisi: Rename config space accessors to remove "acpi" PCI: hisi: Add DT almost-ECAM support for Hip06/Hip07 host controllers PCI: hisi: Use of_device_get_match_data() to simplify probe Conflicts: drivers/pci/dwc/pcie-hisi.c
2017-02-21Merge branch 'pci/host-exynos' into nextBjorn Helgaas6-226/+673
* pci/host-exynos: PCI: exynos: Support the PHY generic framework Documentation: binding: Modify the exynos5440 PCIe binding phy: phy-exynos-pcie: Add support for Exynos PCIe PHY Documentation: samsung-phy: Add exynos-pcie-phy binding PCI: exynos: Refactor to make it easier to support other SoCs PCI: exynos: Remove duplicated code PCI: exynos: Use the bitops BIT() macro to build bitmasks PCI: exynos: Remove unnecessary local variables PCI: exynos: Replace the *_blk/*_phy/*_elb accessors PCI: exynos: Rename all pointer names from "exynos_pcie" to "ep" Conflicts: drivers/pci/dwc/pci-exynos.c
2017-02-21Merge branch 'pci/host-altera' into nextBjorn Helgaas1-1/+1
* pci/host-altera: PCI: altera: Extract TLP completion status correctly
2017-02-21Merge branch 'pci/host-designware' into nextBjorn Helgaas24-1030/+1333
* pci/host-designware: PCI: dwc: Remove dependency of designware on CONFIG_PCI PCI: dwc: Add CONFIG_PCIE_DW_HOST to enable PCI dwc host PCI: dwc: Split pcie-designware.c into host and core files PCI: dwc: designware: Fix style errors in pcie-designware.c PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc() PCI: dwc: all: Split struct pcie_port into host-only and core structures PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init() PCI: dwc: all: Rename cfg_read/cfg_write to read/write PCI: dwc: all: Use platform_set_drvdata() to save private data PCI: dwc: designware: Move register defines to designware header file PCI: dwc: Use PTR_ERR_OR_ZERO to simplify code PCI: dra7xx: Group PHY API invocations PCI: dra7xx: Enable MSI and legacy interrupts simultaneously PCI: dra7xx: Add support to force RC to work in GEN1 mode PCI: dra7xx: Simplify probe code with devm_gpiod_get_optional() PCI: Move DesignWare IP support to new drivers/pci/dwc/ directory PCI: designware: Check for iATU unroll only on platforms that use ATU
2017-02-21PCI: dwc: Remove dependency of designware on CONFIG_PCIKishon Vijay Abraham I3-4/+15
CONFIG_PCI is used to enable host mode PCI. In preparation for adding endpoint mode support to designware driver, remove the dependency of designware on CONFIG_PCI and make only the host-specific part depend on CONFIG_PCI. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-21PCI: dwc: Add CONFIG_PCIE_DW_HOST to enable PCI dwc hostKishon Vijay Abraham I3-16/+42
Now that PCI designware host has a separate file, add a new PCIE_DW_HOST config symbol to select the host-only driver. This will enable to independently select host support and endpoint support (when it's added). Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-21PCI: dwc: Split pcie-designware.c into host and core filesKishon Vijay Abraham I4-624/+650
Split pcie-designware.c into pcie-designware-host.c that contains the host specific parts of the driver and pcie-designware.c that contains the parts used by both host driver and endpoint driver. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-21PCI: dwc: designware: Fix style errors in pcie-designware.cKishon Vijay Abraham I1-21/+21
No functional change. Fix all checkpatch warnings and check errors in pcie-designware.c Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-By: Joao Pinto <[email protected]>
2017-02-21PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc()Kishon Vijay Abraham I2-8/+11
The "num-lanes" DT property is parsed in dw_pcie_host_init(). However num-lanes is applicable to both root complex mode and endpoint mode. As a first step, move the parsing of this property outside dw_pcie_host_init(). This is in preparation for splitting pcie-designware.c to pcie-designware.c and pcie-designware-host.c Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-21PCI: dwc: all: Split struct pcie_port into host-only and core structuresKishon Vijay Abraham I15-481/+666
Keep only the host-specific members in struct pcie_port and move the common members (i.e common to both host and endpoint) to struct dw_pcie. This is in preparation for adding endpoint mode support to designware driver. While at that also fix checkpatch warnings. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> CC: Jingoo Han <[email protected]> CC: Richard Zhu <[email protected]> CC: Lucas Stach <[email protected]> CC: Murali Karicheri <[email protected]> CC: Minghuan Lian <[email protected]> CC: Mingkai Hu <[email protected]> CC: Roy Zang <[email protected]> CC: Thomas Petazzoni <[email protected]> CC: Niklas Cassel <[email protected]> CC: Jesper Nilsson <[email protected]> CC: Joao Pinto <[email protected]> CC: Zhou Wang <[email protected]> CC: Gabriele Paoloni <[email protected]> CC: Stanimir Varbanov <[email protected]> CC: Pratyush Anand <[email protected]>
2017-02-21PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init()Kishon Vijay Abraham I1-16/+17
No functional change. Get device pointer at the beginning of dw_pcie_host_init() instead of getting it all over dw_pcie_host_init(). This is in preparation for splitting struct pcie_port into host and core structures (once split pcie_port will not have device pointer). Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-21PCI: dwc: all: Rename cfg_read/cfg_write to read/writeKishon Vijay Abraham I7-33/+33
No functional change. dw_pcie_cfg_read()/dw_pcie_cfg_write() doesn't do anything specific to access configuration space. It can be just renamed to dw_pcie_read()/dw_pcie_write() and used to read/write data to dbi space. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-By: Joao Pinto <[email protected]> CC: Jingoo Han <[email protected]> CC: Murali Karicheri <[email protected]> CC: Stanimir Varbanov <[email protected]> CC: Pratyush Anand <[email protected]>
2017-02-21PCI: dwc: all: Use platform_set_drvdata() to save private dataKishon Vijay Abraham I11-4/+22
Add platform_set_drvdata() in all designware-based drivers to store the private data structure of the driver so that dev_set_drvdata() can be used to get back private data structure in add_pcie_port/host_init. This is in preparation for splitting struct pcie_port into core and host only structures. After the split pcie_port will not be part of the driver's private data structure and *container_of* used now to get the private data pointer cannot be used. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> CC: Jingoo Han <[email protected]> CC: Richard Zhu <[email protected]> CC: Lucas Stach <[email protected]> CC: Murali Karicheri <[email protected]> CC: Minghuan Lian <[email protected]> CC: Mingkai Hu <[email protected]> CC: Roy Zang <[email protected]> CC: Thomas Petazzoni <[email protected]> CC: Niklas Cassel <[email protected]> CC: Jesper Nilsson <[email protected]> CC: Joao Pinto <[email protected]> CC: Zhou Wang <[email protected]> CC: Gabriele Paoloni <[email protected]> CC: Stanimir Varbanov <[email protected]> CC: Pratyush Anand <[email protected]>
2017-02-21PCI: dwc: designware: Move register defines to designware header fileKishon Vijay Abraham I2-70/+71
No functional change. Move the register defines and other macros from pcie-designware.c to pcie-designware.h. This is in preparation to split the pcie-designware.c file into designware core file and host-specific file. While at that also fix a checkpatch warning. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-By: Joao Pinto <[email protected]>
2017-02-21PCI: dwc: Use PTR_ERR_OR_ZERO to simplify codeFengguang Wu1-12/+3
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR to avoid the following warnings found by scripts/coccinelle/api/ptr_ret.cocci: drivers/pci/dwc/pcie-qcom.c:215:1-3: WARNING: PTR_ERR_OR_ZERO can be used drivers/pci/dwc/pcie-qcom.c:247:1-3: WARNING: PTR_ERR_OR_ZERO can be used drivers/pci/dwc/pcie-qcom.c:481:1-3: WARNING: PTR_ERR_OR_ZERO can be used Signed-off-by: Fengguang Wu <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> CC: Kishon Vijay Abraham I <[email protected]>
2017-02-21PCI: dra7xx: Group PHY API invocationsKishon Vijay Abraham I1-41/+51
No functional change. PHY APIs like phy_init()/phy_power_on() are invoked from multiple places. Group all the PHY APIs in dra7xx_pcie_enable_phy() and dra7xx_pcie_disable_phy() and use these functions for enabling or disabling the PHY. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-21PCI: dra7xx: Enable MSI and legacy interrupts simultaneouslyKishon Vijay Abraham I1-19/+13
pci-dra7xx driver had a bug in that if CONFIG_PCI_MSI config is enabled, it doesn't support legacy interrupt. Fix it here so that both MSI and legacy interrupts can be enabled simultaneously and the interrupt mechanism supported by the endpoint device will be used. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-21PCI: dra7xx: Add support to force RC to work in GEN1 modeKishon Vijay Abraham I1-0/+29
PCIe in AM57x/DRA7x devices is by default configured to work in GEN2 mode. However there may be situations when working in GEN1 mode is desired. One example is limitation i925 (PCIe GEN2 mode not supported at junction temperatures < 0C). Add support to force Root Complex to work in GEN1 mode if so desired, but don't force GEN1 mode on any board just yet. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-21PCI: dra7xx: Simplify probe code with devm_gpiod_get_optional()Kishon Vijay Abraham I1-16/+5
No functional change. Use the new devm_gpiod_get_optional() to simplify the probe code. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-21PCI: Move DesignWare IP support to new drivers/pci/dwc/ directoryKishon Vijay Abraham I22-136/+155
Group all the PCI drivers that use DesignWare core in dwc directory. dwc IP is capable of operating in both host mode and device mode and keeping it inside the *host* directory is misleading. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Jingoo Han <[email protected]> Acked-By: Joao Pinto <[email protected]> Cc: Thomas Petazzoni <[email protected]> Cc: Minghuan Lian <[email protected]> Cc: Mingkai Hu <[email protected]> Cc: Roy Zang <[email protected]> Cc: Richard Zhu <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Pratyush Anand <[email protected]> Cc: Niklas Cassel <[email protected]> Cc: Jesper Nilsson <[email protected]> Cc: Zhou Wang <[email protected]> Cc: Gabriele Paoloni <[email protected]> Cc: Stanimir Varbanov <[email protected]>
2017-02-21Merge branch 'for-linus' into pci/host-designwareBjorn Helgaas1-5/+5
* for-linus: PCI: designware: Check for iATU unroll only on platforms that use ATU
2017-02-21PCI: exynos: Support the PHY generic frameworkJaehoon Chung1-4/+50
Switch the pci-exynos driver to generic PHY framework. At the same time backward compatibility is preserved: Warning will be printed for old DTB. Refer to the binding file: - Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt Signed-off-by: Jaehoon Chung <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Pankaj Dubey <[email protected]> Reviewed-by: Alim Akhtar <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Acked-by: Jingoo Han <[email protected]>
2017-02-21Documentation: binding: Modify the exynos5440 PCIe bindingJaehoon Chung1-0/+29
According to using PHY framework, updates the exynos5440-pcie binding. For maintaining backward compatibility, leaves the current dt-binding. (It should be deprecated.) Recommends to use the PHY Framework and "config" property to follow the designware-pcie binding. If you use the old way, can see "missing *config* reg space" message. Because the getting configuration space address from range is old way. NOTE: When use the "config" property, first name of 'reg-names' must be set to "elbi". Otherwise driver can't maintain the backward capability. Signed-off-by: Jaehoon Chung <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Pankaj Dubey <[email protected]> Reviewed-by: Alim Akhtar <[email protected]> Acked-by: Rob Herring <[email protected]>
2017-02-21phy: phy-exynos-pcie: Add support for Exynos PCIe PHYJaehoon Chung3-0/+294
Add support for Generic PHY framework about Exynos SoCs. Current Exynos PCIe driver doesn't use the PHY framework, which makes it difficult to upstream the other Exynos variants because of different PHY registers. Move the codes relevant to PHY from Exnyos PCIe driver to PHY Exynos PCIe driver. [bhelgaas: depend on "OF && (ARCH_EXYNOS || COMPILE_TEST)", update copyright year, both per Vivek] Signed-off-by: Jaehoon Chung <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Jingoo Han <[email protected]> Reviewed-by: Pankaj Dubey <[email protected]> Reviewed-by: Vivek Gautam <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-21Documentation: samsung-phy: Add exynos-pcie-phy bindingJaehoon Chung1-0/+17
Add the exynos-pcie-phy binding for Exynos PCIe PHY. This is for using generic PHY framework. Signed-off-by: Jaehoon Chung <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Rob Herring <[email protected]>
2017-02-17PCI: altera: Extract TLP completion status correctlyYadi Hu1-1/+1
Previously we extracted 'Completion Status' from b14:12, but it is actually b15:13. Extract it from the correct bits. Signed-off-by: Hu Yadi<[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Ley Foon Tan <[email protected]>
2017-02-17PCI: rockchip: Set vendor ID from local core config spaceShawn Lin1-2/+2
The TRM says the vendor ID in the RC's configure space can be rewritten and the value must be the same as the value read from the local core configure space. But we misread that and didn't notice it before. Actually we should only able to rewrite it from the local core configure space. Fix that issue to make lspci show the correct IP vendor infomation. Signed-off-by: Shawn Lin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-17PCI: hv: Use device serial number as PCI domainHaiyang Zhang1-0/+12
Use the device serial number as the PCI domain. The serial numbers start with 1 and are unique within a VM. So names, such as VF NIC names, that include domain number as part of the name, can be shorter than that based on part of bus UUID previously. The new names will also stay same for VMs created with copied VHD and same number of devices. Signed-off-by: Haiyang Zhang <[email protected]> Signed-off-by: Stephen Hemminger <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: K. Y. Srinivasan <[email protected]>
2017-02-15Merge branch 'pci/vpd' into nextBjorn Helgaas1-1/+1
* pci/vpd: PCI: Increase VPD access timeout to 125ms
2017-02-15Merge branch 'pci/virtualization' into nextBjorn Helgaas4-19/+41
* pci/virtualization: PCI: Lock each enable/disable num_vfs operation in sysfs PCI: Add ACS quirk for Intel Union Point
2017-02-15Merge branch 'pci/resource' into nextBjorn Helgaas1-10/+1
* pci/resource: PCI: Remove res_to_dev_res() debug message
2017-02-15Merge branch 'pci/msi' into nextBjorn Helgaas12-378/+136
* pci/msi: PCI/MSI: Update MSI/MSI-X bits in PCIEBUS-HOWTO PCI/MSI: Document pci_alloc_irq_vectors(), deprecate pci_enable_msi() PCI/MSI: Return -ENOSPC if pci_enable_msi_range() can't get enough vectors PCI/portdrv: Use pci_irq_alloc_vectors() PCI/MSI: Check that we have a legacy interrupt line before using it PCI/MSI: Remove pci_msi_domain_{alloc,free}_irqs() PCI/MSI: Remove unused pci_msi_create_default_irq_domain() PCI/MSI: Return failure when msix_setup_entries() fails PCI/MSI: Remove pci_enable_msi_{exact,range}() amd-xgbe: Update PCI support to use new IRQ functions [media] cobalt: use pci_irq_allocate_vectors() PCI/MSI: Fix msi_capability_init() kernel-doc warnings
2017-02-15Merge branch 'pci/hotplug' into nextBjorn Helgaas2-4/+2
* pci/hotplug: PCI: acpiphp_ibm: Make ibm_apci_table_attr __ro_after_init PCI: rpadlpar: Remove unnecessary return statement
2017-02-15Merge branch 'pci/enumeration' into nextBjorn Helgaas4-8/+35
* pci/enumeration: PCI: Remove duplicate check for positive return value from probe() functions PCI: Enable PCIe Extended Tags if supported PCI: Avoid possible deadlock on pci_lock and p->pi_lock PCI/ACPI: Fix bus range comparison in pci_mcfg_lookup() PCI: Apply _HPX settings only to relevant devices
2017-02-15Merge branch 'pci/dpc' into nextBjorn Helgaas2-3/+32
* pci/dpc: PCI/DPC: Wait for Root Port busy to clear PCI/DPC: Decode extended reasons
2017-02-15Merge branch 'pci/aspm' into nextBjorn Helgaas3-13/+302
* pci/aspm: PCI/ASPM: Add comment about L1 substate latency PCI/ASPM: Configure L1 substate settings PCI/ASPM: Calculate and save the L1.2 timing parameters PCI/ASPM: Read and set up L1 substate capabilities PCI/ASPM: Add support for L1 substates PCI/ASPM: Add L1 substate capability structure register definitions
2017-02-15Merge branch 'pci/aer' into nextBjorn Helgaas6-50/+3
* pci/aer: PCI/AER: Remove unused .link_reset() callback
2017-02-15PCI/MSI: Update MSI/MSI-X bits in PCIEBUS-HOWTOChristoph Hellwig1-26/+7
Update the MSI/MSI-X bits in PCIEBUS-HOWTO. Stop talking about low-level details that mention deprecated APIs and concentrate on what service drivers should do and why. Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-15PCI/MSI: Document pci_alloc_irq_vectors(), deprecate pci_enable_msi()Christoph Hellwig1-12/+12
Document pci_alloc_irq_vectors() instead of the deprecated pci_enable_msi() and pci_enable_msix() APIs. Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-14PCI/ASPM: Add comment about L1 substate latencyRajat Jain1-0/+8
Since the exit latencies for L1 substates are not advertised by a device, it is not clear in spec how to do a L1 substate exit latency check. We assume that the L1 exit latencies advertised by a device include L1 substate latencies (and hence do not do any check). If that is not true, we should do some sort of check here. (I'm not clear about what that check should like currently. I'd be glad to take up any suggestions). Signed-off-by: Rajat Jain <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
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