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2017-02-14PCI/ASPM: Configure L1 substate settingsRajat Jain1-2/+104
Configure the L1 substate settings on the upstream and downstream devices, while taking care of the rules dictated by the PCIe spec. [bhelgaas: drop "inline"] Signed-off-by: Rajat Jain <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-14PCI/ASPM: Calculate and save the L1.2 timing parametersRajat Jain1-0/+79
Calculate and save the timing parameters that need to be programmed if we need to enable L1.2 substates later. We use the same logic (and a constant value for 1 of the parameters) as used by Intel's coreboot: https://www.coreboot.org/pipermail/coreboot-gerrit/2015-March/021134.html https://review.coreboot.org/#/c/8832/ Signed-off-by: Rajat Jain <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-14PCI/ASPM: Read and set up L1 substate capabilitiesRajat Jain1-1/+58
The PCIe spec (r3.1, sec 7.33) says the L1 PM Substates Capability may be implemented only in function 0. Read the L1 substate capability structures of upstream and downstream components of the link and set it up in the device structure. [bhelgaas: add specific spec reference] Signed-off-by: Rajat Jain <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-14PCI/ASPM: Add support for L1 substatesRajat Jain2-10/+37
Add support for ASPM L1 substates. For details about L1 substates, see the PCIe r3.1 spec, which includes the ECN below in secs 5.5 and 7.33. Add macros for the 4 new L1 substates, and add a new ASPM "POWER_SUPERSAVE" policy that can be used to enable L1 substates on a system if desired. The new policy is in a sense, a superset of the existing POWERSAVE policy. The 4 policies are now: DEFAULT: Reads and uses whatever ASPM states BIOS enabled PERFORMANCE: Everything except L0 disabled. POWERSAVE: L0s and L1 enabled (but not L1 substates) POWER_SUPERSAVE: L0s + L1 + L1 substates also enabled [bhelgaas: add PCIe r3.1 spec reference] Link: https://pcisig.com/sites/default/files/specification_documents/ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf Signed-off-by: Rajat Jain <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-10PCI/ASPM: Add L1 substate capability structure register definitionsRajat Jain1-0/+16
Add L1 substate capability structure register definitions for use in subsequent patches. See the PCIe r3.1 spec, sec 7.33. [bhelgaas: add PCIe spec reference] Signed-off-by: Rajat Jain <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-10PCI: exynos: Refactor to make it easier to support other SoCsNiyas Ahmed S T1-129/+217
Currently the Exynos PCIe driver only supports the Exynos5440 SoC. Refactor the driver to allow support for other Exynos SoC. Following are the main changes in this patch: 1) Add separate structs for memory, clock resources Future Exynos SoC will have different hardware resources such as iomem, clocks, regmap handles, etc., so keeping these resources in separate structs will let us initialize them via per-SoC ops and avoid littering the code with of_machine_is_compatible(). 2) Add exynos_pcie_ops struct which will allow us to support the differences in resources in different Exynos SoC. No functional change intended. Signed-off-by: Niyas Ahmed S T <[email protected]> Signed-off-by: Pankaj Dubey <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Bartlomiej Zolnierkiewicz <[email protected]> Reviewed-by: Alim Akhtar <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Acked-by: Jingoo Han <[email protected]>
2017-02-10PCI/MSI: Return -ENOSPC if pci_enable_msi_range() can't get enough vectorsDennis Chen1-1/+1
If device doesn't support as many MSI vectors as the driver requested, we previously returned -EINVAL from __pci_enable_msi_range() and pci_enable_msi_range(). In other similar situations in both __pci_enable_msi_range() and __pci_enable_msix_range(), we returned -ENOSPC. Return -ENOSPC from __pci_enable_msi_range() so we do it consistently. [bhelgaas: changelog] Signed-off-by: Dennis Chen <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> CC: Tejun Heo <[email protected]> CC: Christoph Hellwig <[email protected]> CC: Tom Long Nguyen <[email protected]> CC: Greg Kroah-Hartman <[email protected]> CC: Marc Zyngier <[email protected]> CC: Lorenzo Pieralisi <[email protected]> CC: Steve Capper <[email protected]>
2017-02-10PCI/portdrv: Use pci_irq_alloc_vectors()Christoph Hellwig1-113/+48
Use pci_irq_alloc_vectors() and greatly simplify the code by managing the vector number for the subservices directly. Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-10PCI/MSI: Check that we have a legacy interrupt line before using itChristoph Hellwig1-3/+5
It seems like there are some devices (e.g. the PCIe root port driver) that may not always have a INTx interrupt. Check for dev->irq before returning a legacy interrupt in pci_irq_alloc_vectors to properly handle this case. Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-10PCI: rockchip: Fix rockchip_pcie_probe() error path to free resource listShawn Lin1-4/+6
rockchip_pcie_probe() calls of_pci_get_host_bridge_resources() to parse resources from DT and build a resource list. The caller is responsible for disposing of the resource list. This is normally done by pci_release_host_bridge_dev() when the host bridge is removed. If the host bridge probe fails, dispose of the resource list in the probe error path. [bhelgaas: changelog] Suggested-by: Bjorn Helgaas <[email protected]> Signed-off-by: Shawn Lin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-10PCI: imx6: Fix a typo in error messageAndrey Smirnov1-2/+1
Fix a typo in the "pcie_inbound_axi clock missing or invalid" error message. Signed-off-by: Andrey Smirnov <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Lucas Stach <[email protected]> CC: [email protected] CC: Fabio Estevam <[email protected]>
2017-02-10PCI: hv: Fix wslot_to_devfn() to fix warnings on device removalDexuan Cui1-3/+5
The devfn of 00:02.0 is 0x10. devfn_to_wslot(0x10) == 0x2, and wslot_to_devfn(0x2) should be 0x10, while it's 0x2 in the current code. Due to this, hv_eject_device_work() -> pci_get_domain_bus_and_slot() returns NULL and pci_stop_and_remove_bus_device() is not called. Later when the real device driver's .remove() is invoked by hv_pci_remove() -> pci_stop_root_bus(), some warnings can be noticed because the VM has lost the access to the underlying device at that time. Signed-off-by: Jake Oshins <[email protected]> Signed-off-by: Dexuan Cui <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Haiyang Zhang <[email protected]> CC: [email protected] CC: K. Y. Srinivasan <[email protected]> CC: Stephen Hemminger <[email protected]>
2017-02-10PCI: Remove duplicate check for positive return value from probe() functionsGabriel Krisman Bertazi1-2/+0
Function __pci_device_probe() tries to be careful about a PCI driver probe() hook returning a positive value, but this is not really necessary, since the same fix up is already done in local_pci_probe() (preceded by a noisy warning), which renders this instance dead code. Signed-off-by: Gabriel Krisman Bertazi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-10PCI/DPC: Wait for Root Port busy to clearKeith Busch2-1/+26
Per PCIe r3.1, sec 6.2.10 and sec 7.13.4, on Root Ports that support "RP Extensions for DPC", When the DPC Trigger Status bit is Set and the DPC RP Busy bit is Set, software must leave the Root Port in DPC until the DPC RP Busy bit reads 0b. Wait up to 1 second for the Root Port to become non-busy. [bhelgaas: changelog, spec references] Signed-off-by: Keith Busch <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-10PCI/DPC: Decode extended reasonsKeith Busch1-2/+6
Decode the currently defined extended event reasons rather than just using the generic "extended" explanation. Signed-off-by: Keith Busch <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-10PCI/MSI: Remove pci_msi_domain_{alloc,free}_irqs()Christoph Hellwig3-32/+3
Just call the msi_* version directly instead of having trivial wrappers for one or two callsites. Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Thomas Gleixner <[email protected]>
2017-02-10PCI/MSI: Remove unused pci_msi_create_default_irq_domain()Christoph Hellwig2-51/+2
pci_msi_create_default_irq_domain() is never called in the whole tree, so remove it as well as all the supporting code for a default PCI MSI domain. Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Thomas Gleixner <[email protected]>
2017-02-10PCI/MSI: Return failure when msix_setup_entries() failsChristophe JAILLET1-1/+1
If alloc_msi_entry() fails, we free resources and set ret = -ENOMEM. However, msix_setup_entries() returns 0 unconditionally. Return the error code instead. Fixes: e75eafb9b039 ("genirq/msi: Switch to new irq spreading infrastructure") Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-10PCI: xgene: Configure PCIe MPS settingsBjorn Helgaas1-1/+3
Make sure PCIe MPS settings are valid when we enumerate a new hierarchy. Based-on-patch-by: Jon Mason <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-09PCI: Enable PCIe Extended Tags if supportedSinan Kaya1-0/+18
Every PCIe device can generate 5-bit transaction Tags, which allow up to 32 concurrent requests. Some devices can generate 8-bit Extended Tags, which allow up to 256 concurrent requests. Per the ECN mentioned below, all PCIe Receivers are expected to support Extended Tags, so devices are allowed (but not required) to enable them by default. If a device supports Extended Tags but does not enable them by default, enable them. This allows the device to have up to 256 outstanding transactions at a time, which may improve performance. [bhelgaas: changelog, check for PCIe device] Link: https://pcisig.com/sites/default/files/specification_documents/ECN_Extended_Tag_Enable_Default_05Sept2008_final.pdf Signed-off-by: Sinan Kaya <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-09PCI/AER: Remove unused .link_reset() callbackMichael S. Tsirkin6-50/+3
No hardware seems to actually call .link_reset(), and no driver implements it as more than a nop stub. Drop mentions of the callback from everywhere. It's dropped from the documentation as well, but the doc really needs to be updated to reflect reality better (e.g., on PCIe, slot reset is the link reset). This will be done in a later patch. Signed-off-by: Michael S. Tsirkin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-09PCI: generic: Call pci_fixup_irqs() only on ARMDongdong Liu1-0/+2
pci_fixup_irqs() is problematic because: - it's called when we enumerate a host bridge, so we don't fixup IRQs for hot-added PCI devices, and - it fixes up IRQs for all PCI devices in the system, so if we call it multiple times, e.g., if we have several host controllers, we may reallocate an IRQ for a device after a driver has already claimed it. We plan to replace pci_fixup_irqs() soon, but we still need it on ARM because we don't have any other generic method for doing this. On ARM64, we don't need pci_fixup_irqs() because we do IRQ setup when we bind a driver to the device (in the pci_device_probe() -> pcibios_alloc_irq() path). pci-host-common.c is currently only used on ARM and ARM64. In principle, it could be used on x86, and we wouldn't want pci_fixup_irqs() there either, because x86 does IRQ setup in the pci_enable_device() path. [bhelgaas: changelog, use #ifdef ARM, not #ifndef ARM64] Signed-off-by: Dongdong Liu <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Gabriele Paoloni <[email protected]> Reviewed-by: Zhou Wang <[email protected]> Acked-by: Lorenzo Pieralisi <[email protected]>
2017-02-09PCI: Disable MSI for HiSilicon Hip06/Hip07 Root PortsDongdong Liu2-0/+3
The PCIe Root Port in Hip06/Hip07 SoCs advertises an MSI capability, but it cannot generate MSIs. It can transfer MSI/MSI-X from downstream devices, but does not support MSI/MSI-X itself. Add a quirk to prevent use of MSI/MSI-X by the Root Port. [bhelgaas: changelog, sort vendor ID #define, drop device ID #define] Signed-off-by: Dongdong Liu <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Gabriele Paoloni <[email protected]> Reviewed-by: Zhou Wang <[email protected]>
2017-02-09PCI: hisi: Rename config space accessors to remove "acpi"Bjorn Helgaas1-8/+8
There's nothing ACPI-specific about the config space accessors hisi_pcie_acpi_rd_conf() and hisi_pcie_acpi_wr_conf(), and they're used for both the ACPI and the DT driver model. Rename them to hisi_pcie_rd_conf() and hisi_pcie_wr_conf(). No functional change intended. Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-08PCI: Add Broadcom Northstar2 PAXC quirk for device class and MPSSJon Mason1-0/+21
The Broadcom Northstar2 SoC has a number of quirks for the PAXC (internal/fake) PCI bus. Specifically, the PCI config space is shared between the root port and the first PF (ie., PF0), and a number of fields are tied to zero (thus preventing them from being set). These cannot be "fixed" in device firmware, so we must fix them with a quirk. Signed-off-by: Jon Mason <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-08PCI: versatile: Configure PCIe MPS settingsBjorn Helgaas1-1/+3
Make sure PCIe MPS settings are valid when we enumerate a new hierarchy. Based-on-patch-by: Jon Mason <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-08PCI: iproc: Configure PCIe MPS settingsJon Mason1-1/+4
Make sure PCIe MPS settings are valid when we enumerate a new hierarchy. [bhelgaas: changelog] Signed-off-by: Jon Mason <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Ray Jui <[email protected]>
2017-02-08PCI: exynos: Remove duplicated codeJaehoon Chung1-14/+8
Remove duplicated register reads and writes. Signed-off-by: Jaehoon Chung <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Pankaj Dubey <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Acked-by: Jingoo Han <[email protected]>
2017-02-08PCI: exynos: Use the bitops BIT() macro to build bitmasksJaehoon Chung1-12/+12
Use the bitops BIT() macro to build bitmasks. Signed-off-by: Jaehoon Chung <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Pankaj Dubey <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Acked-by: Jingoo Han <[email protected]>
2017-02-08PCI: exynos: Remove unnecessary local variablesJaehoon Chung1-9/+7
Remove unnecessary local variables: elbi_base, phy_base, block_base. We need one resource structure for assigning each resource. Reuse the single 'res' variable for all. Signed-off-by: Jaehoon Chung <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Pankaj Dubey <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Acked-by: Jingoo Han <[email protected]>
2017-02-08PCI: exynos: Replace the *_blk/*_phy/*_elb accessorsJaehoon Chung1-102/+82
There is no reason to maintain *_blk/phy/elbi_* as register accessors. They can be replaced by one accessor to make maintenance easier. Signed-off-by: Jaehoon Chung <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Pankaj Dubey <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Acked-by: Jingoo Han <[email protected]>
2017-02-08PCI: mvebu: Change delay after reset to the PCIe spec mandated 100msLucas Stach2-2/+3
The current default of 20ms cause some devices, which are slow to initialize, to not show up during the bus scanning. Change this to the PCIe spec mandated 100ms and document this in the DT binding. From PCIe base spec rev 3.0, chapter "6.6.1. Conventional Reset": To allow components to perform internal initialization, system software must wait a specified minimum period following the end of a Conventional Reset of one or more devices before it is permitted to issue Configuration Requests to those devices. With a Downstream Port that does not support Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms before sending a Configuration Request to the device immediately below that Port. Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Jason Cooper <[email protected]>
2017-02-06PCI: hisi: Add DT almost-ECAM support for Hip06/Hip07 host controllersDongdong Liu2-1/+98
The PCIe controller in HiSilicon Hip06/Hip07 SoCs is not completely ECAM-compliant. It is non-ECAM only for the RC bus config space; for any other bus underneath the root bus it does support ECAM access. Add DT support for the almost-ECAM Hip06/Hip07 controllers. [bhelgaas: drop dev->of_node test, driver name "hisi-pcie-almost-ecam"] Signed-off-by: Dongdong Liu <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Gabriele Paoloni <[email protected]> Reviewed-by: Zhou Wang <[email protected]>
2017-02-03PCI: hisi: Use of_device_get_match_data() to simplify probeShailendra Verma1-5/+3
The only way to call hisi_pcie_probe() is to match an entry in hisi_pcie_of_match[], so match cannot be NULL. Use of_device_get_match_data() to retrieve the soc_ops pointer. No functional change intended. [bhelgaas: use of_device_get_match_data(), changelog] Based-on-suggestion-from: Geert Uytterhoeven <[email protected]> Signed-off-by: Shailendra Verma <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-02-03PCI: Lock each enable/disable num_vfs operation in sysfsEmil Tantilov3-15/+17
Enabling/disabling SRIOV via sysfs by echo-ing multiple values simultaneously: # echo 63 > /sys/class/net/ethX/device/sriov_numvfs& # echo 63 > /sys/class/net/ethX/device/sriov_numvfs # sleep 5 # echo 0 > /sys/class/net/ethX/device/sriov_numvfs& # echo 0 > /sys/class/net/ethX/device/sriov_numvfs results in the following bug: kernel BUG at drivers/pci/iov.c:495! invalid opcode: 0000 [#1] SMP CPU: 1 PID: 8050 Comm: bash Tainted: G W 4.9.0-rc7-net-next #2092 RIP: 0010:[<ffffffff813b1647>] [<ffffffff813b1647>] pci_iov_release+0x57/0x60 Call Trace: [<ffffffff81391726>] pci_release_dev+0x26/0x70 [<ffffffff8155be6e>] device_release+0x3e/0xb0 [<ffffffff81365ee7>] kobject_cleanup+0x67/0x180 [<ffffffff81365d9d>] kobject_put+0x2d/0x60 [<ffffffff8155bc27>] put_device+0x17/0x20 [<ffffffff8139c08a>] pci_dev_put+0x1a/0x20 [<ffffffff8139cb6b>] pci_get_dev_by_id+0x5b/0x90 [<ffffffff8139cca5>] pci_get_subsys+0x35/0x40 [<ffffffff8139ccc8>] pci_get_device+0x18/0x20 [<ffffffff8139ccfb>] pci_get_domain_bus_and_slot+0x2b/0x60 [<ffffffff813b09e7>] pci_iov_remove_virtfn+0x57/0x180 [<ffffffff813b0b95>] pci_disable_sriov+0x65/0x140 [<ffffffffa00a1af7>] ixgbe_disable_sriov+0xc7/0x1d0 [ixgbe] [<ffffffffa00a1e9d>] ixgbe_pci_sriov_configure+0x3d/0x170 [ixgbe] [<ffffffff8139d28c>] sriov_numvfs_store+0xdc/0x130 ... RIP [<ffffffff813b1647>] pci_iov_release+0x57/0x60 Use the existing mutex lock to protect each enable/disable operation. Signed-off-by: Emil Tantilov <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Gavin Shan <[email protected]> CC: Alexander Duyck <[email protected]>
2017-02-03PCI: Increase VPD access timeout to 125msMatthew R. Ochs1-1/+1
The PCI core uses a fixed 50ms timeout when waiting for VPD accesses to complete. When an access does not complete within this period, a warning is logged and an error returned to the caller. While this default timeout is valid for most hardware, some devices can experience longer access delays under certain circumstances. For example, one of the IBM CXL Flash devices can take up to ~120ms in a worst-case scenario. These types of devices can benefit from an extended timeout. To support devices with a longer access delay, increase the timeout in pci_vpd_wait() to 125ms. The PCI specification is silent with respect to VPD delays, therefore there is no concern for violating a threshold. Tested-by: Uma Krishnan <[email protected]> Signed-off-by: Matthew R. Ochs <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Gavin Shan <[email protected]>
2017-01-31PCI: iproc: Use of_device_get_match_data() to simplify probeBjorn Helgaas1-6/+1
The only way to call iproc_pcie_pltfm_probe() is to match an entry in iproc_pcie_of_match_table[], so match cannot be NULL. Use of_device_get_match_data() to retrieve the pcie->type. No functional change intended. Based-on-suggestion-from: Geert Uytterhoeven <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-01-31PCI: layerscape: Use of_device_get_match_data() to simplify probeBjorn Helgaas1-6/+1
The only way to call ls_pcie_probe() is to match an entry in ls_pcie_of_match[], so match cannot be NULL. Use of_device_get_match_data() to retrieve the drvdata pointer. No functional change intended. Based-on-suggestion-from: Geert Uytterhoeven <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-01-31PCI: rcar: Use of_device_get_match_data() to simplify probeBjorn Helgaas1-6/+1
This is a DT-only driver, so the only way to call rcar_pcie_probe() is to match an entry in rcar_pcie_of_match[], so of_id cannot be NULL. Furthermore, of_id->data can only be NULL if an rcar_pcie_of_match[] entry has a NULL .data member. That's a driver defect, and we don't want to return -EINVAL, which is easy to ignore. We'd rather take the NULL pointer dereference so we notice the problem and fix it. Use of_device_get_match_data() to retrieve the hw_init_fn pointer. No functional change intended. Suggested-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Acked-by: Simon Horman <[email protected]>
2017-01-30PCI: xgene: Fix double free on init errorDan Carpenter1-5/+2
The "port" variable was allocated with devm_kzalloc() so if we free it with kfree() it will be freed twice. Also I changed it to propogate the error from devm_ioremap_resource() instead of returning -ENOMEM. Fixes: c5d460396100 ("PCI: Add MCFG quirks for X-Gene host controller") Also-posted-by: Shawn Lin <[email protected]> Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Tanmay Inamdar <[email protected]>
2017-01-30PCI: imx6: Remove LTSSM disable workaroundLucas Stach1-30/+0
This causes CPU hangs when the system is reset by the watchdog, as the GPRs aren't cleared, but the clocks are back to disabled state. If the bootloader uses PCIe, it must take care to bring it down into a safe state, before passing control to the Linux kernel. This is the only way to get a properly operating system at all times and circumstances. Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-01-30PCI: Avoid possible deadlock on pci_lock and p->pi_lockBjorn Helgaas1-1/+2
pci_lock is an IRQ-safe spinlock that protects all accesses to PCI configuration space (see PCI_OP_READ() and PCI_OP_WRITE() in pci/access.c). The pci_cfg_access_unlock() path acquires pci_lock, then p->pi_lock (inside wake_up_all()). According to lockdep, there is a possible path involving snbep_uncore_pci_read_counter() that could acquire them in the reverse order: acquiring p->pi_lock, then pci_lock, which could result in a deadlock. Lockdep details are in the bugzilla below. Avoid the possible deadlock by dropping pci_lock before waking up any config access waiters. Link: https://bugzilla.kernel.org/show_bug.cgi?id=192901 Signed-off-by: Bjorn Helgaas <[email protected]>
2017-01-30PCI: rockchip: Mark PM functions as __maybe_unusedArnd Bergmann1-2/+2
When CONFIG_PM_SLEEP is disabled, we get harmless build warnings: host/pcie-rockchip.c:1267:12: error: 'rockchip_pcie_resume_noirq' defined but not used [-Werror=unused-function] host/pcie-rockchip.c:1240:12: error: 'rockchip_pcie_suspend_noirq' defined but not used [-Werror=unused-function] Marking both functions as __maybe_unused avoids the warning without the need for #ifdef around them. Fixes: 013dd3d5e183 ("PCI: rockchip: Add system PM support") Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Shawn Lin <[email protected]>
2017-01-30PCI: rockchip: Use readl_poll_timeout() instead of open-coding itShawn Lin1-36/+16
Use readl_poll_timeout() instead of open-coding it. Signed-off-by: Shawn Lin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-01-30PCI: mvebu: Handle changes to the bridge windows while enabledJason Gunthorpe1-41/+60
The PCI core will write to the bridge window config multiple times while they are enabled. This can lead to mbus failures like this: mvebu_mbus: cannot add window '4:e8', conflicts with another window mvebu-pcie mbus:pex@e0000000: Could not create MBus window at [mem 0xe0000000-0xe00fffff]: -22 For me this is happening during a hotplug cycle. The PCI core is not changing the values, just writing them twice while active. The patch addresses the general case of any change to an active window, but not atomically. The code is slightly refactored so io and mem can share more of the window logic. Signed-off-by: Jason Gunthorpe <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Jason Cooper <[email protected]>
2017-01-28PCI: exynos: Rename all pointer names from "exynos_pcie" to "ep"Jaehoon Chung1-175/+173
Rename the simple pointer name as "ep" instead of "exynos_pcie". After applying this patch, it can save the 10 characthers within one line. Signed-off-by: Jaehoon Chung <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Pankaj Dubey <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Acked-by: Jingoo Han <[email protected]>
2017-01-28PCI: Add ACS quirk for Intel Union PointAlex Williamson1-4/+24
Intel 200-series chipsets have the same errata as 100-series: the ACS capability doesn't follow the PCIe spec, the capability and control registers are dwords rather than words. Add PCIe root port device IDs to existing quirk. Signed-off-by: Alex Williamson <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-01-13PCI/MSI: Remove pci_enable_msi_{exact,range}()Christoph Hellwig3-35/+13
All multi-MSI allocations are now done through pci_irq_alloc_vectors(), so remove the old pci_enable_msi_range() and pci_enable_msi_exact() interfaces. Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-01-13amd-xgbe: Update PCI support to use new IRQ functionsTom Lendacky2-95/+41
Some of the PCI MSI/MSI-X functions have been deprecated and it is recommended to use the new pci_alloc_irq_vectors() function. Convert the code over to use the new function. Also, modify the way in which the IRQs are requested - try for multiple MSI-X/MSI first, then a single MSI/legacy interrupt. Signed-off-by: Tom Lendacky <[email protected]> Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-01-13[media] cobalt: use pci_irq_allocate_vectors()Christoph Hellwig2-8/+2
Simplify the interrupt setup by using the new PCI layer helpers. Despite using pci_enable_msi_range(), this driver was only requesting a single MSI vector anyway. Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
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