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2018-10-09drm/amdgpu: Refine uvd_v6/7_0_enc_get_destroy_msgRex Zhu2-15/+7
1. make uvd_v7_0_enc_get_destroy_msg static 2. drop a function variable that always true Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/display: Signal hw_done() after waiting for flip_done()Shirish S1-2/+8
In amdgpu_dm_commit_tail(), wait until flip_done() is signaled before we signal hw_done(). [Why] This is to temporarily address a paging error that occurs when a nonblocking commit contends with another commit, particularly in a mirrored display configuration where at least 2 CRTCs are updated. The error occurs in drm_atomic_helper_wait_for_flip_done(), when we attempt to access the contents of new_crtc_state->commit. Here's the sequence for a mirrored 2 display setup (irrelevant steps left out for clarity): **THREAD 1** | **THREAD 2** | Initialize atomic state for flip | | Queue worker | ... | Do work for flip | | Signal hw_done() on CRTC 1 | Signal hw_done() on CRTC 2 | | Wait for flip_done() on CRTC 1 <---- **PREEMPTED BY THREAD 1** Initialize atomic state for cursor | update (1) | | Do cursor update work on both CRTCs | | Clear atomic state (2) | **DONE** | ... | | Wait for flip_done() on CRTC 2 | *ERROR* | The issue starts with (1). When the atomic state is initialized, the current CRTC states are duplicated to be the new_crtc_states, and referenced to be the old_crtc_states. (The new_crtc_states are to be filled with update data.) Some things to note: * Due to the mirrored configuration, the cursor updates on both CRTCs. * At this point, the pflip IRQ has already been handled, and flip_done signaled on all CRTCs. The cursor commit can therefore continue. * The old_crtc_states used by the cursor update are the **same states** as the new_crtc_states used by the flip worker. At (2), the old_crtc_state is freed (*), and the cursor commit completes. We then context switch back to the flip worker, where we attempt to access the new_crtc_state->commit object. This is problematic, as this state has already been freed. (*) Technically, 'state->crtcs[i].state' is freed, which was made to reference old_crtc_state in drm_atomic_helper_swap_state() [How] By moving hw_done() after wait_for_flip_done(), we're guaranteed that the new_crtc_state (from the flip worker's perspective) still exists. This is because any other commit will be blocked, waiting for the hw_done() signal. Note that both the i915 and imx drivers have this sequence flipped already, masking this problem. Signed-off-by: Shirish S <[email protected]> Signed-off-by: Leo Li <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/display: Use proper enums in process_channel_replyNathan Chancellor2-2/+2
Clang warns when one enumerated type is implicitly converted to another. drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.c:315:19: warning: implicit conversion from enumeration type 'enum aux_channel_operation_result' to different enumeration type 'enum aux_transaction_reply' [-Wenum-conversion] reply->status = AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON; ~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/i2caux/dce110/aux_engine_dce110.c:349:19: warning: implicit conversion from enumeration type 'enum aux_channel_operation_result' to different enumeration type 'enum aux_transaction_reply' [-Wenum-conversion] reply->status = AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON; ~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The current enum is incorrect, it should be from aux_transaction_reply, so use AUX_TRANSACTION_REPLY_HPD_DISCON. Reported-by: Nick Desaulniers <[email protected]> Suggested-by: Nick Desaulniers <[email protected]> Signed-off-by: Nathan Chancellor <[email protected]> Reviewed-by: Nick Desaulniers <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/display: Raise dispclk value for dce_update_clocksNicholas Kazlauskas1-0/+5
[Why] The DISPCLK value was previously requested to be 15% higher for all ASICS that went through the dce110 bandwidth code path. As part of a refactoring of dce_clocks and dce110 set_bandwidth this was removed for power saving considerations. This changed caused corruption under certain display configurations. Originally thought to be Vega specific, it was also observed on Polaris. [How] The 15% is brought back but its placement differs from the original patch. This boost should only be enable while DFS bypass is inactive. This (like the Vega patch) is also a workaround that should be removed after the root cause is identified. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/display: HLK Periodic Frame Notification test failedMurton Liu1-1/+1
[Why] Due to a small pre-fetch window, the active vline timing is a couple of lines off when compared to what it should be. [How] Changed the calculation for the start vline to account for this window. Signed-off-by: Murton Liu <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/display: fix Interlace video timing.Charlene Liu1-25/+7
[Description] interlace mode shows wrong vertical timing. Interface timing in Edid is half vertical timing as progressive timing. driver doubled the vertical timing in edid_paser, no need to double in optc again. Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Chris Park <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/display: Flatten irq handler data structLeo Li1-23/+14
[Why] There is no reason why the common data needs to be kept separate. [How] Flatten the struct by moving common data into the DM IRQ struct. Signed-off-by: Leo Li <[email protected]> Reviewed-by: David Francis <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/display: fix memory leak in resource poolsJun Lei6-3/+15
[why] ddc engines were recently changed to be independently tracked from pipe count. the change was reflected in resource constructor but not in destructor. this manifests as a memory leak when pipe harvesting is enabled, since not all constructed ddc engines are freed [how] make destructor symmetric with constructor for all dcX_resource Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/display: dc 3.1.68Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Steven Chiu <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/display: WA for DF keeps awake after S0i3.Yongqiang Sun3-0/+35
[Why] DF keeps awake after S0i3 resume due to DRAM_STATE_CNTL is set by bios command table during dcn init_hw. [How] As a work around, check STATE_CNTL status before init_hw, if it is 0 before init_hw and set to 1 after init_hw, change it to 0. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/display: clean up encoding checksEric Yang9-43/+7
[Why] All ASICS we support has YCbCr support, so the check is unnecessary, the currently logic in validate output also returns true all the time, so the unneccessary logic is removed Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/display: block DP YCbCr420 modesEric Yang2-0/+6
[why] Currently not supported, will black screen when set. [How] Fail validate timing helper for those modes. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/display: Add function to fetch clock requirementsEryk Brol3-1/+28
Also add dram clock to clocks struct, for systems that uses them. Signed-off-by: Eryk Brol <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/display: Calculate swizzle mode using bpp during validationSu Sung Chung6-30/+67
[Why] Previously bandwidth validation was failing because swizzle mode was not initialized during plane_state allocation. The swizzle mode was calculated using pixed format which is how swizzle mode is initially calculated in addrlib. [How] * Set default swizzle mode for validation to DC_SW_UNKNOWN * Created new function in dcn10_assign_swizzle_mode which sets the plane swizzle mode based on selected pixed format * Added the call of assign_swizzle_mode into dc_validate_global_state * Set failsafe swizzle mode back to DC_SW_LINEAR Signed-off-by: Su Sung Chung <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/display: Add a check-function for virtual signal typeNikola Cornij1-0/+5
[why] Same functions exist for all other signal types. [how] Add a function that checks against virtual signal type. Signed-off-by: Nikola Cornij <[email protected]> Reviewed-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/display: fix 4K stereo screen flash issueCharlene Liu1-0/+3
[Why] HDMI_scramber is not enabled for pixel rate >340Mhz. [How] Calculate the phy clock to include the Hw frame packing factor. Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Chris Park <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/display: Add DC build_id to determine build typeJun Lei2-0/+5
[why] Sometimes there are indications that the incorrect driver is being loaded in automated tests. This change adds the ability for builds to be tagged with a string, and picked up by the test infrastructure. [how] dc.c will allocate const for build id, which is init-ed with default value, indicating production build. For test builds, build server will find/replace this value. The test machine will then verify this value. Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/powerplay: Enable/Disable NBPSTATE on On/OFF of UVDAkshu Agrawal1-1/+4
We observe black lines (underflow) on display when playing a 4K video with UVD. On Disabling Low memory P state this issue is not seen. Multiple runs of power measurement shows no imapct. Signed-off-by: Akshu Agrawal <[email protected]> Signed-off-by: Satyajit Sahu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2018-10-09drm/amd/pp: Remove wrong code in fiji_start_smuRex Zhu1-10/+0
HW CG feature will be enabled after hw ip initialized Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/pp: Remove uncessary extra vcn pg cntl in smuRex Zhu1-15/+1
the vcn power will be controlled by VCN. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amdgpu: Move out power up/down sdma out of smuRex Zhu3-15/+7
smu only expose interface to other ip blocks. in order to reduce dependence between smu and other ip blocks Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/pp: Expose the smu support for SDMA PG cntlRex Zhu3-0/+27
SDMA IP can be power up/down via smu message Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/pp: Avoid divide-by-zero in fan_ctrl_set_fan_speed_rpmRex Zhu2-0/+2
The minRPM speed maybe equal to zero. so need to check input RPM not equal to 0, otherwise cause divide-by-zero driver crash. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/pp: Fix fan's RPM setting not work on VI/Vega10Rex Zhu2-4/+4
set the target rpm value to wrong register. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amdgpu: Fix comments error in sdma_v4_1_update_power_gatingRex Zhu1-1/+1
Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/powerplay: enable MGPU fan boost feature on Vega20Evan Quan1-0/+15
Added Vega20 specific implementation for MGPU fan boost feature. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/powerplay: helper interfaces for MGPU fan boost featureEvan Quan5-0/+66
MGPU fan boost feature is enabled only when two or more dGPUs in the system. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amdgpu: added AMD GPU instance counting V2Evan Quan3-0/+73
Count all GPU instances from AMD(including iGPUs and dGPUs) in the system. V2: drop unnecessary initialization for other gpu_info members except mutex Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amdgpu/vega20: make power profile output more consistentAlex Deucher1-1/+1
Make the profile name line match previous generations more closely. E.g., 0 3D_FULL_SCREEN : vs: 0(3D_FULL_SCREEN ) Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amdgpu: change Raven always on CUs to 4Evan Quan1-2/+6
For Vega10 and Vega20, the always on CUs are 12. For Raven, it's 4. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amdgpu: added vega20 LBPW support v2Evan Quan1-1/+104
Enable LBPW support on vega20. v2: squash in warning fix (Alex) Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/powerplay/vega20: enable fan RPM and pwm settings V2Evan Quan5-4/+207
Manual fan RPM and pwm setting on vega20 are available now. V2: correct the register for fan speed setting and avoid divide-by-zero Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/powerplay/vega20: tell the correct gfx voltage V2Evan Quan3-0/+18
Export the correct gfx voltage by hwmon interface. V2: update the register naming for consistency Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09drm/amd/powerplay/vega20: correct the hwmon interface ppt limit outputEvan Quan2-0/+14
The ppt limit read out by hwmon interface is always 0. Correct this hwmon interface output. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-10-09MAINTAINERS: Add Maxime Ripard as drm-misc maintainerSean Paul1-1/+1
Unfortunately Gustavo has decided to step down as drm-misc maintainer to focus on other projects. Thanks Gustavo for your dedication and hard work! Fortunately for us, we have a wealth of people qualified to assume a -misc maintainer role. Maxime has done an outstanding job with sun4i and in the community in general. I'm really excited that he agreed to take on this responsibility and I look forward to working with him! Cc: Dave Airlie <[email protected]> Cc: Gustavo Padovan <[email protected]> Cc: Maarten Lankhorst <[email protected]> Cc: Maxime Ripard <[email protected]> Acked-by: Maarten Lankhorst <[email protected]> Acked-by: Maxime Ripard <[email protected]> Acked-by: Dave Airlie <[email protected]> Signed-off-by: Sean Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-10-08drm/msm: a6xx: Fix improper u64 divisionSean Paul1-4/+7
This patch uses the proper do_div() macro to perform u64 division and guards against overflow if the result is too large for the unsigned long return type Fixes: a2c3c0a54d4c drm/msm/a6xx: Add devfreq support for a6xx Cc: Sharat Masetty <[email protected]> Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-10-08drm/msm: a5xx: Remove unneeded parensSean Paul1-2/+2
A small fixup I posted with my v2 patch [1] that was dropped. [1]- https://lists.freedesktop.org/archives/freedreno/2018-October/003647.html Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-10-08Merge branch 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld into ↵Dave Airlie1-1/+3
drm-next I've realised that the commit 3dae1c0919d8 ("drm/arm/malidp: Implemented the size validation for AFBC framebuffers") got bungled up in the upstreaming process and it was missing an important line from the function that calculates the size of the AFBC framebuffer Signed-off-by: Dave Airlie <[email protected]> From: Liviu Dudau <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-10-07drm/msm/a6xx: Remove CP perfcounter selects from the protected listJordan Crouse1-3/+1
The CP performance counter selects were accidentally marked as protected so they couldn't be written from PM4 streams. Remove the protection because user space does have an interest in setting up their own counters. Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-10-07drm/msm: dpu: Fix memory leak caused by dropped referenceSean Paul1-3/+1
We are currently leaking a drm_crtc_commit struct for every atomic commit containing plane state. The dpu plane destroy function cleans up the fb reference manually, but fails to release the commit ref. As a result, we just keep allocating drm_crtc_commits without ever freeing them. Fortunately there's a helper function which will clean up all of our mess at once, so use that. Thanks to Doug Anderson for reporting the memory leak (and leaving breadcrumbs from kmemleak!). Reported-by: Doug Anderson <[email protected]> Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-10-07drm/msm: a5xx: Fix improper u64 divisionSean Paul1-5/+7
This patch uses the proper do_div() macro to perform u64 division and guards against overflow if the result is too large for the unsigned long return type Fixes: de0a3d094de0 drm/msm: re-factor devfreq code Cc: Sharat Masetty <[email protected]> Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-10-07drm/msm: update generated headersRob Clark8-342/+1149
Signed-off-by: Rob Clark <[email protected]>
2018-10-05drm: malidp: Add the size of the superblocks when calculating totalLiviu Dudau1-1/+3
size for AFBC buffers The size of the superblocks being added to the total AFBC buffer size got lost in the upstreaming process. Add it back. Reviewed-by: Ayan Kumar Halder <[email protected]> Signed-off-by: Liviu Dudau <[email protected]>
2018-10-05drm/imx: fix build failure without CONFIG_DRM_FBDEV_EMULATIONArnd Bergmann1-2/+0
The variable is declared in an #ifdef section, but the user is now unconditional, which leads to a build failure: drivers/gpu/drm/imx/imx-drm-core.c: In function 'imx_drm_bind': drivers/gpu/drm/imx/imx-drm-core.c:264:6: error: 'legacyfb_depth' undeclared (first use in this function); did you mean 'lockdep_depth'? Remove the remaining #ifdef as well. Fixes: f53705fd9803 ("drm/imx: Use drm_fbdev_generic_setup()") Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Noralf Trønnes <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-10-04drm/msm/a6xx: Add devfreq support for a6xxSharat Masetty4-5/+67
Implement routines to estimate GPU busy time and fetching the current frequency for the polling interval. This is required by the devfreq framework which recommends a frequency change if needed. The driver code then tries to set this new frequency on the GPU by sending an Out Of Band(OOB) request to the GMU. Signed-off-by: Sharat Masetty <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-10-04drm/msm: re-factor devfreq codeSharat Masetty3-23/+41
The devfreq framework requires the drivers to provide busy time estimations. The GPU driver relies on the hardware performance counteres for the busy time estimations, but different hardware revisions have counters which can be sourced from different clocks. So the busy time estimation will be target dependent. Additionally on targets where the clocks are completely controlled by the on chip microcontroller, fetching and setting the current GPU frequency will be different. This patch aims to embrace these differences by re-factoring the devfreq code a bit. Signed-off-by: Sharat Masetty <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-10-04drm/msm/a6xx: Add gmu_read64() register read opSharat Masetty1-0/+10
Add a simple function to read 64 registers in the GMU domain Signed-off-by: Sharat Masetty <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-10-04drm/msm: suspend devfreq on initSharat Masetty1-0/+2
Devfreq turns on and starts recommending power level as soon as it is initialized. The GPU is still not powered on by the time the devfreq init happens and this leads to problems on GPU's where register access is needed to get/set power levels. So we start suspended and only restart devfreq when GPU is powered on. Signed-off-by: Sharat Masetty <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-10-04Merge branch 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld into ↵Dave Airlie7-73/+520
drm-next misc mali-dp updates. Signed-off-by: Dave Airlie <[email protected]> From: Liviu Dudau <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-10-04Merge tag 'tilcdc-4.20' of https://github.com/jsarha/linux into drm-nextDave Airlie2-13/+4
drm/tilcdc changes for Linux v4.20 suspend/resume update. Signed-off-by: Dave Airlie <[email protected]> From: Jyri Sarha <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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