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2014-09-16ARM: dts: hummingboard: Split HummingBoard DT to support s/dl and d/qRabeeh Khoury4-198/+219
Signed-off-by: Rabeeh Khoury <[email protected]> Signed-off-by: Russell King <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: i.MX53: add pmu nodeSteffen Trumtrar1-0/+5
The i.MX53 has a Cortex-A8 Performance Monitor Unit. Add it to the dtsi. Signed-off-by: Steffen Trumtrar <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: nitrogen6x: Add Intersil ISL1208 RTCPhilipp Zabel1-0/+5
This patch adds the battery backed real time clock connected to I2C1 to the device tree. Signed-off-by: Philipp Zabel <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: imx6sl-evk: Add LCD supportFabio Estevam2-0/+98
Add support for the "MX28LCD Seiko 4.3' WVGA" panel. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: imx6sl-evk.dts: Keep pinctrl nodes sortedFabio Estevam1-6/+6
Let's keep pinctrl nodes sorted. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: Gateworks GW5520 support (i.MX6)Tim Harvey4-0/+313
Add support for the Gateworks GW5520 board. Signed-off-by: Tim Harvey <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: i.MX: dts: Add simple-card supportAlexander Shiyan8-0/+20
This patch adds simple-card support to the i.MX SoCs. Signed-off-by: Alexander Shiyan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: i.MX: dts: Add support for the Freescale i.MX1 ADS boardAlexander Shiyan2-0/+153
This patch adds support for the Freescale (Motorola) i.MX1 ADS board. This change is intended to further remove non-DT support for this board. Signed-off-by: Alexander Shiyan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: vf610-twr: Add USB supportStefan Agner1-0/+10
Add USB support for Freescale Vybrid tower. The USB hosts over-current protection signal is not connected to the PHY's over- current protection, hence we need to disable it. Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: vf610-colibri: Add USB supportStefan Agner1-0/+10
Add USB support for Colibri VF61 modules. The Colibri standard pinout defines a pin for USB over-current. However, due to lack of pinmux options, the USB hosts over-current protection signal of the Colibri standard could not be connected to the PHY's over-current protection. Hence we need to disable the over-current functionality of the USB controller. Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: vf610: Add usbmisc for non-core registersStefan Agner1-1/+15
Add device tree node for usbmisc which controls the non-core USB registers. This is required to use the property to disable the over- current detection. Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: vf610: Add USB PHY and controllerStefan Agner1-3/+43
This adds USB PHY and USB controller nodes. Vybrid SoCs have two independent USB cores which each supports DR (dual role). However, real OTG is not supported since the OTG ID pin is not available. The PHYs are located within the anadig register range, hence we need to change the length of the anadig registers. Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: imx28: add alternative pinmuxing for i2c1Uwe Kleine-König1-0/+11
Signed-off-by: Uwe Kleine-König <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: imx28: add pinmuxing for mmc1Marc Kleine-Budde1-0/+32
Signed-off-by: Marc Kleine-Budde <[email protected]> [ukl: rebase from ancient kernel version] Signed-off-by: Uwe Kleine-König <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: imx25-pinfunc: Add several pin configurationsMichael Grzeschik1-2/+31
This patch adds pin configurations for: - csi aud6 - cspi1 uart3 - csi uart5 - cc - csi sdhc2 - csi cspi3 - sd1 cspi2 - cspi1 pwm Signed-off-by: Michael Grzeschik <[email protected]> Signed-off-by: Markus Pargmann <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: imx25: remove imx35-sdma compatibleMarkus Pargmann1-1/+1
The preloaded script addresses on imx25 and imx35 are different, so imx25 is not compatible with imx35-sdma unless a custom firmware is loaded. Signed-off-by: Markus Pargmann <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: vf610-twr: Add ttyLP2 device.Bill Pringlemeir1-2/+13
The ttyLP1 is already the default console/serial port. The tower board will route ttyLP2 to the same connectors depending on the JP23/24 settings. See: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/276457.html http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/275576.html Signed-off-by: Bill Pringlemeir <[email protected]> Acked-by: Stefan Agner <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: add thermal sensor support for i.mx6slAnson Huang1-1/+9
Add thermal sensor support for i.MX6SL. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: i.MX1: Add i.MX1 templateAlexander Shiyan2-0/+568
This patch adds basic devicetree template for i.MX1 based SoCs. Signed-off-by: Alexander Shiyan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: nitrogen6x: add i2c3Philipp Zabel1-0/+14
Signed-off-by: Philipp Zabel <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: nitrogen6x: add hdmiMichael Olbrich1-0/+5
Signed-off-by: Michael Olbrich <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: nitrogen6x: add i2c2Michael Olbrich1-0/+14
Signed-off-by: Michael Olbrich <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: imx6qdl-sabresd: add always on pcie regulatorLucas Stach1-0/+19
Everything in the PCI specification assumes devices to be enumerable on startup. This is only possible if they have power available. A future improvement may allow this regulator to be switched off for D3hot and D3cold power states, but there is a lot of work to do the pcie host controller side for this to work. To keep things simple always enable the regulator for now. Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: dts: vf610-colibri: split device tree for carrier boardsStefan Agner3-13/+49
The Colibri VF61 is a module which needs a carrier board to actually run. Different carrier board have different hardware support, hence we should reflect this in the device tree files. This patch adds the Colibri Evaluation Board, which supports almost all peripherals defined in the Colibri standard. Also align the compatible naming, file splitting and file naming with the scheme which was choosen for the Tegra based modules. Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16Merge branch 'imx/soc' into imx/dtShawn Guo39-1990/+521
2014-09-16Merge tag 'ib-mfd-arm-v3.18' into imx/dtShawn Guo8-20/+21
Immutable branch between MFD and some ARM sub-arch maintainers.
2014-09-16ARM: imx_v6_v7_defconfig updatesFabio Estevam1-6/+4
The rtc isl1208 driver is used by mx6 nitrogen board, so let's enable it by default. The fsl sai driver is used by the vf610-twr board, so let's enable it by default. simple-audio-card driver is used by the vf610-twr board, so let's enable it by default. Generated this patch by doing: - make imx_v6_v7_defconfig - make menuconfig and manually select options - make savedefconfig - cp defconfig arch/arm/configs/imx_v6_v7_defconfig ,which results in some additional cleanups. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx_v4_v5_defconfig: Select CONFIG_IMX_WEIMFabio Estevam1-9/+2
The imx weim driver is used by some mx27/mx1 boards, so let's enable it by default. Generated this patch by doing: - make imx_v4_v5_defconfig - make menuconfig and manually select CONFIG_IMX_WEIM - make savedefconfig - cp defconfig arch/arm/configs/imx_v4_v5_defconfig ,which results in some additional cleanups. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16arm: mach-imx: Convert pr_warning to pr_warnJoe Perches4-6/+6
Use the more common pr_warn. Signed-off-by: Joe Perches <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx: source gpt per clk from OSC for system timerAnson Huang1-5/+26
On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock can be from OSC instead of ipg_per, as ipg_per's rate may be scaled when system enter low bus mode, to keep system timer NOT drift, better to make gpt per clock at fixed rate, here add support for gpt per clock to be from OSC which is at fixed rate always. There are some difference on this implementation of gpt per clock source, see below for details: i.MX6Q TO > 1.0: GPT_CR_CLKSRC, b'101 selects fix clock of OSC / 8 for gpt per clk; i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, b'101 selects OSC for gpt per clk, and we must enable GPT_CR_24MEM to enable OSC clk source for gpt per, GPT_PR_PRESCALER24M is for pre-scaling of this OSC clk, here set it to 8 to make gpt per clk is 3MHz; i.MX6SL: ipg_per can be from OSC directly, so no need to implement this new clk source for gpt per. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx: add gpt_3m clk for i.mx6qdlAnson Huang2-1/+10
Add gpt_3m clock for i.mx6qdl, as gpt can source clock from OSC, some i.MX6 series SOCs has fixed divider of 8 for gpt clock, so here add a fix clk of gpt_3m. i.MX6Q TO1.0 has no gpt_3m option, so force it to be from ipg_per. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx: fix register offset of pll7_usb_host gate clockShawn Guo3-3/+3
There is a copy&paste error on register offset of pll7_usb_host gate clock introduced by i.MX6 PLL bypass support patches. The error breaks the ENET function, because it overwrites the pll6_enet gate bit. Correct the offset for all i.MX6 clock drivers. Thanks to Fugang Duan <[email protected]> for spotting the error. Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: clk-imx6sl: refine clock tree for SSIShengjiu Wang2-4/+14
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by: Shengjiu Wang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driverShawn Guo1-37/+0
Since ENABLE and BYPASS bits of PLLs are now implemented as separate gate and mux clocks by clock drivers, the code handling these two bits can be removed from clk-pllv3 driver. Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx6sx: add BYPASS support for PLL clocksShawn Guo2-10/+78
This is the same change for imx6sx clock driver as "ARM: imx6q: add BYPASS support for PLL clocks" for imx6q. The difference is that only anaclk1 is available on imx6sx. Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx6sl: add BYPASS support for PLL clocksShawn Guo2-9/+87
This is the same change for imx6sl clock driver as "ARM: imx6q: add BYPASS support for PLL clocks" for imx6q. The difference is that only anaclk1 is available on imx6sl. Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx6q: add BYPASS support for PLL clocksShawn Guo2-11/+83
The imx6q clock driver currently hard-codes all PLL clocks to source from OSC24M without BYPASS support. The patch adds the missing lvds_in clock which is mutually exclusive with lvds_gate, and implements BYPASS and BYPASS_CLK_SRC selection for PLL clocks as per Figure 10-3. Primary Clock Generation in IMX6DQRM, i.e. both BYPASS_CLK_SRC and BYPASS bits are implemented as mux clocks, and ENABLE bit of PLL clocks is implemented as a gate clock after BYPASS mux. Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx: add an exclusive gate clock typeShawn Guo3-1/+99
There are a couple of gate clocks are mutually exclusive on i.MX6, i.e. LVDSCLK1_IBEN and LVDSCLK1_OBEN. They cannot be enabled simultaneously. This patches adds an exclusive gate clock type specifically for such case. The clock driver will need to call imx_clk_gate_exclusive() to register a gate clock with parameter exclusive_mask indicating the mask of gate bits which are mutually exclusive to this gate clock. Right now, it only handles the exclusive gate clocks which are defined in a single hardware register, which is the case we're running into today. But it can be extended to handle exclusive gate clocks defined in different registers later if needed. Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: clk-imx6q: refine clock tree for SSIShengjiu Wang1-3/+9
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by: Shengjiu Wang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: clk-imx6q: refine clock tree for ASRCShengjiu Wang2-2/+7
ASRC has "asrc", "asrc_ipg", "asrc_mem" clocks, and they share the same gate bits. Signed-off-by: Shengjiu Wang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: clk-imx6sl: correct the pxp and epdc axi clock selectionsFancy Fang1-3/+4
The parent clocks of IMX6SL_CLK_PXP_AXI_SEL and IMX6SL_CLK_EPDC_AXI_SEL clocks are not the same. So split the epdc_pxp_sels into two different clock selections 'pxp_axi_sels' and 'epdc_axi_sels'. Signed-off-by: Fancy Fang <[email protected]> Signed-off-by: Robby Cai <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: clk-imx6q: refine clock tree for ESAIShengjiu Wang2-6/+8
There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Rename 'esai' to 'esai_extal', 'esai_ahb' to 'esai_mem', and add 'esai_ipg'. Make the clock for ESAI more clear and align them with imx6sx. Signed-off-by: Shengjiu Wang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: clk-imx6sl: Select appropriate parents for LCDIF clocksFabio Estevam1-0/+7
PLL5 is well suited for being the parent of IMX6SL_CLK_LCDIF_PIX_SEL and PLL2_PFD for IMX6SL_CLK_LCDIF_AXI_SEL. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: clk-imx6sl: Remove csi_lcdif_sels[]Fabio Estevam1-3/+4
Currently csi_lcdif_sels[] is a shared array for the providing the possible clock parents for csi and lcdif blocks. This is not correct, as csi and lcdif do not share the same clock parents. Introduce csi_sels[] for the csi and lcdif_axi_sels[] for the lcdif clocks in order to describe the parents correctly. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx: clk-vf610: Add USBPHY clocksStefan Agner2-3/+14
This commit adds PLL7 which is required for USBPHY1. It also adds the USB PHY and USB Controller clocks and the gates to enable them. Acked-by: Jingchang Lu <[email protected]> Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx: add cpufreq support for i.mx6sxAnson Huang1-0/+3
Add cpufreq support for i.MX6SX, using common i.MX6Q cpufreq driver. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx: clk-vf610: introduce clks_init_onStefan Agner1-0/+9
At the end of the boot process, the clock framework might disable required main PLL's. So far, this was no issue since drivers requested clocks, which are descended of the main PLL's (e.g. pll1_pfd1, which provides the system clock). To archive the full 500MHz system clock, DDR clock need to be a descendant of PLL2 rather than PLL1 (DDRC_CLK_SEL set to 0). The bootloader sets up the clocks accordingly before making use of DDR at all. However, in Linux, there is no driver using PLL2, which lead to PLL2 being disabled by the clock framework. With this patch, we make sure that the main system clock and the DDR clock are initially enabled and are kept enabled. Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: i.MX1: Add devicetree supportAlexander Shiyan3-0/+35
This patch adds basic devicetree support for i.MX1 based SoCs. Signed-off-by: Alexander Shiyan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: i.MX6: add more chip revision supportJason Liu2-0/+15
Add more revision support for the new i.MX6DQ tape-out (TO1.5). This TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3 and TO1.4 are never revealed. Signed-off-by: Jason Liu <[email protected]> Signed-off-by: Shawn Guo <[email protected]> Acked-by: Sascha Hauer <[email protected]>
2014-09-13ARM: mvebu: add user LED support of Armada 370 RDThomas Petazzoni1-0/+17
The Armada 370 RD has a GPIO controlled LED connected on MPP32, so this commit adds the relevant hardware description to Armada 370 RD Device Tree. Signed-off-by: Thomas Petazzoni <[email protected]> Acked-by: Andrew Lunn <[email protected]> Link: https://lkml.kernel.org/r/1410429419-29820-3-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <[email protected]>
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