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The PCI bus specification (rev 3.0, 3.2.5 "Transaction Ordering and
Posting") defines rules for PCI configuration space transactions ordering
and posting, that state that configuration writes are non-posted
transactions.
This rule is reinforced by the ARM v8 architecture reference manual (issue
A.k, Early Write Acknowledgment) that explicitly recommends that No Early
Write Acknowledgment attribute should be used to map PCI configuration
(write) transactions.
Current ioremap interface on ARM64 implements mapping functions where the
Early Write Acknowledgment hint is enabled, so they cannot be used to map
PCI configuration space in a PCI specs compliant way.
Implement an ARM64 specific pci_remap_cfgspace() interface that allows to
map PCI config region with nGnRnE attributes, providing a remap function
that complies with PCI specifications and the ARMv8 architecture reference
manual recommendations.
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
Cc: Will Deacon <[email protected]>
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Currently SoCs pass2.x do not emulate EA headers for ACPI boot method at
all. However, for pass2.x some devices (like EDAC) advertise incorrect
base addresses in their BARs which results in driver probe failure during
resource request. Since all problematic blocks are on 2nd NUMA node under
domain 10 add necessary quirk entry to obtain BAR addresses correction
using EA header emulation.
Fixes: 44f22bd91e88 ("PCI: Add MCFG quirks for Cavium ThunderX pass2.x host controller")
Signed-off-by: Tomasz Nowicki <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Robert Richter <[email protected]>
CC: [email protected] # v4.10+
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With no blank lines, it's not obvious where the macro definitions end and
the uses begin. Add some blank lines and reorder the ThunderX definitions.
No functional change intended.
Signed-off-by: Bjorn Helgaas <[email protected]>
CC: [email protected] # v4.10+
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Now that we've exported pci_remap_iospace() and added proper remove()
support, there's no reason this can't be a loadable module.
Signed-off-by: Brian Norris <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Shawn Lin <[email protected]>
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These are useful for PCIe host drivers, and those drivers can be modules.
[bhelgaas: don't remove __weak; it's removed elsewhere]
Signed-off-by: Brian Norris <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Shawn Lin <[email protected]>
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Currently, if we try to unbind the platform device, the remove will
succeed, but the removal won't undo most of the registration, leaving
partially-configured PCI devices in the system.
This allows, for example, a simple 'lspci' to crash the system, as it will
try to touch the freed (via devm_*) driver structures, e.g., on RK3399:
# echo f8000000.pcie > /sys/bus/platform/drivers/rockchip-pcie/unbind
# lspci
So let's implement device remove().
Signed-off-by: Brian Norris <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Shawn Lin <[email protected]>
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The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting")
mandate non-posted configuration transactions. As further highlighted in
the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the
Enhanced Configuration Access Mechanism"), through ECAM and ECAM-derivative
configuration mechanism, the memory mapped transactions from the host CPU
into Configuration Requests on the PCI express fabric may create ordering
problems for software because writes to memory address are typically posted
transactions (unless the architecture can enforce through virtual address
mapping non-posted write transactions behaviour) but writes to
Configuration Space are not posted on the PCI express fabric.
Current DT and ACPI host bridge controllers map PCI configuration space
(ECAM and ECAM-derivative) into the virtual address space through ioremap()
calls, that are non-cacheable device accesses on most architectures, but
may provide "bufferable" or "posted" write semantics in architecture like
eg ARM/ARM64 that allow ioremap'ed regions writes to be buffered in the bus
connecting the host CPU to the PCI fabric; this behaviour, as underlined in
the PCIe specifications, may trigger transactions ordering rules and must
be prevented.
Introduce a new generic and explicit API to create a memory mapping for
ECAM and ECAM-derivative config space area that defaults to
ioremap_nocache() (which should provide a sane default behaviour) but still
allowing architectures on which ioremap_nocache() results in posted write
transactions to override the function call with an arch specific
implementation that complies with the PCI specifications for configuration
transactions.
[bhelgaas: fold in #ifdef CONFIG_PCI wrapper]
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Will Deacon <[email protected]>
Cc: Russell King <[email protected]>
Cc: Catalin Marinas <[email protected]>
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pci_remap_iospace() is marked as a weak symbol even though no architecture
is currently overriding it; given that its implementation internals have
already code paths that are arch specific (ie PCI_IOBASE and
ioremap_page_range() attributes) there is no need to leave the weak symbol
in the kernel since the same functionality can be achieved by customizing
per-arch the corresponding functionality.
Remove the __weak symbol from pci_remap_iospace().
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
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A PCI/PCI-X to PCI Express bridge, sometimes referred to as a "reverse
bridge", is a bridge with conventional PCI or PCI-X on its primary side and
a PCI Express Port on its secondary (downstream) side.
That PCIe Port is a Downstream Port and could be connected to a slot, just
like a Root Port or a Switch Downstream Port. Make pcie_downstream_port()
return true for them, so we can access the Slot registers in the PCIe
capability.
Signed-off-by: Bjorn Helgaas <[email protected]>
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pci_host_common_probe() is defined when CONFIG_PCI_HOST_COMMON=y;
therefore the function declaration should match that.
drivers/pci/host/pcie-tango.c:300:9: error:
implicit declaration of function 'pci_host_common_probe'
Signed-off-by: Marc Gonzalez <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Local variables 'l' and 'sz' are uninitialized. Normally, they would
be initialized by pci_read_config_dword() but when an error occurs,
some drivers immediately return an error code, which leaves the
argument uninitialized.
Provide a safe initial value to make the code more robust.
Signed-off-by: Marc Gonzalez <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Signed-off-by: Christoph Hellwig <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
Reviewed-by: Keith Busch <[email protected]>
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These are small wrappers around request_threaded_irq() and free_irq(),
which dynamically allocate space for the device name so that drivers don't
need to keep static buffers for these around. Additionally it works with
device-relative vector numbers to make the usage easier, and force the
IRQF_SHARED flag on given that it has no runtime overhead and should be
supported by all PCI devices.
Signed-off-by: Christoph Hellwig <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
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This allows callers to get back at them instead of having to store it in
another variable.
Signed-off-by: Christoph Hellwig <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
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Signed-off-by: Christoph Hellwig <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
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refcount_t type and corresponding API should be used instead of atomic_t
when the variable is used as a reference counter. This allows to avoid
accidental refcounter overflows that might lead to use-after-free
situations.
Signed-off-by: Elena Reshetova <[email protected]>
Signed-off-by: Hans Liljestrand <[email protected]>
Signed-off-by: Kees Cook <[email protected]>
Signed-off-by: David Windsor <[email protected]>
Reviewed-by: Stephen Hemminger <[email protected]>
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On Cavium ThunderX2 arm64 SoCs (formerly known as Broadcom Vulcan), the PCI
topology is slightly unusual. For a multi-node system, it looks like:
00:00.0 PCI bridge to [bus 01-1e]
01:0a.0 PCI-to-PCIe bridge to [bus 02-04]
02:00.0 PCIe Root Port bridge to [bus 03-04] (XLATE_ROOT)
03:00.0 PCIe Endpoint
pci_for_each_dma_alias() assumes IOMMU translation is done at the root of
the PCI hierarchy. It generates 03:00.0, 01:0a.0, and 00:00.0 as DMA
aliases for 03:00.0 because buses 01 and 00 are non-PCIe buses that don't
carry the Requester ID.
Because the ThunderX2 IOMMU is at 02:00.0, the Requester IDs 01:0a.0 and
00:00.0 are never valid for the endpoint. This quirk stops alias
generation at the XLATE_ROOT bridge so we won't generate 01:0a.0 or
00:00.0.
The current IOMMU code only maps the last alias (this is a separate bug in
itself). Prior to this quirk, we only created IOMMU mappings for the
invalid Requester ID 00:00:0, which never matched any DMA transactions.
With this quirk, we create IOMMU mappings for a valid Requester ID, which
fixes devices with no aliases but leaves devices with aliases still broken.
The last alias for the endpoint is also used by the ARM GICv3 MSI-X code.
Without this quirk, the GIC Interrupt Translation Tables are setup with the
invalid Requester ID, and the MSI-X generated by the device fails to be
translated and routed.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=195447
Signed-off-by: Jayachandran C <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Robin Murphy <[email protected]>
Acked-by: David Daney <[email protected]>
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Add a new quirk flag PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT to limit the DMA alias
search to go no further than the bridge where the IOMMU unit is attached.
The flag will be used to indicate a bridge device which forwards the
address translation requests to the IOMMU, i.e., where the interrupt and
DMA requests leave the PCIe hierarchy and go into the system blocks.
Usually this happens at the PCI RC, so this flag is not needed. But on
systems where there are bridges that introduce aliases above the IOMMU,
this flag prevents pci_for_each_dma_alias() from generating aliases that
the IOMMU will never see.
The function pci_for_each_dma_alias() is updated to stop when it see a
bridge with this flag set.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=195447
Signed-off-by: Jayachandran C <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Robin Murphy <[email protected]>
Acked-by: David Daney <[email protected]>
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The ITE 8893 bridge has the same problems as the ITE 8892, which were
resulting in crippling an older PCI 1Gbps NIC down to 45Mbps throughput
with IOMMU and VT-d enabled. With the patch, this old e1000 goes back up
to ~900Mbps.
Suggested-by: Alex Williamson <[email protected]>
Signed-off-by: Jarod Wilson <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Alex Williamson <[email protected]>
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Add a couple of special IOCTLs to:
* Inform userspace of firmware partition locations
* Pass event counts and allow userspace to wait on events
* Translate PFF numbers used by the switch to port numbers
[Dan Carpenter <[email protected]>: fix off-by-one in
ioctl_event_ctl()]
Tested-by: Krishna Dhulipala <[email protected]>
Signed-off-by: Logan Gunthorpe <[email protected]>
Signed-off-by: Stephen Bates <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Wei Zhang <[email protected]>
Reviewed-by: Jens Axboe <[email protected]>
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Add a few read-only sysfs attributes which provide some device information
that is exposed from the devices, primarily component and device names and
versions.
These are documented in Documentation/ABI/testing/sysfs-class-switchtec.
Tested-by: Krishna Dhulipala <[email protected]>
Signed-off-by: Logan Gunthorpe <[email protected]>
Signed-off-by: Stephen Bates <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Wei Zhang <[email protected]>
Reviewed-by: Jens Axboe <[email protected]>
Reviewed-by: Greg Kroah-Hartman <[email protected]>
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Add standard documentation for the sysfs switchtec attributes and a RST
formatted text file which documents the char device interface. Jonathan
Corbet has indicated he will move this to a new user-space developer
documentation book once it's created.
Tested-by: Krishna Dhulipala <[email protected]>
Signed-off-by: Logan Gunthorpe <[email protected]>
Signed-off-by: Stephen Bates <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Wei Zhang <[email protected]>
Reviewed-by: Jens Axboe <[email protected]>
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All platforms using Rockchip use a common clock for the Root Port and the
slot connected to it. Indicate this by setting the Slot Clock Configuration
(PCI_EXP_LNKSTA_SLC) bit in the Root Port's Link Status.
Per the Implementation Note in the spec (PCIe r3.1, sec 7.8.7), if the
downstream component also sets PCI_EXP_LNKSTA_SLC, software may set the
Common Clock Configuration (PCI_EXP_LNKCTL_CCC) bits on both ends of the
Link. This is done by pcie_aspm_configure_common_clock().
Signed-off-by: Shawn Lin <[email protected]>
Cc: Brian Norris <[email protected]>
Cc: jeffy.chen <[email protected]>
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Adds a new endpoint function driver (to program the virtual test device)
making use of the EP-core library.
[bhelgaas: fold in pci_epf_test_probe() -ENOMEM test from Wei Yongjun
<[email protected]>]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Add specification for the *PCI test* virtual function device. The endpoint
function driver and the host PCI driver should be created based on this
specification.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Invoke APIs provided by pci-ep-cfs to create configfs entry for every EPC
device and EPF driver to help users in creating EPF device and binding the
EPF device to the EPC device.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Add Documentation to help users use PCI endpoint to configure PCI endpoint
function and to bind the endpoint function with endpoint controller.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Acked-By: Joao Pinto <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Introduce a new configfs entry to configure the EP function (like
configuring the standard configuration header entries) and to bind the EP
function with EP controller.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Add Documentation to help users use endpoint library to enable endpoint
mode in the PCI controller and add new PCI endpoint functions.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Acked-By: Joao Pinto <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Introduce a new EP core layer in order to support endpoint functions in
linux kernel. This comprises the EPC library (Endpoint Controller Library)
and EPF library (Endpoint Function Library). EPC library implements
functions specific to an endpoint controller and EPF library implements
functions specific to an endpoint function.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Acked-by: Joao Pinto <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Save a bit of time and avoid going through link speed change procedure in
configuration where link max speed is limited to Gen1 in DT.
Signed-off-by: Andrey Smirnov <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
Cc: [email protected]
Cc: Fabio Estevam <[email protected]>
Cc: Dong Aisheng <[email protected]>
Cc: [email protected]
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As can be seen from [1]:
"...the different behavior between iMX6Q PCIe and iMX7D PCIe maybe caused
by the different controller version.
Regarding to the DOC description, the DIRECT_SPEED_CHANGE should be
cleared after the speed change from GEN1 to GEN2. Unfortunately, when
GEN1 device is used, the behavior is not documented.
So, IC design guys run the simulation and find out the following
behaviors:
1. DIRECT_SPEED_CHANGE will be cleared in 7D after speed change
from GEN1 to GEN2. This matches doc’s description
2. set MAX link speed(PCIE_CAP_TARGET_LINK_SPEED=0x01) as GEN1 and
re-run the simulation, DIRECT_SPEED_CHANGE will not be cleared;
remain as 1, this matches your result, but function test is
passed, so this bit should not affect the normal PCIe function."
imx6_pcie_wait_for_speed_change() will report false failures for Gen1 ->
Gen1 speed transition, so avoid doing that check and just rely on
imx6_pcie_wait_for_link() only.
[1] https://community.nxp.com/message/867943
Signed-off-by: Andrey Smirnov <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
Cc: [email protected]
Cc: Fabio Estevam <[email protected]>
Cc: Dong Aisheng <[email protected]>
Cc: [email protected]
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Some designs implement reset GPIO via a GPIO expander connected to a
peripheral bus. One such example would be i.MX7 Sabre board where said
GPIO is provided by SPI shift register connected to a bitbanged SPI bus.
To support such designs, allow reset GPIO request to defer probing of the
driver.
Signed-off-by: Andrey Smirnov <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
Cc: [email protected]
Cc: Fabio Estevam <[email protected]>
Cc: Dong Aisheng <[email protected]>
Cc: [email protected]
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Add various bits of code needed to support i.MX7D variant of the IP.
Signed-off-by: Andrey Smirnov <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
Acked-by: Lee Jones <[email protected]>
Acked-by: Rob Herring <[email protected]>
Cc: [email protected]
Cc: Mark Rutland <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Dong Aisheng <[email protected]>
Cc: [email protected]
Cc: [email protected]
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The memory allocation here needs to be non-blocking. Fix the issue.
Signed-off-by: K. Y. Srinivasan <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Long Li <[email protected]>
Cc: <[email protected]>
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When we have 32 or more CPUs in the affinity mask, we should use a special
constant to specify that to the host. Fix this issue.
Signed-off-by: K. Y. Srinivasan <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Long Li <[email protected]>
Cc: <[email protected]>
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There is no pci_cfg_access_unlocked(). I think the author meant
pci_cfg_access_unlock().
Signed-off-by: Brian Norris <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Currently devm_request_irq() is being called before base, PCI fields of
dra7xx_pcie structure are populated. It is called even before
pm_runtime_enable() and pm_runtime_get_sync() are called. This will lead
to exceptions if in case an interrupt is triggered before the all of the
above are done. Hence push the devm_request_irq() call to the end of the
probe.
Signed-off-by: Keerthy <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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No functional change. Rename dw_pcie_writel_unroll/dw_pcie_readl_unroll to
dw_pcie_writel_ob_unroll/dw_pcie_readl_ob_unroll respectively as these
functions are used to perform only outbound configurations. Also move
these _unroll configurations to a separate function.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Previously dbi accessors can be used to access data of size 4 bytes. But
there might be situations (like accessing MSI_MESSAGE_CONTROL in order to
set/get the number of required MSI interrupts in EP mode) where dbi
accessors must be used to access data of size 2. This is in preparation
for adding endpoint mode support to designware driver.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Niklas Cassel <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Joao Pinto <[email protected]>
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dwc has 2 dbi address space labeled dbics and dbics2. The existing helper
to access dbi address space can access only dbics. However dbics2 has to
be accessed for programming the BAR registers in the case of EP mode. This
is in preparation for adding EP mode support to dwc driver.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Niklas Cassel <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Joao Pinto <[email protected]>
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Populate cpu_addr_fixup ops to extract the least 28 bits of the
corresponding CPU address.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Niklas Cassel <[email protected]>
Acked-by: Joao Pinto <[email protected]>
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Populate cpu_addr_fixup ops to extract the least 28 bits of the
corresponding CPU address.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Joao Pinto <[email protected]>
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Some platforms (like dra7xx) require only the least 28 bits of the
corresponding 32 bit CPU address to be programmed in the address
translation unit. This modified address is stored in io_base/mem_base/
cfg0_base/cfg1_base in dra7xx_pcie_host_init(). While this is okay for
host mode where the address range is fixed, device mode requires different
addresses to be programmed based on the host buffer address. Add a new
ops to get the least 28 bits of the corresponding 32 bit CPU address and
invoke it before programming the address translation unit.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Joao Pinto <[email protected]>
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The bug is that "val" is unsigned long but we only initialize 32 bits of
it. Then we test "if (val)" and that might be true not because we set the
bits but because some were never initialized.
Fixes: f342d940ee0e ("PCI: exynos: Add support for MSI")
Signed-off-by: Dan Carpenter <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Use "continue" to skip rest of the loop when possible to save an indent
level. No functional change intended.
Suggested-by: walter harms <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Fix a crash from dereferencing a NULL dw_pcie_ops pointer. For example,
on ARTPEC-6:
Unable to handle kernel NULL pointer dereference at virtual address 00000004
pgd = c0204000
[00000004] *pgd=00000000
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.11.0-rc3-next-20170321 #1
Hardware name: Axis ARTPEC-6 Platform
task: db098000 task.stack: db096000
PC is at dw_pcie_writel_dbi+0x2c/0xd0
Prior to 442ec4c04d12 ("PCI: dwc: all: Split struct pcie_port into
host-only and core structures"), every driver had a struct pcie_host_ops
with function pointers, typically used as:
if (pp->ops->readl_rc)
return pp->ops->readl_rc(...);
442ec4c04d12 split struct pcie_host_ops into two pieces: struct
dw_pcie_host_ops and struct dw_pcie_ops, so the above became:
if (pci->ops->readl_dbi)
return pci->ops->readl_dbi(...);
But pcie-artpec6.c and pcie-designware-plat.c don't need the dw_pcie_ops
pointers and didn't supply a pci->ops struct, which leads to NULL pointer
dereferences.
Supply an empty struct dw_pcie_ops to avoid the NULL pointer dereferences.
[bhelgaas: changelog]
Fixes: 442ec4c04d12 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures")
Signed-off-by: Niklas Cassel <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Kishon Vijay Abraham I <[email protected]>
Acked-by: Joao Pinto <[email protected]>
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Without PCI_HOST_COMMON support enabled, we get a link error:
drivers/pci/dwc/built-in.o: In function `hisi_pcie_map_bus':
pcie-hisi.c:(.text+0x8860): undefined reference to `pci_ecam_map_bus'
drivers/pci/dwc/built-in.o: In function `hisi_pcie_almost_ecam_probe':
pcie-hisi.c:(.text+0x88b4): undefined reference to `pci_host_common_probe'
Add an explicit 'select', as the other users have.
Signed-off-by: Arnd Bergmann <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Jingoo Han <[email protected]>
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Rockchip Root Ports support either 64 or 128 byte Read Completion Boundary
(RCB). Set the RCB bit in the Link Control register to indicate this.
A 128 byte RCB significantly improves performance of NVMe with libaio.
[bhelgaas: changelog]
Signed-off-by: Shawn Lin <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Cc: Brian Norris <[email protected]>
Cc: Jeffy Chen <[email protected]>
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SZ_16M PEM resource size includes PEM-specific register and its children
resources. Reservation of the whole SZ_16M range leads to child device
driver failure when pcieport driver is requesting resources:
pcieport 0004:1f:00.0: can't enable device: BAR 0 [mem 0x87e0c0f00000-0x87e0c0ffffff 64bit] not claimed
So we cannot reserve full 16M here and instead we want to reserve
PEM-specific register only which is SZ_64K.
At the end increase PEM resource to SZ_16M since this is what
thunder_pem_init() call expects for proper initialization.
Fixes: 9abb27c7594a ("PCI: thunder-pem: Add legacy firmware support for Cavium ThunderX host controller")
Signed-off-by: Tomasz Nowicki <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
CC: [email protected] # v4.10+
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