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Adds clk support for the pl031 RTC on hi6220
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Pawel Moll <[email protected]>
Cc: Wei Xu <[email protected]>
Cc: Guodong Xu <[email protected]>
Signed-off-by: Zhangfei Gao <[email protected]>
[jstultz: Forward ported, tweaked commit description]
Signed-off-by: John Stultz <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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This commit adds the Device Tree description for the two XOR engines
found in the CP part of the Armada 7K/8K SoC.
Signed-off-by: Thomas Petazzoni <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
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As suggested by Rob Herring, we should:
1/ Use a SoC-specific compatible string in addition to the more generic
one.
2/ The generic compatible string has been changed from
"marvell,mv-xor-v2" to "marvell,xor-v2".
We simply reflect the changes made to the Device Tree bindings to the
relevant Marvell 7K/8K Device Tree files.
Signed-off-by: Thomas Petazzoni <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
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This names the GPIO lines on the HiKey board in accordance with
the 96Board Specification for especially the Low Speed External
Connector: "GPIO-A" thru "GPIO-L".
This will make these line names reflect through to userspace
so that they can easily be identified and used with the new
character device ABI.
Some care has been taken to name all lines, not just those used
by the external connectors, also lines that are muxed into some
other function than GPIO: these are named "[FOO]" so that users
can see with lsgpio what all lines are used for.
Cc: [email protected]
Cc: John Stultz <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: David Mandala <[email protected]>
Cc: Haojian Zhuang <[email protected]>
Cc: Wei Xu <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Signed-off-by: Wei Xu <[email protected]>
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There are two sleep related pins on rk3399: ap_pwroff and ddrio_pwroff.
Let's add the definition of these two pins to rk3399's main dtsi file so
that boards can use them.
These two pins are similar to the global_pwroff and ddrio_pwroff pins in
rk3288 and are expected to be used in the same way: boards will likely
want to configure these pinctrl settings in their global pinctrl hog
list.
Note that on rk3288 there were two additional pins in the "sleep"
section: "ddr0_retention" and "ddr1_retention". On rk3288 designs these
pins appeared to actually route from rk3288 back to rk3288. Presumably
on rk3399 this is simply not needed since the pins don't appear to exist
there.
Signed-off-by: Douglas Anderson <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
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This patch adds support to sdc2 sdhci controller, which is used on some
of the boards.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch adds pinctrl required for sdhci for external sd card
controller.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch adds support to blsp2_spi5 device, which is used in some of
the APQ8096 based boards.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch adds pinctrl required for blsp2_spi5 device.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch adds support to blsp1_spi0 which is used on some of APQ8096
based boards.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch adds pinctrl nodes required for blsp1_spi0.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch adds support to blsp2_i2c0, which is used on some of the
APQ8096 based boards.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch adds support to blsp2_i2c0 pinctrl.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch adds support to blsp2_i2c1, which is used in one of the
apq8096 based boards.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch adds support to blsp2_i2c1 pinctrl nodes.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch adds blsp1_i2c2 support, as this bus is used on some of the
apq8096 boards.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch adds pinctrl nodes required for blsp1_i2c2.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch adds bslp2_uart2 node in soc so that boards that use this
uart can enable it.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch adds blsp2_uart2 pinctrl nodes.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch adds 2pin and 4 pin uart pinctrl support for blsp2_uart1
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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This patch adds msmgpio label for pin and gpio controller so that
it can referenced in dedicated pins file and other board level gpios.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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With the clock driver upstream, switch to the real clock.
Signed-off-by: Kevin Hilman <[email protected]>
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Add the clock controller node for the AmLogic GXBB machine.
Signed-off-by: Michael Turquette <[email protected]>
Signed-off-by: Kevin Hilman <[email protected]>
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Previous changes in this series allowed exposing the card clock from the
rk3399 SDHCI device and allowed consuming the card clock in the rk3399
eMMC PHY. Hook things up in the main rk3399 dtsi file.
Signed-off-by: Douglas Anderson <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
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On rk3399 we'd like to be able to properly set corecfg registers in the
Arasan SDHCI component. Specify the syscon to enable that.
Signed-off-by: Douglas Anderson <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
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The juno dts have entries for the hwmon scpi, let's create thermal zones
for the temperature sensors described in the Juno ARM Development
Platform Implementation Details.
Cc: Liviu Dudau <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Acked-by: Punit Agrawal <[email protected]>
Signed-off-by: Javi Merino <[email protected]>
Signed-off-by: Sudeep Holla <[email protected]>
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This patch adds power domain information to coresight devices using
SCPI power domains.
Cc: Lorenzo Pieralisi <[email protected]>
Acked-by: Liviu Dudau <[email protected]>
Signed-off-by: Sudeep Holla <[email protected]>
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Most of the debug-related components on Juno are located in the coreSight
subsystem while others are located in the Cortex-Axx clusters, the SCP
subsystem, and in the main system.
Each core in the two processor clusters contain an Embedded Trace
Macrocell(ETM) which generates real-time trace information that trace
tools can use and an ATB trace output that is sent to a funnel before
going to the CoreSight subsystem.
The trace output signals combine with two trace expansions using another
funnel and fed into the Embedded Trace FIFO(ETF0).
The output trace data stream of the funnel is then replicated before it
is sent to either the:
- Trace Port Interface Unit(TPIU), that sends it out using the trace port.
- ETR that can write the trace data to memory located in the application
memory space
Cc: Lorenzo Pieralisi <[email protected]>
Acked-by: Liviu Dudau <[email protected]>
Acked-by: Mathieu Poirier <[email protected]>
Signed-off-by: Sudeep Holla <[email protected]>
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Signed-off-by: Khiem Nguyen <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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This patch adds DRIF module clocks for r8a7795 SoC.
Signed-off-by: Ramesh Shanmugasundaram <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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According to the latest information, the parent clock of the LVDS module
clock is the S0D4 clock, not the S2D1 clock.
Note that this change has no influence on actual operation, as the
rcar-du LVDS encoder driver doesn't use the parent clock's rate.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
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Reviewed-by: Laurent Pinchart <[email protected]>
Signed-off-by: Kieran Bingham <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Renesas R-Car V2H (R8A7792) clocks are handled by R-Car gen2 clock driver.
Signed-off-by: Sergei Shtylyov <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Renesas R8A7792 SoC also has the CPG MSTP clocks...
Signed-off-by: Sergei Shtylyov <[email protected]>
Acked-by: Simon Horman <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Renesas R8A7792 SoC is a member of the R-Car gen2 family and so has CPG...
Signed-off-by: Sergei Shtylyov <[email protected]>
Acked-by: Simon Horman <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Adds the cache nodes and next-level-cache property for the
cacheinfo to work.
Signed-off-by: Li Yang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Adds the cache nodes and next-level-cache property for the
cacheinfo to work.
Signed-off-by: Li Yang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Node qmlclk has no consumer, so remove it.
Signed-off-by: Duc Dang <[email protected]>
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Correct X-Gene 2 timer interrupt polarity as low-level triggered.
Signed-off-by: Duc Dang <[email protected]>
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Unit addresses should not have a leading '0x'. Remove them.
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Duc Dang <[email protected]>
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The convention in these files is to use lowercase for "0x" prefixes and for
the hex constants themselves, but a few changes didn't follow that
convention, which makes the file annoying to read.
Use lowercase consistently for the hex constants. No functional change
intended.
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Duc Dang <[email protected]>
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http://github.com/Broadcom/stblinux into next/dt64
This pull request contains Device Tree changes for Broadcom ARM64-based SoCS:
- Anup adds nodes for the AHCI and SATA3 PHY peripherals to the Northstar2 SoCs
- Dhanajay enables pinctrl for the Northstar2 SoCs
- Jon Mason enables all of the UART peripherals found in the NS2 SVK and
finally adds the CCI-400 and PMU nodes
* tag 'arm-soc/for-4.8/devicetree-arm64' of http://github.com/Broadcom/stblinux:
arm64: dts: NS2: Add CCI-400 PMU support
arm64: dts: NS2: Add all of the UARTs
arm64: dts: Enable GPIO for Broadcom NS2 SoC
arm64: dts: enable pinctrl for Broadcom NS2 SoC
arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2
dt-bindings: ata: add compatible string for iProc AHCI controller
Signed-off-by: Olof Johansson <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt64
Amlogic DT 64-bit changes for v4.8
- add pinctrl driver and pins for several devices
- add reset driver
* tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM64: dts: amlogic: Enable Reset Controller on GXBB-based platforms
ARM64: dts: amlogic: gxbb: add ethernet
ARM64: dts: amlogic: gxbb: pinctrl: add/update UART
ARM64: dts: amlogic: add pins for EMMC, SD
ARM64: dts: amlogic: Enable pin controller on GXBB-based platforms
documentation: Add compatibles for Amlogic Meson GXBB pin controllers
ARM64: dts: amlogic: Add hiu and periphs buses
Signed-off-by: Olof Johansson <[email protected]>
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The 2nd additional region is the GIC virtual cpu interface register
base and size.
As the gic400 of rk3368 says, the cpu interface register map as below
:
-0x0000 GICC_CTRL
.
.
.
-0x00fc GICC_IIDR
-0x1000 GICC_IDR
Obviously, the region size should be greater than 0x1000.
So we should make sure to include the GICC_IDR since the kernel will access
it in some cases.
Fixes: b790c2cab5ca ("arm64: dts: add Rockchip rk3368 core dtsi and board dts for the r88 board")
Signed-off-by: Caesar Wang <[email protected]>
Reviewed-by: Shawn Lin <[email protected]>
Cc: [email protected]
[added Fixes and stable-cc]
Signed-off-by: Heiko Stuebner <[email protected]>
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We've got 9 (count em!) i2c controllers on rk3399, some of which are in
the PMU power domain and some of which are normal peripherals. Add them
all to the main rk3399 dtsi file so future patches can turn them on in
the board dts files.
Note: by default we try to set the i2c clock rate to 200 MHz so that we
can achieve good i2c functional clock rates. 200 MHz gives us the
ability to make very close to 100 kHz / 400 kHz / 1 MHz rates. If
boards want to tune clock rates further they can always override.
Possibly boards could want to tune this if:
- they wanted to save an infinitesimal amount of power and they knew
their i2c bus was slow anyway. Since we gate the functional clock
when the i2c bus is not active, power savings would only be while i2c
transfers were happening and probably won't be very big anyway.
- they wanted to eek out a bit more speed by carefully tuning the source
clock to make divisions work out perfectly, accounting for the rise /
fall time measured on an actual board.
Note also that we still request 200 MHz for the PMU i2c busses even
though we expect that we won't make that exactly (currently PPLL is 676
MHz which gives us 169 MHz).
Signed-off-by: David Wu <[email protected]>
Signed-off-by: Jianqun Xu <[email protected]>
[dianders: wrote desc; put in assigned-clocks; reordered nodes]
Signed-off-by: Douglas Anderson <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
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Make the sor1 and sor1_src clocks available on Tegra210. They will be
used by the display driver to support HDMI and DP.
Signed-off-by: Thierry Reding <[email protected]>
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The sor1 clock on Tegra210 is structured in the following way:
+-------+
| pllp |---+
+-------+ | +--------------+ +-----------+
+----| | | sor_safe |
+-------+ | | +-----------+
| plld |--------| | |
+-------+ | | +-----------+
| sor1_src |-------| |
+-------+ | | +-----------+
| plld2 |--------| | |
+-------+ | | |
+----| | |
+-------+ | +--------------+ |
| clkm |---+ +-----------+
+-------+ +--------------+ | |
| sor1_brick |-------| sor1 |
+--------------+ | |
+-----------+
This is impractical to represent in a clock tree, though, because there
is no name for the mux that has sor_safe and sor1_src as parents. It is
also much more cumbersome to deal with the additional mux because users
of these clocks (the display driver) would have to juggle with an extra
mux for no real reason.
To simply things, the above is squashed into two muxes instead, so that
it looks like this:
+-------+
| pllp |---+
+-------+ | +--------------+ +-----------+
+----| | | sor_safe |
+-------+ | | +-----------+
| plld |--------| | |
+-------+ | | +-----------+
| sor1_src |-------| sor1 |
+-------+ | | +-----------+
| plld2 |--------| | | |
+-------+ | | | |
+----| | | |
+-------+ | +--------------+ | |
| clkm |---+ | |
+-------+ +--------------+ | |
| sor1_brick |-----------+---+
+--------------+
This still very accurately represents the hardware. Note that sor1 has
sor1_brick as input twice, that's because bit 1 in the mux selects the
sor1_brick irrespective of bit 0.
Signed-off-by: Thierry Reding <[email protected]>
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Enabling spread spectrum on pll_d2 can lead to issues with display
modes. HDMI monitors, for example, would report "Signal Error" and
some modes driven over DisplayPort would generate fuzzy horizontal
bands.
Signed-off-by: Thierry Reding <[email protected]>
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The 'dma-coherent' indicates that the hardware IP block can ensure
the coherency of the data transferred from/to the IP block. This
can avoid the software cache flush/invalid actions, and improve
the performance significantly.
The PCI IP block of ls1043a has this capability, so adding this
feature to improve the PCI performance.
Signed-off-by: Liu Gang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Add 'dma-coherent' description for PCI nodes.
The 'dma-coherent' indicates that the hardware IP block can ensure
the coherency of the data transferred from/to the IP block. This
can avoid the software cache flush/invalid actions, and improve
the performance significantly.
The PCI IP block of ls1043a has this capability, so adding
this feature to improve the PCI performance.
Signed-off-by: Liu Gang <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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