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2020-04-30Merge tag 'amd-drm-next-5.8-2020-04-24' of ↵Dave Airlie260-3868/+9302
git://people.freedesktop.org/~agd5f/linux into drm-next amd-drm-next-5.8-2020-04-24: amdgpu: - Documentation improvements - Enable FRU chip access on boards that support it - RAS updates - SR-IOV updates - Powerplay locking fixes for older SMU versions - VCN DPG (dynamic powergating) cleanup - VCN 2.5 DPG enablement - Rework GPU scheduler handling - Improve scheduler priority handling - Add SPM (streaming performance monitor) golden settings for navi - GFX10 clockgating fixes - DC ABM (automatic backlight modulation) fixes - DC cursor and plane fixes - DC watermark fixes - DC clock handling fixes - DC color management fixes - GPU reset fixes - Clean up MMIO access macros - EEPROM access fixes - Misc code cleanups amdkfd: - Misc code cleanups radeon: - Clean up safe reg list generation - Misc code cleanups From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-04-24Merge tag 'drm-misc-next-2020-04-23' of ↵Dave Airlie96-1809/+2162
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.8: UAPI Changes: Cross-subsystem Changes: * MAINTAINERS: adapt several filenames to changes in panel code * arch/arm, fbdev: Use GPIO descriptors in sa11x0 * dma-buf: Fix typo in documentation Core Changes: * drm: Don't free framebuffer in drm_gem_fb_init() * drm: Document struct drm_device.dev_private being deprecated * drm: Merged topic/phy-compliance-202004-08 Driver Changes: * drm/adv7511: Add support for HDMI SPDIF and additional sampling rates * drm/ast: Allocate CRTC state of correct size * drm/panel: convert many driver bindings to DT schema; add port/ports property to bindings * drm/rockchip: Convert rk3066 bindings to YAML; spelling fixes * fbdev/arcfb: Call request_irq(), free_irq() at appropriate places * fbdev/controlfb: Support COMPILE_TEST; cleanups * fbdev/imxfb: Fix unbalanced enables/disables * fbdev/s1d13xxxfb: Call unregister_framebuffer() * fbdev/ssd1307fb: Use atomic PWM API, device properties and probe_new(); cleanups * fbdev/vesafb: Call release_region() * cleanups of includes, unused types/variables/fields, and fallthrough Signed-off-by: Dave Airlie <[email protected]> From: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20200423083425.GA15883@linux-uq9g
2020-04-23drm/amdgpu: retire legacy vega10 sos version checkHawking Zhang1-27/+1
retired those early sos version used in vega10 bring up phase Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: switch to helper function to init sos ucodeHawking Zhang2-84/+6
call common helper function to init sos ucode, instead of duplicate codes per ip version Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: add helper function to init sos ucodeHawking Zhang2-0/+72
driver already had psp_firmware_header struture to deal with different layout of sos ucode. the sos micorcode initialization could be common one. Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: switch to helper function to init asd ucodeHawking Zhang4-75/+5
call common helper function to initialize asd ucode Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: add helper function to init asd ucodeHawking Zhang2-0/+38
asd is unified ucode across asic. it is not necessary to keep its software structure to be ip specific one Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: retire unused check_fw_loading statusHawking Zhang6-544/+0
The driver can't access UCODE_DATA/ADDR registers on production boards. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: remove unnecessary tOS version checkHawking Zhang3-16/+4
tOS version is available through debugfs interface Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: retire support_vmr_ring interfaceHawking Zhang5-66/+30
vmr ring is dedicated for sriov vf (i.e.guest driver in sriov), which is general communication interface between driver and psp fw accross all ip version. it is not correct to make it as ip specific callback. it is even worse to check specific tOS version per IP version (like psp_v11/v12). Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: shrink critical section in amdgpu_amdkfd_gpuvm_free_memory_of_gpuBernard Zhao1-7/+7
Reduce the mem->lock`s protected code area, no need to protect pr_debug. This also simplifies error handling. Signed-off-by: Bernard Zhao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: Init data to avoid oops while reading pp_num_states.limingyu1-1/+4
For chip like CHIP_OLAND with si enabled(amdgpu.si_support=1), the amdgpu will expose pp_num_states to the /sys directory. In this moment, read the pp_num_states file will excute the amdgpu_get_pp_num_states func. In our case, the data hasn't been initialized, so the kernel will access some ilegal address, trigger the segmentfault and system will reboot soon: uos@uos-PC:~$ cat /sys/devices/pci0000\:00/0000\:00\:00.0/0000\:01\:00 .0/pp_num_states Message from syslogd@uos-PC at Apr 22 09:26:20 ... kernel:[ 82.154129] Internal error: Oops: 96000004 [#1] SMP This patch aims to fix this problem, avoid that reading file triggers the kernel sementfault. Signed-off-by: limingyu <[email protected]> Signed-off-by: zhoubinbin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: remove set but not used variable 'priority'YueHaibing1-2/+0
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c: In function amdgpu_job_submit: drivers/gpu/drm/amd/amdgpu/amdgpu_job.c:148:26: warning: variable priority set but not used [-Wunused-but-set-variable] commit 33abcb1f5a17 ("drm/amdgpu: set compute queue priority at mqd_init") left behind this, remove it. Reviewed-by: Christian König <[email protected]> Signed-off-by: YueHaibing <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm: amdgpu: fix kernel-doc struct warningRandy Dunlap1-1/+1
Fix a kernel-doc warning of missing struct field desription: ../drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:92: warning: Function parameter or member 'vm' not described in 'amdgpu_vm_eviction_lock' Fixes: a269e44989f3 ("drm/amdgpu: Avoid reclaim fs while eviction lock") Signed-off-by: Randy Dunlap <[email protected]> Cc: Signed-off-by: Alex Sierra <[email protected]> Cc: Felix Kuehling <[email protected]> Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Cc: David (ChunMing) Zhou <[email protected]> Cc: [email protected] Reviewed-by: Harry Wentland <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm: amd/display: fix Kconfig help textRandy Dunlap1-6/+2
Fix help text: indent one tab + 2 spaces; end a sentence with a period; and collapse short lines of text to one line. Fixes: 23c61b4599c4 ("drm/amd: Fix Kconfig indentation") Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by: Randy Dunlap <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Krzysztof Kozlowski <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-23drm/amdgpu: request reg_val_offs each kiq read regYintian Tao7-29/+41
According to the current kiq read register method, there will be race condition when using KIQ to read register if multiple clients want to read at same time just like the expample below: 1. client-A start to read REG-0 throguh KIQ 2. client-A poll the seqno-0 3. client-B start to read REG-1 through KIQ 4. client-B poll the seqno-1 5. the kiq complete these two read operation 6. client-A to read the register at the wb buffer and get REG-1 value Therefore, use amdgpu_device_wb_get() to request reg_val_offs for each kiq read register. v2: fix the error remove v3: fix the print typo v4: remove unused variables Signed-off-by: Yintian Tao <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amdgpu: change how we update mmRLC_SPM_MC_CNTLChristian König3-8/+28
In pp_one_vf mode avoid the extra overhead and read/write the registers without the KIQ. Signed-off-by: Christian König <[email protected]> Reviewed-by: Monk Liu <[email protected]> Acked-by: Yintian Tao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amdgpu: set error query ready after all IPs late initDennis Li2-5/+3
If set error query ready in amdgpu_ras_late_init, which will cause some IP blocks aren't initialized, but their error query is ready. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amdgpu: code cleanup around gpu resetEvan Quan1-10/+4
Make code more readable. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amdgpu: optimize the gpu reset for XGMI setup V2Evan Quan1-51/+25
This is basically just some code cosmetic. The current design for XGMI setup gput reset is to operate on current device(adev) first and then on other devices from the hive(by another 'for' loop). But actually we can do some sort to the device list(to put current device 1st position) and handle all the devices in a single 'for' loop. V2: added missing hive->hive_lock protection Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amdgpu: correct cancel_delayed_work_sync on gpu resetEvan Quan1-0/+2
As for XGMI setup, it should be performed on other devices from the hive also. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amdgpu: correct fbdev suspend on gpu resetEvan Quan1-1/+1
As for XGMI setup, it needs to be performed on all the devices from the same hive. Signed-off-by: Evan Quan <[email protected]> Acked-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amdgpu: cleanup coding style in amdkfd a bitBernard Zhao1-11/+9
Make the code a bit more readable by using a common error handling pattern. Signed-off-by: Bernard Zhao <[email protected]> Reviewed-by: Christian König <[email protected]>. Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amdgpu: clean up unused variable about ring lruKevin Wang2-6/+0
clean up unused variable: 1. ring_lru_list 2. ring_lru_list_lock related-commit: drm/amdgpu: remove ring lru handling Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amdgpu: replace DRM prefix with PCI device info for gfx/mmhubDennis Li2-16/+31
Prefix RAS message printing in gfx/mmhub with PCI device info, which assists the debug in multiple GPU case. Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Dennis Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/powerplay: limit smu support to Arcturus for onevfJiansong Chen1-1/+4
Under onevf mode the smu support to other chips is not well verified yet. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amdgpu: disble vblank when unloading sriov driverJiawei1-1/+2
disble vblank in dce_vitual_crtc_commit(), which is skipped under sriov before Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Jiawei <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amdgpu: Print CU information by default during initializationYong Zhao1-1/+2
This is convenient for multiple teams to obtain the information. Also, add device info by using dev_info(). Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Dennis Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/powerplay: update smu12_driver_if.h to align with pmfwPrike Liang1-15/+25
Update the smu12_driver_if.h header to follow the pmfw release. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amdgpu/powerplay:avoid to show invalid DPM table infoYuxian Dai1-0/+2
for different ASIC support different the number of DPM levels, we should avoid to show the invalid level value. v1 -> v2: follow the suggestion,clarifiy the description for this change Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Yuxian Dai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amdgpu: Adjust the SDMA doorbell info printingYong Zhao2-2/+2
Turn off the printing by default because it is not very useful, while adding more details. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amdkfd: Adjust three kfd dmesg printings during initializationYong Zhao2-3/+1
Delete two printings which are not very useful, and change one from pr_info() to pr_debug(). Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: fix bug in the logic for panel power controlAnthony Koo1-1/+1
[Why] there's a bug in the new logic for panel power control. the check is wrong, and will skip panel power control under the wrong conditions. [How] fix to check for NULL panel_cntl Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Ashley Thomas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: Convert memory from cpu to fw endianness correctlyWyatt Wood1-27/+31
[Why] Current code does not guarantee the correct endianness of memory being copied to fw, specifically in the case where cpu isn't little endian. [How] Windows and Diags are always little endian, so we define a macro that does nothing. Linux already defines this macro and will do the correct endianness conversion. Signed-off-by: Wyatt Wood <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Anthony Koo <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: Fix green screen issue after suspendRodrigo Siqueira1-9/+29
[why] We have seen a green screen after resume from suspend in a Raven system connected with two displays (HDMI and DP) on X based system. We noticed that this issue is related to bad DCC metadata from user space which may generate hangs and consequently an underflow on HUBP. After taking a deep look at the code path we realized that after resume we try to restore the commit with the DCC enabled framebuffer but the framebuffer is no longer valid. [how] This problem was only reported on Raven based system and after suspend, for this reason, this commit adds a new parameter on fill_plane_dcc_attributes() to give the option of disabling DCC programmatically. In summary, for disabling DCC we first verify if is a Raven system and if it is in suspend; if both conditions are true we disable DCC temporarily, otherwise, it is enabled. Co-developed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: Adjust refactored dm for color management onlyStylon Wang3-14/+14
[Why] Commit cdde482caabf2adad47d23f0d1e235db2c4f2b7d is causing regression from changing the order of call sequence. [How] Keep the call sequence and take in extra dm state only if plane-level color management is enabled. Fixes: cdde482caabf2a ("drm/amd/display: Refactor color management to take dm plane state") Signed-off-by: Stylon Wang <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: access ABM from stream resource.Yongqiang Sun1-16/+23
[Why] Since ABM resource is mapped to stream res, all the ABM access should via stream res. [How] Get ABM instance from stream res instead of resource pool. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: blank dp stream before re-train the linkXiaodong Yan1-0/+12
[Why] When link loss happened, monitor can not light up if only re-train the link. [How] Blank all the DP streams on this link before re-train the link, and then unblank the stream Signed-off-by: Xiaodong Yan <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: DispalyPort: Write OUI only if panel supports itAurabindo Pillai1-0/+15
[why] Organizational Unit Identifier register is optional, and its presence is published via Down Stream Port Count register. Writing this register when not available will result in errors [how] Read this register and continue writing OUI only if the panel has the support advertised. Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: change from panel to panel cntlAnthony Koo16-249/+251
[Why] it doesn't represent panel specifically, it's more like the control logic for the panel [How] change from panel to panel cntl to make it a bit more clear Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: Add HW rotation cursor changes to dcn10Jaehyun Chung1-5/+13
[Why] HW rotation was enabled in DAL3 but hubp cursor calculations for HW roation were only added to dcn20. [How] Add hubp cursor position calculation changes to dcn10. Signed-off-by: Jaehyun Chung <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: Factor in immediate flip support into DLG calculationsNicholas Kazlauskas1-1/+1
[Why] We expect to be able to perform immediate flipping without having to recalculate and update all the watermarks. There are certain usecases today (1080p @ 90deg, 2160p @ 90deg) such that we get a urgency value of 0 for frac_urg_bw_flip because we're explicitly passing in a value of "false" for requiring immediate flip support into the DLG calculation. [How] Always pass in true into the calculation. With this we get a correct non-zero value for frac_urg_bw_flip. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: fix virtual signal dsc setupDmytro Laktyushkin1-1/+1
This prevents dpcd access on virtual links. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: destroy panel on link destructAnthony Koo1-0/+3
[Why] without destroy it is causing a memory leak [How] destroy panel on link destruct Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Wyatt Wood <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: dmcu wait loop calculation is incorrect in RVPaul Hsieh1-3/+0
[Why] Driver already get display clock from SMU base on MHz, but driver read again and mutiple 1000 cause wait loop value is overflow. [How] remove coding error Signed-off-by: Paul Hsieh <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: move panel power seq to new panel structAnthony Koo22-94/+572
[Why] panel power sequencer is currently just sitting in hwseq but it really it tied to internal panels [How] make a new panel struct to contain power sequencer code Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: make all backlight calls link basedAnthony Koo5-32/+33
[Why] Backlight adjustment is tied to a specific display. So make the calls target a link rather than making it a global state. [How] make all backlight calls link based Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: Cap certain DML values for Low Pix Clk on DCN2.1Sung Lee1-2/+10
[WHY] In certain conditions with low pixel clock, some values in DML may go past the max due to margining for latency hiding. This causes assertions to get hit. [HOW] If the pixel clock is low and some values are high, cap it to the max. Signed-off-by: Sung Lee <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: Various fixes for PSR on DMCUBWyatt Wood3-1/+51
[Why] - Driver does not recognize new definitions of psr states. - Internal tool is required for checking if psr is active. [How] - Parse psr state correctly so that driver will recognize psr state. - Add visual confirmation that psr is active using existing mechanisms. Signed-off-by: Wyatt Wood <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-22drm/amd/display: 3.2.81Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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