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2021-03-23drm/amdgpu: Verify bo size can fit framebuffer size on init.Mark Yacoub3-15/+65
To initialize the framebuffer, call drm_gem_fb_init_with_funcs which verifies that the BO size can fit the FB size by calculating the minimum expected size of each plane. The bug was caught using igt-gpu-tools test: kms_addfb_basic.too-high and kms_addfb_basic.bo-too-small Tested on ChromeOS Zork by turning on the display and running a YT video. === Changes from v1 === 1. Added new line under declarations. 2. Use C style comment. Cc: Alex Deucher <[email protected]> Cc: "Christian König" <[email protected]> Cc: Sean Paul <[email protected]> Signed-off-by: Mark Yacoub <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: remove duplicate include in dcn21 and gpioZhang Yunkai2-5/+0
'dce110_resource.h' included in 'dcn21_resource.c' is duplicated. 'hw_gpio.h' included in 'hw_factory_dce110.c' is duplicated. Signed-off-by: Zhang Yunkai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: remove duplicate include in amdgpu_dm.cZhang Yunkai1-1/+0
'drm/drm_hdcp.h' included in 'amdgpu_dm.c' is duplicated. It is also included in the 79th line. Signed-off-by: Zhang Yunkai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu/swsmu: fix error return code of smu_v11_0_set_allowed_mask()Jia-Ju Bai1-1/+3
When bitmap_empty() or feature->feature_num triggers an error, no error return code of smu_v11_0_set_allowed_mask() is assigned. To fix this bug, ret is assigned with -EINVAL as error return code. Reviewed-by: Evan Quan <[email protected]> Reported-by: TOTE Robot <[email protected]> Signed-off-by: Jia-Ju Bai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: Align cursor cache address to 2KBJoshua Aberback1-3/+2
[Why] The registers for the address of the cursor are aligned to 2KB, so all cursor surfaces also need to be aligned to 2KB. Currently, the provided cursor cache surface is not aligned, so we need a workaround until alignment is enforced by the surface provider. [How] - round up surface address to nearest multiple of 2048 - current policy is to provide a much bigger cache size than necessary,so this operation is safe Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: Revert dram_clock_change_latency for DCN2.1Sung Lee1-1/+1
[WHY & HOW] Using values provided by DF for latency may cause hangs in multi display configurations. Revert change to previous value. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Sung Lee <[email protected]> Reviewed-by: Haonan Wang <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: 3.2.126Aric Cyr1-1/+1
DC version 3.2.126 brings improvements in multiple areas. In summary, we highlight: - DMUB fixes - Firmware relase 0.0.55 - Expanded dmub_cmd documentation - Enhancements in DCN30 Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: Added multi instance support for panel controlJake Wang6-18/+33
[Why] Panel control always programs instance 0. With multi eDP we need to support multiple instances. [How] Use link index to set different instances for panel control. Refactored LVTMA control to support multiple instances. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Jake Wang <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: [FW Promotion] Release 0.0.55Anthony Koo1-39/+795
Add comments to better describe the function of different cmds and parameters in the dmub interface Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: Fixed read/write pointer issue for get dmub traceYongqiang Sun4-18/+13
[Why] Driver get wrap around dmub trace data due to read pointer being increased incorrectly when there are multiple interrupt queues with very short interval [How] Check read/write pointer before copying data from ring buffer Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: Fix warningQingqing Zhuo2-3/+12
[Why] - Wrong scope for ifdef - Missing struct description [How] Move ifdef and add comment Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: Read all the trace entry if it is not emptyYongqiang Sun1-5/+14
[Why] If interval of two interrupt from dmub outbox0 is too short, some event might be skipped [How] Compare read pointer and write pointer until all the event entry is processed Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: Enable pflip interrupt upon pipe enableQingqing Zhuo10-0/+37
[Why] pflip interrupt would not be enabled promptly if a pipe is disabled and re-enabled, causing flip_done timeout error during DP compliance tests [How] Enable pflip interrupt upon pipe enablement Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: Fix dmub trace event not update issueYongqiang Sun1-1/+1
[Why & How] Reference to read pointer which is incorrect. Change to reference to write pointer. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: Move define from internal header to dmub_cmd.hYongqiang Sun2-3/+14
[Why & How] Fix linux compile error Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: Fix typo when retrieving dppclk from UEFI configMartin Leung1-1/+1
[why] In some boot configurations we need to retrieve the currently UEFI-set dppclk, but there was a typo in the calculation [how] Fix typo to make dpp_clk calculate off dpp_clk divider instead of disp_clk Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Martin Leung <[email protected]> Reviewed-by: Sung Lee <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: Skip powerstate DC hw access if virtual dalMartin Leung1-0/+3
[Why] On baco-enabled systems running virtual dal, can get set power state when hw is not initialized [How] Skip DC hw part of setPowerState when hw not available Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Martin Leung <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/display: Enabled pipe harvesting in dcn30Dillon Varone1-0/+31
[Why & How] Ported logic from dcn21 for reading in pipe fusing to dcn30. Supported configurations are 1 and 6 pipes. Invalid fusing will revert to 1 pipe being enabled. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: Check if FB BAR is enabled for ROM readLijo Lazar1-0/+4
Some configurations don't have FB BAR enabled. Avoid reading ROM image from FB BAR region in such cases. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/pm: Remove min/max overload of pp_dpm_sclkLijo Lazar1-85/+0
To maintain consistency with legacy usage, remove min/max clock overload of pp_dpm_sclk node. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/pm: Enable pp_od_clk_voltage node on aldebaranLijo Lazar2-2/+78
Use pp_od_clk_voltage node to enable performance determinism and GFX clock min/max range for aldebaran. This is to avoid overload of pp_dpm_sclk and maintain consistency in user lib interfaces. Ex: To enable perf determinism at 900MHz max gfx clock 1) echo perf_determinism > /sys/bus/pci/devices/.../power_dpm_force_performance_level 2) echo s 1 900 > /sys/bus/pci/devices/.../pp_od_clk_voltage 3) echo c > /sys/bus/pci/devices/.../pp_od_clk_voltage Ex: To enable min 500MHz/max 900MHz gfx clocks 1) echo manual > "/sys/bus/pci/devices/.../power_dpm_force_performance_level" 2) echo s 0 500 > "/sys/bus/pci/devices/.../pp_od_clk_voltage" 3) echo s 1 900 > "/sys/bus/pci/devices/.../pp_od_clk_voltage” 4) echo c > "/sys/bus/pci/devices/.../pp_od_clk_voltage” Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: Set GTT_USWC flag to enable freesync v2Shashank Sharma1-3/+11
This patch sets 'AMDGPU_GEM_CREATE_CPU_GTT_USWC' as input parameter flag, during object creation of an imported DMA buffer. In absence of this flag: 1. Function amdgpu_display_supported_domains() doesn't add AMDGPU_GEM_DOMAIN_GTT as supported domain. 2. Due to which, Function amdgpu_display_user_framebuffer_create() refuses to create framebuffer for imported DMA buffers. 3. Due to which, AddFB() IOCTL fails. 4. Due to which, amdgpu_present_check_flip() check fails in DDX 5. Due to which DDX driver doesn't allow flips (goes to blitting) 6. Due to which setting Freesync/VRR property fails for PRIME buffers. So, this patch finally enables Freesync with PRIME buffer offloading. v2 (chk): instead of just checking the flag we copy it over if the exporter is an amdgpu device as well. Signed-off-by: Shashank Sharma <[email protected]> Signed-off-by: Christian König <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: clean-up unused variableShashank Sharma1-8/+0
Variable 'bp' seems to be unused residue from previous logic, and is not required anymore. Cc: Koenig Christian <[email protected]> Cc: Deucher Alexander <[email protected]> Signed-off-by: Shashank Sharma <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23Revert freesync video patches temporarilyAurabindo Pillai4-349/+35
This temporarily reverts freesync video patches since it causes regression with eDP displays. This patch is a squashed revert of the following patches: 6f59f229f8ed ("drm/amd/display: Skip modeset for front porch change") d10cd527f5e5 ("drm/amd/display: Add freesync video modes based on preferred modes") 0eb1af2e8205 ("drm/amd/display: Add module parameter for freesync video mode") Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdkfd: Fix UBSAN shift-out-of-bounds warningAnson Jacob1-2/+15
If get_num_sdma_queues or get_num_xgmi_sdma_queues is 0, we end up doing a shift operation where the number of bits shifted equals number of bits in the operand. This behaviour is undefined. Set num_sdma_queues or num_xgmi_sdma_queues to ULLONG_MAX, if the count is >= number of bits in the operand. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1472 Reported-by: Lyude Paul <[email protected]> Signed-off-by: Anson Jacob <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Tested-by: Lyude Paul <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: Increase PSP runtime TMR region sizeOak Zeng2-3/+3
Aldebaran uses more than 4M runtime TMR. The current hard coded 4M TMR is not big enough for Aldebaran. Increase it to 8M. v2: Only do 8M size for ALDEBARAN (Hawking) Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdkfd: apply uncached flag for aldebaranEric Huang1-1/+7
The flag is only applied on fine-grained memory. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Oak Zeng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: set snoop bit in pde/pte entries for A+AEric Huang1-0/+4
Page tables in vram mapping to cpu is changed from uncached to cached in A+A, the snoop bit in VM_CONTEXTx_PAGE_TABLE_BASE_ADDR/ PDE0s/PDE1s/PDE2s/PTE.TFs has to be set so gpuvm walker snoop page table data out of CPU cache. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: set CPU mapping of vram as cached for A+A modeEric Huang1-1/+4
New A+A HW supports cached vram mapped to cpu. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: harvest edc status when connected to host via xGMIDennis Li7-28/+107
When connected to a host via xGMI, system fatal errors may trigger warm reset, driver has no change to query edc status before reset. Therefore in this case, driver should harvest previous error loging registers during boot, instead of only resetting them. v2: 1. IP's ras_manager object is created when its ras feature is enabled, so change to query edc status after amdgpu_ras_late_init called 2. change to enable watchdog timer after finishing gfx edc init Signed-off-by: Dennis Li <[email protected]> Reivewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: Make noretry the default on AldebaranFelix Kuehling1-0/+1
This is needed for best machine learning performance. XNACK can still be enabled per-process if needed. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Philip Yang <[email protected]> Tested-by: Alex Sierra <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: update default timeout of Aldebaran SQ watchdogHarish Kasiviswanathan2-2/+9
Signed-off-by: Harish Kasiviswanathan <[email protected]> Reivewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/pm: add new data in metrics tableKenneth Feng4-18/+26
Export new data in the metrics table for gfx and memory utilization counter, and each hbm temperature as well. v2: change the metrics table version to v1.1 v3: fix the coding style v4: rebase against latest kernel Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: add psp RAP L0 check supportKevin Wang1-1/+9
add PSP RAP L0 check when RAP TA is loaded. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: change psp_rap_invoke() function return valueKevin Wang3-16/+22
RAP TA is an optional firmware. if it doesn’t exist, the driver should bypass psp_rap_invoke() function. 1. bypass psp_rap_invoke() when RAP TA is not loaded. 2. add new parameter (status) to query RAP TA status. (the status value is different with psp_ta_invoke(), 3. fix the 'rap_status' MThread critical problem. (used without lock) Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/pm: add aldebaran serial number supportKevin Wang1-0/+23
add aldebaran serial number support. (serial number from metrics table) Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: Let KFD use more VMIDs on AldebaranFelix Kuehling1-1/+2
When there is no graphics support, KFD can use more of the VMIDs. Graphics VMIDs are only used for video decoding/encoding and post processing. With two VCE engines, there is no reason to reserve more than 2 VMIDs for that. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: enable watchdog feature for SQ of aldebaranDennis Li8-0/+174
SQ's watchdog timer monitors forward progress, a mask of which waves caused the watchdog timeout is recorded into ras status registers and then trigger a system fatal error event. v2: 1. change *query_timeout_status to *query_sq_timeout_status. 2. move query_sq_timeout_status into amdgpu_ras_do_recovery. 3. add module parameters to enable/disable fatal error event and modify the watchdog timer. v3: 1. remove unused parameters of *enable_watchdog_timer Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: refine ras codes for GC utc of aldebaranDennis Li2-174/+97
The bank number of both VML2 and ATCL2 are changed to 8, so refine related codes to avoid defining long name arrays. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: add ras support for gfx of aldebaranDennis Li6-0/+1128
add edc counter/status reset and query functions for gfx block of aldebaran. v2: change to clear edc counter explicitly aldebaran hardware will not clear edc counter after driver reading them, so driver should clear them explicitly. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: add gc powerbrake support (v2)Kevin Wang3-0/+30
add GC power brake feature support for Aldebaran. v2: squash in fixes (Alex) Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: update TCP_CHAN_STEER_1 golden value for aldebaranHawking Zhang1-1/+1
The golden setting was changed recently. update to the latest one Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: add common gc golden settings for aldebaranHawking Zhang1-3/+6
golden settings that should be applied Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: apply gc v9_4_2 golden settings for aldebaranHawking Zhang3-1/+57
Those registers should be programmed as one-time initialization Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: restore aldebaran save ttmp and trap config on init (v2)Jonathan Kim4-0/+82
Initialization of TRAP_DATA0/1 is still required for the debugger to detect new waves on Aldebaran. Also, per-vmid global trap enablement may be required outside of debugger scope so move to init phase. v2: just add the gfx 9.4.2 changes (Alex) Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdkfd: add aldebaran kfd2kgd callbacks to kfd device (v2)Jonathan Kim5-10/+88
Create dedicated Aldebaran kfd2kgd callbacks to prepare for new per-vmid register instructions for debug trap setting functions and sending host traps. v2: rebase (Alex) Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Oak Zeng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdkfd: Check HIQ's MQD for queue preemption statusOak Zeng7-16/+66
MEC firmware can silently fail the queue preemption request without time out. In this case, HIQ's MQD's queue_doorbell_id will be set. Check this field to see whether last queue preemption was successful or not. Signed-off-by: Oak Zeng <[email protected]> Suggested-by: Jay Cornwall <[email protected]> Acked-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdkfd: Add kernel parameter to stop queue eviction on vm faultOak Zeng4-4/+18
This is to keep wavefront context for debug purpose Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: allow use psp to load firmware (v2)Hawking Zhang1-2/+1
Match existing asics. v2: rebase (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/pm: Enable user min/max gfxclk on aldebaranLijo Lazar1-1/+8
Aldebaran has fine grained DPM for GFXCLK. Instead of a discrete level, user can specify a min/max range of GFXCLK for any profiling/tuning purpose.This option is available only in manual performance level mode. Select "manual" as power_dpm_force_performance_level and specify the min/max range using pp_dpm_sclk sysfs node. User cannot specify a min/max range outside of the default min/max range of the ASIC. If specified outside the range, values will be bound by the default min/max range. Ex: To use gfxclk min = 600MHz and max = 900MHz echo manual > /sys/bus/pci/devices/.../power_dpm_force_performance_level echo min 600 max 900 > /sys/bus/pci/devices/.../pp_dpm_sclk Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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