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2020-01-21Merge tag 'zynqmp-soc-for-v5.6' of https://github.com/Xilinx/linux-xlnx into ↵Olof Johansson5-17/+201
arm/drivers arm64: soc: ZynqMP SoC changes for v5.6 - Extend firmware interface for feature checking - Use mailbox for communication with firmware for power management * tag 'zynqmp-soc-for-v5.6' of https://github.com/Xilinx/linux-xlnx: drivers: soc: xilinx: Use mailbox IPI callback dt-bindings: power: reset: xilinx: Add bindings for ipi mailbox drivers: firmware: xilinx: Add support for feature check Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-21drivers: soc: xilinx: Use mailbox IPI callbackTejas Patel2-14/+112
Add support for init suspend callback through mailbox IPI callback. Signed-off-by: Tejas Patel <[email protected]> Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2020-01-21dt-bindings: power: reset: xilinx: Add bindings for ipi mailboxRajan Vaja1-3/+39
Add IPI mailbox property and its example in xilinx zynqmp-power documentation. Signed-off-by: Rajan Vaja <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2020-01-20Merge tag 'v5.5-next-soc' of ↵Olof Johansson5-28/+205
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers cmdq: - clean ups of unused code and debuggability - add cmdq_instruction to make the function call interface more readable - add functions for polling and providing info for the user of cmdq scpsys: - add bindings for MT6765 * tag 'v5.5-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: dt-bindings: mediatek: add MT6765 power dt-bindings soc: mediatek: cmdq: delete not used define soc: mediatek: cmdq: add cmdq_dev_get_client_reg function soc: mediatek: cmdq: add polling function soc: mediatek: cmdq: define the instruction struct soc: mediatek: cmdq: remove OR opertaion from err return Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-20Merge tag 'arm-soc/for-5.6/maintainers' of ↵Olof Johansson1-0/+4
https://github.com/Broadcom/stblinux into arm/drivers This pull request contains Broadcom SoCs MAINTAINERS file updates for 5.6, please pull the following: - Nicolas adds an entry for the Broadcom STB PCIe Root Complex files for both BCM7xxx (actual STB SoCs) and BCM2711 (Raspberry Pi 4). * tag 'arm-soc/for-5.6/maintainers' of https://github.com/Broadcom/stblinux: MAINTAINERS: Add brcmstb PCIe controller entry Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-19drivers: soc: ti: knav_qmss_queue: Pass lockdep expression to RCU listsAmol Grover1-2/+5
inst->handles is traversed using list_for_each_entry_rcu outside an RCU read-side critical section but under the protection of knav_dev_lock. Hence, add corresponding lockdep expression to silence false-positive lockdep warnings, and harden RCU lists. Add macro for the corresponding lockdep expression. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Amol Grover <[email protected]> Acked-by: Santosh Shilimkar <[email protected]> Signed-off-by: Olof Johansson <[email protected]>
2020-01-17MAINTAINERS: Add brcmstb PCIe controller entryNicolas Saenz Julienne1-0/+4
The controller serves both the Raspberry Pi 4 (bcm2711) and brcmstb platforms. Signed-off-by: Nicolas Saenz Julienne <[email protected]> Signed-off-by: Florian Fainelli <[email protected]>
2020-01-17Merge tag 'drivers_soc_for_5.6' of ↵Olof Johansson5-0/+1472
git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into arm/drivers SOC: TI Keystone Ring Accelerator driver The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs. * tag 'drivers_soc_for_5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: soc: ti: k3: add navss ringacc driver bindings: soc: ti: add documentation for k3 ringacc Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-16Merge tag 'omap-for-v5.6/ti-sysc-signed' of ↵Olof Johansson2-9/+10
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/drivers ti-sysc driver changes for omaps for v5.6 merge window Few changes to implement quirk handling for cases where we need to block clockdomain autoidle, drop old MMU specific quirks, and simplify the return code for sysc_init_resets(). * tag 'omap-for-v5.6/ti-sysc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: bus: ti-sysc: Use PTR_ERR_OR_ZERO() to simplify code bus: ti-sysc: Drop MMU quirks bus: ti-sysc: Implement quirk handling for CLKDM_NOAUTO Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-16Merge tag 'qcom-drivers-for-5.6' of ↵Olof Johansson16-1741/+1504
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers Qualcomm driver updates for v5.6 * SCM major refactoring and cleanup * Properly flag active only power domains as active only * Add SC7180 and SM8150 RPMH power domains * Return EPROBE_DEFER from QMI if packet family is not yet available * tag 'qcom-drivers-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (27 commits) firmware: qcom_scm: Dynamically support SMCCC and legacy conventions firmware: qcom_scm: Remove thin wrappers firmware: qcom_scm: Order functions, definitions by service/command firmware: qcom_scm-32: Add device argument to atomic calls firmware: qcom_scm-32: Create common legacy atomic call firmware: qcom_scm-32: Move SMCCC register filling to qcom_scm_call firmware: qcom_scm-32: Use qcom_scm_desc in non-atomic calls firmware: qcom_scm-32: Add funcnum IDs firmware: qcom_scm-32: Use SMC arch wrappers firmware: qcom_scm-64: Improve SMC convention detection firmware: qcom_scm-64: Move SMC register filling to qcom_scm_call_smccc firmware: qcom_scm-64: Add SCM results struct firmware: qcom_scm-64: Move svc/cmd/owner into qcom_scm_desc firmware: qcom_scm-64: Make SMC macros less magical firmware: qcom_scm: Remove unused qcom_scm_get_version firmware: qcom_scm: Apply consistent naming scheme to command IDs firmware: qcom_scm: Rename macros and structures soc: qcom: rpmhpd: Set 'active_only' for active only power domains firmware: scm: Add stubs for OCMEM and restore_sec_cfg_available dt-bindings: power: rpmpd: Convert rpmpd bindings to yaml ... Link: https://lore.kernel.org/r/20200113204405.GD3325@yoga Signed-off-by: Olof Johansson <[email protected]>
2020-01-16Merge tag 'soc-fsl-next-v5.6' of ↵Olof Johansson33-1128/+775
git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/drivers NXP/FSL SoC driver updates for v5.6 QUICC Engine drivers - Improve the QE drivers to be compatible with ARM/ARM64/PPC64 architectures - Various cleanups to the QE drivers * tag 'soc-fsl-next-v5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux: (49 commits) soc: fsl: qe: remove set but not used variable 'mm_gc' soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE soc: fsl: qe: remove unused #include of asm/irq.h from ucc.c net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32 net/wan/fsl_ucc_hdlc: reject muram offsets above 64K net/wan/fsl_ucc_hdlc: fix reading of __be16 registers net/wan/fsl_ucc_hdlc: avoid use of IS_ERR_VALUE() soc: fsl: qe: avoid IS_ERR_VALUE in ucc_fast.c soc: fsl: qe: drop pointless check in qe_sdma_init() soc: fsl: qe: drop use of IS_ERR_VALUE in qe_sdma_init() soc: fsl: qe: avoid IS_ERR_VALUE in ucc_slow.c soc: fsl: qe: refactor cpm_muram_alloc_common to prevent BUG on error path soc: fsl: qe: drop broken lazy call of cpm_muram_init() soc: fsl: qe: make cpm_muram_free() ignore a negative offset soc: fsl: qe: make cpm_muram_free() return void soc: fsl: qe: change return type of cpm_muram_alloc() to s32 serial: ucc_uart: access __be32 field using be32_to_cpu serial: ucc_uart: limit brg-frequency workaround to PPC32 serial: ucc_uart: use of_property_read_u32() in ucc_uart_probe() serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32 ... Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-16Merge tag 'imx-driver-5.6' of ↵Olof Johansson3-2/+11
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers i.MX driver changes for 5.6: - Add i.MX8MP SoC driver support. - Allow IMX DSP Protocol driver to be built as module. - Add COMPILE_TEST for IMX_SCU_SOC driver to increase build coverage. - Print SoC type and revision in i.MX8 SoC driver, as this is useful information to have when looking through boot log. * tag 'imx-driver-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: firmware: imx: Allow IMX DSP to be selected as module soc: imx: Enable compile testing of IMX_SCU_SOC soc: imx: Add i.MX8MP SoC driver support soc: imx8: print SoC type and revision Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-16Merge tag 'mvebu-drivers-5.6-1' of git://git.infradead.org/linux-mvebu into ↵Olof Johansson4-10/+4
arm/drivers mvebu drivers for 5.6 (part 1) - Various cleanup on the following drivers: - Turris Mox rWTM firmware - Moxtet bus - Armada 37xx rWTM mailbox - Marvell EBU Device Bus * tag 'mvebu-drivers-5.6-1' of git://git.infradead.org/linux-mvebu: mailbox: armada-37xx-rwtm: convert to devm_platform_ioremap_resource memory: mvebu-devbus: convert to devm_platform_ioremap_resource bus: moxtet: declare moxtet_bus_type as static firmware: turris-mox-rwtm: small white space cleanup Link: https://lore.kernel.org/r/877e1x3nxc.fsf@FE-laptop Signed-off-by: Olof Johansson <[email protected]>
2020-01-16Merge tag 'tegra-for-5.6-soc' of ↵Olof Johansson7-15/+70
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers soc: tegra: Changes for v5.6-rc1 This adds a couple of optimizations to how the chip ID and straps are read and adds support for the FUSE block on Tegra194. Included is also a small optimization for the coupled regulator driver to abort early if no voltage change has occurred. * tag 'tegra-for-5.6-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: fuse: Unmap registers once they are not needed anymore soc/tegra: fuse: Correct straps' address for older Tegra124 device trees soc/tegra: fuse: Warn if straps are not ready soc/tegra: fuse: Cache values of straps and Chip ID registers soc/tegra: regulators: Do nothing if voltage is unchanged soc/tegra: fuse: Add APB DMA dependency for Tegra20 soc/tegra: fuse: Add Tegra194 support Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-16Merge tag 'tegra-for-5.6-memory' of ↵Olof Johansson7-149/+1928
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers memory: tegra: Changes for v5.6-rc1 This adds a couple of fixes for the Tegra30 EMC frequency scaling code and adds support for EMC frequency scaling on Tegra186 and later. * tag 'tegra-for-5.6-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra30-emc: Correct error message for timed out auto calibration memory: tegra30-emc: Firm up hardware programming sequence memory: tegra30-emc: Firm up suspend/resume sequence memory: tegra: Correct reset value of xusb_hostr memory: tegra: Add support for the Tegra194 memory controller memory: tegra: Only include support for enabled SoCs memory: tegra: Support DVFS on Tegra186 and later memory: tegra: Add system sleep support memory: tegra: Extract memory client SID programming memory: tegra: Add per-SoC data for Tegra186 memory: tegra: Rename tegra_mc to tegra186_mc on Tegra186 memory: tegra: Implement EMC debugfs interface on Tegra30 memory: tegra: Implement EMC debugfs interface on Tegra20 memory: tegra: Refashion EMC debugfs interface on Tegra124 Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-16Merge tag 'tegra-for-5.6-bus' of ↵Olof Johansson1-1/+0
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers bus: tegra: Changes for v5.6-rc1 Contains a single fix to remove a Kconfig dependency that's no longer required. * tag 'tegra-for-5.6-bus' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: bus: tegra-aconnect: Remove PM_CLK dependency Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-15soc: ti: k3: add navss ringacc driverGrygorii Strashko4-0/+1413
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs. The RINGACC converts constant-address read and write accesses to equivalent read or write accesses to a circular data structure in memory. The RINGACC eliminates the need for each DMA controller which needs to access ring elements from having to know the current state of the ring (base address, current offset). The DMA controller performs a read or write access to a specific address range (which maps to the source interface on the RINGACC) and the RINGACC replaces the address for the transaction with a new address which corresponds to the head or tail element of the ring (head for reads, tail for writes). Since the RINGACC maintains the state, multiple DMA controllers or channels are allowed to coherently share the same rings as applicable. The RINGACC is able to place data which is destined towards software into cached memory directly. Supported ring modes: - Ring Mode - Messaging Mode - Credentials Mode - Queue Manager Mode TI-SCI integration: Texas Instrument's System Control Interface (TI-SCI) Message Protocol now has control over Ringacc module resources management (RM) and Rings configuration. The corresponding support of TI-SCI Ringacc module RM protocol introduced as option through DT parameters: - ti,sci: phandle on TI-SCI firmware controller DT node - ti,sci-dev-id: TI-SCI device identifier as per TI-SCI firmware spec if both parameters present - Ringacc driver will configure/free/reset Rings using TI-SCI Message Ringacc RM Protocol. The Ringacc driver manages Rings allocation by itself now and requests TI-SCI firmware to allocate and configure specific Rings only. It's done this way because, Linux driver implements two stage Rings allocation and configuration (allocate ring and configure ring) while TI-SCI Message Protocol supports only one combined operation (allocate+configure). Signed-off-by: Grygorii Strashko <[email protected]> Signed-off-by: Peter Ujfalusi <[email protected]> Reviewed-by: Tero Kristo <[email protected]> Tested-by: Keerthy <[email protected]> Signed-off-by: Santosh Shilimkar <[email protected]>
2020-01-15bindings: soc: ti: add documentation for k3 ringaccGrygorii Strashko1-0/+59
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x and j721e. This patch introduces RINGACC device tree bindings. Signed-off-by: Grygorii Strashko <[email protected]> Signed-off-by: Peter Ujfalusi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Tested-by: Keerthy <[email protected]> Signed-off-by: Santosh Shilimkar <[email protected]>
2020-01-10Merge tag 'samsung-drivers-5.6' of ↵Olof Johansson13-27/+22
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers Samsung soc drivers changes for v5.6 1. Convert to managed (devm_x()) versions, 2. Cleanups (Samsung and Exynos names). * tag 'samsung-drivers-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: memory: samsung: Rename Exynos to lowercase soc: samsung: Rename Samsung and Exynos to lowercase memory: samsung: exynos5422-dmc: Convert to devm_platform_ioremap_resource soc: samsung: exynos-pmu: Convert to devm_platform_ioremap_resource Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-10Merge tag 'reset-for-5.6' of git://git.pengutronix.de/pza/linux into arm/driversOlof Johansson12-23/+937
Reset controller updates for v5.6 This tag adds support for the Nuvoton NPCM, Intel Gatway SoC, and Broadcom BCM7216 RESCAL reset controllers, adds missing SCSSI reset controls for newer Uniphier SoCs, aligns the program flow in the devm_reset_controller_register, __devm_reset_control_get, and devm_reset_control_array_get functions for better consistency, and allows to build the Qcom AOSS reset driver as a module. This is based on v5.5-rc3 because the core patch depends on commit db23808615e2 ("reset: Do not register resource data for missing resets"). * tag 'reset-for-5.6' of git://git.pengutronix.de/pza/linux: reset: qcom-aoss: Allow CONFIG_RESET_QCOM_AOSS to be a tristate reset: Add Broadcom STB RESCAL reset controller dt-bindings: reset: Document BCM7216 RESCAL reset controller reset: intel: Add system reset controller driver dt-bindings: reset: Add YAML schemas for the Intel Reset controller reset: uniphier: Add SCSSI reset control for each channel reset: Align logic and flow in managed helpers reset: npcm: add NPCM reset controller driver dt-bindings: reset: Add binding constants for NPCM7xx reset controller dt-bindings: reset: add NPCM reset controller documentation Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-10Merge tag 'arm-soc/for-5.6/drivers' of https://github.com/Broadcom/stblinux ↵Olof Johansson1-8/+22
into arm/drivers This pull request contains Broadcom ARM/ARM64/MIPS-based SoCs drivers changes for 5.6, please pull the following: - Florian provides a set of updates to the Bus Interface Unit control to tune it appropriately for the most recent chips: 7255, 7260, 7216, 7211 * tag 'arm-soc/for-5.6/drivers' of https://github.com/Broadcom/stblinux: soc: bcm: brcmstb: biuctrl: Update programming for 7211 soc: bcm: brcmstb: biuctrl: Update layout for A72 on 7211 soc: bcm: brcmstb: biuctrl: Tune interface for 7255 and 7216 soc: bcm: brcmstb: biuctrl: Tune 7260 BIU interface Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-10soc/tegra: fuse: Unmap registers once they are not needed anymoreDmitry Osipenko1-4/+8
Both Chip ID and strapping registers are now read out during of APB MISC initialization, the registers' mapping isn't needed anymore once registers are read. Hence let's unmap registers once they are not needed anymore, for consistency. Suggested-by: Michał Mirosław <[email protected]> Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-01-10soc/tegra: fuse: Correct straps' address for older Tegra124 device treesDmitry Osipenko1-1/+1
Trying to read out Chip ID before APBMISC registers are mapped won't succeed, in a result Tegra124 gets a wrong address for the HW straps register if machine uses an old outdated device tree. Fixes: 297c4f3dcbff ("soc/tegra: fuse: Restrict legacy code to 32-bit ARM") Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-01-10soc/tegra: fuse: Warn if straps are not readyDmitry Osipenko1-1/+3
Now both Chip ID and HW straps are becoming available at the same time, thus we could simply check the availability of the ID in order to check the availability of the straps. We couldn't check straps for 0x0 because it could be a correct value. This change didn't uncover any problems, but anyways it is nicer to have straps verified for consistency with the Chip ID verification. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-01-10soc/tegra: fuse: Cache values of straps and Chip ID registersDmitry Osipenko1-11/+10
There is no need to re-read Chip ID and HW straps out from hardware each time, it is a bit nicer to cache the values in memory. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-01-10memory: tegra30-emc: Correct error message for timed out auto calibrationDmitry Osipenko1-2/+1
The code waits for auto calibration to be finished and not to be disabled. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-01-10memory: tegra30-emc: Firm up hardware programming sequenceDmitry Osipenko1-61/+89
Previously there was a problem where a late handshake handling caused a memory corruption, this problem was resolved by issuing calibration command right after changing the timing, but looks like the solution wasn't entirely correct since calibration interval could be disabled as well. Now programming sequence is completed immediately after receiving handshake from CaR, without potentially long delays and in accordance to the TRM's programming guide. Secondly, the TRM's programming guide suggests to flush EMC writes by reading any *MC* register before doing CaR changes. This is also addressed now. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-01-10memory: tegra30-emc: Firm up suspend/resume sequenceDmitry Osipenko1-18/+20
The current code doesn't prevent race conditions of suspend/resume vs CCF. Let's take exclusive control over the EMC clock during suspend in a way that is free from race conditions. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-01-10soc/tegra: regulators: Do nothing if voltage is unchangedDmitry Osipenko2-1/+13
There is no need to re-apply the same voltage. This change is just a minor cleanup. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-01-10memory: tegra: Correct reset value of xusb_hostrNicolin Chen1-1/+1
According to Tegra X1 (Tegra210) TRM, the reset value of xusb_hostr field (bit [7:0]) should be 0x7a. So this patch simply corrects it. Signed-off-by: Nicolin Chen <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-01-10soc/tegra: fuse: Add APB DMA dependency for Tegra20Dmitry Osipenko1-0/+1
Tegra20 FUSE driver depends on DMA channel presence, otherwise it fails to probe. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-01-10bus: tegra-aconnect: Remove PM_CLK dependencySameer Pujar1-1/+0
The ACONNECT bus driver does not use pm-clk interface anymore and hence the dependency can be removed from its Kconfig option. Fixes: 0d7dab926130 ("bus: tegra-aconnect: use devm_clk_*() helpers") Signed-off-by: Sameer Pujar <[email protected]> Acked-by: Jon Hunter <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-01-10Merge branch 'v5.5-next/cmdq-stable' into v5.5-next/socMatthias Brugger3-26/+185
2020-01-10dt-bindings: mediatek: add MT6765 power dt-bindingsMars Cheng2-0/+20
This adds power dt-bindings for MT6765 Signed-off-by: Mars Cheng <[email protected]> Signed-off-by: Owen Chen <[email protected]> Signed-off-by: Macpaul Lin <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Matthias Brugger <[email protected]>
2020-01-10soc: mediatek: cmdq: delete not used defineMatthias Brugger1-2/+0
Define CMDQ_EOC_CMD was actually never used. Delete it. Signed-off-by: Matthias Brugger <[email protected]> Reviewed-by: Bibby Hsieh <[email protected]> Reviewed-by: CK Hu <[email protected]> Signed-off-by: Matthias Brugger <[email protected]>
2020-01-09memory: tegra: Add support for the Tegra194 memory controllerThierry Reding3-0/+953
The memory and external memory controllers on Tegra194 are very similar to their predecessors from Tegra186. Add the necessary SoC-specific data to support the newer versions. Signed-off-by: Thierry Reding <[email protected]>
2020-01-09memory: tegra: Only include support for enabled SoCsThierry Reding2-0/+8
The memory client tables can be fairly large and they can easily be omitted if support for the corresponding SoC is not enabled. Signed-off-by: Thierry Reding <[email protected]>
2020-01-09memory: tegra: Support DVFS on Tegra186 and laterThierry Reding3-3/+304
Add a Tegra186 (and later) EMC driver that reads the EMC DVFS tables from BPMP and uses the EMC clock to change the external memory clock. This currently only provides a debugfs interface to show the available frequencies and set lower and upper limits of the allowed range. This can be used for testing the various frequencies. The goal is to eventually integrate this with the interconnect framework so that the EMC frequency can be scaled based on demand from memory clients. Signed-off-by: Thierry Reding <[email protected]>
2020-01-09soc/tegra: fuse: Add Tegra194 supportJC Kuo4-0/+37
This commit adds Tegra194 fuse/apbmisc support. Signed-off-by: JC Kuo <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-01-09memory: tegra: Add system sleep supportThierry Reding1-0/+19
Add system suspend/resume support for the memory controller found on Tegra186 and later. This is required so that the SID registers can be reprogrammed after their content was lost during system sleep. Signed-off-by: Thierry Reding <[email protected]>
2020-01-09memory: tegra: Extract memory client SID programmingThierry Reding1-22/+27
Move programming of the memory client to SID mapping into a separate function so that it can be reused from multiple call sites. Signed-off-by: Thierry Reding <[email protected]>
2020-01-09memory: tegra: Add per-SoC data for Tegra186Thierry Reding1-10/+19
Instead of hard-coding the memory client table, use per-SoC data in preparation for adding support for other SoCs. Signed-off-by: Thierry Reding <[email protected]>
2020-01-09memory: tegra: Rename tegra_mc to tegra186_mc on Tegra186Thierry Reding1-4/+10
This is just for consistency with the rest of the driver. Signed-off-by: Thierry Reding <[email protected]>
2020-01-09memory: tegra: Implement EMC debugfs interface on Tegra30Thierry Reding1-0/+173
A common debugfs interface is already available on Tegra20, Tegra124, Tegra186 and Tegra194. Implement the same interface on Tegra30 to enable testing of the EMC frequency scaling code using a unified interface. Signed-off-by: Thierry Reding <[email protected]>
2020-01-09memory: tegra: Implement EMC debugfs interface on Tegra20Thierry Reding1-0/+175
A common debugfs interface is already available on Tegra124, Tegra186 and Tegra194. Implement the same interface on Tegra20 to enable testing of the EMC frequency scaling code using a unified interface. Signed-off-by: Thierry Reding <[email protected]>
2020-01-09memory: tegra: Refashion EMC debugfs interface on Tegra124Thierry Reding1-42/+143
The current debugfs interface is only partially useful. While it allows listing supported frequencies and testing individual clock rates, it is limited in that it can't be used to restrict the range of frequencies that the driver is allowed to set. This is something we may want to use to test adaptive scaling once that's implemented. Signed-off-by: Thierry Reding <[email protected]>
2020-01-09firmware: imx: Allow IMX DSP to be selected as moduleDaniel Baluta1-1/+1
IMX DSP is only needed by SOF or any other module that wants to communicate with the DSP. When SOF is build as a module IMX DSP is forced to be built inside the kernel image. This is not optimal, so allow IMX DSP to be built as a module. Signed-off-by: Daniel Baluta <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-01-09soc: imx: Enable compile testing of IMX_SCU_SOCKrzysztof Kozlowski1-1/+1
IMX_SCU_SOC can be compile tested to increase build coverage. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-01-09soc: imx: Add i.MX8MP SoC driver supportAnson Huang1-0/+6
Add i.MX8MP SoC driver support: root@imx8mpevk:~# cat /sys/devices/soc0/family Freescale i.MX root@imx8mpevk:~# cat /sys/devices/soc0/machine FSL i.MX8MP EVK root@imx8mpevk:~# cat /sys/devices/soc0/soc_id i.MX8MP root@imx8mpevk:~# cat /sys/devices/soc0/revision 1.0 Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-01-08soc: fsl: qe: remove set but not used variable 'mm_gc'YueHaibing1-2/+0
drivers/soc/fsl/qe/gpio.c: In function qe_pin_request: drivers/soc/fsl/qe/gpio.c:163:26: warning: variable mm_gc set but not used [-Wunused-but-set-variable] commit 1e714e54b5ca ("powerpc: qe_lib-gpio: use gpiochip data pointer") left behind this unused variable. Reported-by: Hulk Robot <[email protected]> Signed-off-by: Chen Zhou <[email protected]> Signed-off-by: YueHaibing <[email protected]> Signed-off-by: Li Yang <[email protected]>
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