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2020-01-08Merge tag 'cpuidle_psci-v5.5-rc4' of ↵Olof Johansson642-3472/+7975
git://git.linaro.org/people/ulf.hansson/linux-pm into arm/drivers Initial support for hierarchical CPU arrangement, managed by PSCI and its corresponding cpuidle driver. This support is based upon using the generic PM domain, which already supports devices belonging to CPUs. Finally, these is a DTS patch that enables the hierarchical topology to be used for the Qcom 410c Dragonboard, which supports the PSCI OS-initiated mode. * tag 'cpuidle_psci-v5.5-rc4' of git://git.linaro.org/people/ulf.hansson/linux-pm: (611 commits) arm64: dts: Convert to the hierarchical CPU topology layout for MSM8916 cpuidle: psci: Add support for PM domains by using genpd PM / Domains: Introduce a genpd OF helper that removes a subdomain cpuidle: psci: Support CPU hotplug for the hierarchical model cpuidle: psci: Manage runtime PM in the idle path cpuidle: psci: Prepare to use OS initiated suspend mode via PM domains cpuidle: psci: Attach CPU devices to their PM domains cpuidle: psci: Add a helper to attach a CPU to its PM domain cpuidle: psci: Support hierarchical CPU idle states cpuidle: psci: Simplify OF parsing of CPU idle state nodes cpuidle: dt: Support hierarchical CPU idle states of: base: Add of_get_cpu_state_node() to get idle states for a CPU node firmware: psci: Export functions to manage the OSI mode dt: psci: Update DT bindings to support hierarchical PSCI states cpuidle: psci: Align psci_power_state count with idle state count Linux 5.5-rc4 locks: print unsigned ino in /proc/locks riscv: export flush_icache_all to modules riscv: reject invalid syscalls below -1 riscv: fix compile failure with EXPORT_SYMBOL() & !MMU ... Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-08soc: mediatek: cmdq: add cmdq_dev_get_client_reg functionBibby Hsieh2-0/+50
GCE cannot know the register base address, this function can help cmdq client to get the cmdq_client_reg structure. Signed-off-by: Bibby Hsieh <[email protected]> Reviewed-by: CK Hu <[email protected]> Reviewed-by: Houlong Wei <[email protected]> Signed-off-by: Matthias Brugger <[email protected]>
2020-01-08soc: mediatek: cmdq: add polling functionBibby Hsieh3-0/+69
add polling function in cmdq helper functions Signed-off-by: Bibby Hsieh <[email protected]> Reviewed-by: CK Hu <[email protected]> Signed-off-by: Matthias Brugger <[email protected]>
2020-01-08soc: mediatek: cmdq: define the instruction structBibby Hsieh2-24/+59
Define an instruction structure for gce driver to append command. This structure can make the client's code more readability. Signed-off-by: Bibby Hsieh <[email protected]> Reviewed-by: CK Hu <[email protected]> Signed-off-by: Matthias Brugger <[email protected]>
2020-01-08soc: mediatek: cmdq: remove OR opertaion from err returnBibby Hsieh1-3/+8
Debugging gets harder if we OR two error return values. Return each error on it's own instead Signed-off-by: Bibby Hsieh <[email protected]> Reviewed-by: CK Hu <[email protected]> [mb: rephrase commit message] Signed-off-by: Matthias Brugger <[email protected]>
2020-01-08mailbox: armada-37xx-rwtm: convert to devm_platform_ioremap_resourceYangtao Li1-4/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2020-01-08memory: mvebu-devbus: convert to devm_platform_ioremap_resourceYangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2020-01-08bus: moxtet: declare moxtet_bus_type as staticMarek Behún1-2/+1
This symbol is not meant to be used from elsewhere. Cc: Ben Dooks <[email protected]> Cc: Christoph Hellwig <[email protected]> Cc: Gregory CLEMENT <[email protected]> Signed-off-by: Marek Behún <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2020-01-08firmware: turris-mox-rwtm: small white space cleanupDan Carpenter1-1/+1
This patch deletes a stray tab. Cc: Gregory CLEMENT <[email protected]> Cc: Colin King <[email protected]> Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Marek Behún <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2020-01-08reset: qcom-aoss: Allow CONFIG_RESET_QCOM_AOSS to be a tristateJohn Stultz2-2/+3
Allow CONFIG_RESET_QCOM_AOSS to be set as as =m to allow for the driver to be loaded from a modules. Also replaces the builtin_platform_driver() line with module_platform_driver() and adds a MODULE_DEVICE_TABLE() entry. Cc: Todd Kjos <[email protected]> Cc: Alistair Delva <[email protected]> Cc: Amit Pundir <[email protected]> Signed-off-by: John Stultz <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Philipp Zabel <[email protected]>
2020-01-07firmware: qcom_scm: Dynamically support SMCCC and legacy conventionsElliot Berman6-135/+176
Dynamically support SMCCCC and legacy conventions by detecting which convention to use at runtime. qcom_scm_call_atomic and qcom_scm_call can then be moved in qcom_scm.c and use underlying convention backend as appropriate. Thus, rename qcom_scm-64,-32 to reflect that they are backends for -smc and -legacy, respectively. Also add support for making SCM calls earlier than when SCM driver probes to support use cases such as qcom_scm_set_cold_boot_addr. Support is added by lazily initializing the convention and guarding the query with a spin lock. The limitation of these early SCM calls is that they cannot use DMA, as in the case of >4 arguments for SMC convention and any non-atomic call for legacy convention. Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07firmware: qcom_scm: Remove thin wrappersElliot Berman4-948/+428
qcom_scm-32 and qcom_scm-64 implementations are nearly identical, so make qcom_scm_call and qcom_scm_call_atomic unique to each and the SCM descriptor creation common to each. There are the following catches: - __qcom_scm_is_call_available is still in each -32,-64 implementation as the argument is unique to each convention - For some functions, only one implementation was provided in -32 or -64. The actual implementation was moved into qcom_scm.c - io_writel and io_readl in -64 were non-atomic calls and in -32 they were. Atomic is the better option, so use it. Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07firmware: qcom_scm: Order functions, definitions by service/commandElliot Berman3-304/+315
Definitions throughout qcom_scm are loosely grouped and loosely ordered. Sort all the functions/definitions by service ID/command ID to improve sanity when needing to add new functionality to this driver. Acked-by: Bjorn Andersson <[email protected]> Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07firmware: qcom_scm-32: Add device argument to atomic callsElliot Berman4-14/+19
Add unused "device" parameter to reduce merge friction between SMCCC and legacy based conventions in an upcoming patch. Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07firmware: qcom_scm-32: Create common legacy atomic callElliot Berman1-38/+68
Per [1], legacy calling convention supports up to 5 arguments and 3 return values. Create one function to support this combination, and remove the original "atomic1" and "atomic2" variants for 1 and 2 arguments. This more closely aligns scm_legacy implementation with scm_smc implementation. [1]: https://source.codeaurora.org/quic/la/kernel/msm-4.9/tree/drivers/soc/qcom/scm.c?h=kernel.lnx.4.9.r28-rel#n1024 Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07firmware: qcom_scm-32: Move SMCCC register filling to qcom_scm_callElliot Berman1-12/+24
Move SMCCC register filling to qcom_scm_call so that __scm_legacy_do only needs to concern itself with retry mechanism. qcom_scm_call then is responsible for translating qcom_scm_desc into the complete set of register arguments and passing onto qcom_scm_call_do. Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07firmware: qcom_scm-32: Use qcom_scm_desc in non-atomic callsElliot Berman1-149/+218
Use qcom_scm_desc in non-atomic calls to remove legacy convention details from every SCM wrapper function. Implementations were copied from qcom_scm-64 and are functionally equivalent when using the qcom_scm_desc and qcom_scm_res structs. Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07firmware: qcom_scm-32: Add funcnum IDsElliot Berman1-3/+5
Add SCM_LEGACY_FNID macro to qcom_scm-32. Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07firmware: qcom_scm-32: Use SMC arch wrappersElliot Berman2-55/+17
Use SMC arch wrappers instead of inline assembly. Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07firmware: qcom_scm-64: Improve SMC convention detectionElliot Berman1-14/+27
Improve the calling convention detection to use __qcom_scm_is_call_available() and not blindly assume 32-bit mode if the checks fails. BUG() if neither 32-bit or 64-bit mode works. Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07firmware: qcom_scm-64: Move SMC register filling to qcom_scm_call_smcccElliot Berman1-20/+34
qcom_scm_call_smccc should be responsible for converting qcom_scm_desc into arguments for smc call. Consolidate the dispersed logic to convert qcom_scm_desc into smc arguments inside qcom_scm_call_smccc. Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07firmware: qcom_scm-64: Add SCM results structElliot Berman1-43/+50
Remove knowledge of arm_smccc_res struct from client wrappers so that client wrappers only work QCOM SCM data structures. SCM calls may have up to 3 arguments, so qcom_scm_call_smccc is responsible now for filling those 3 arguments accordingly. This is necessary to support merging legacy and SMC conventions in an upcoming patch. Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07firmware: qcom_scm-64: Move svc/cmd/owner into qcom_scm_descElliot Berman1-74/+121
Service, command, and owner IDs are all part of qcom_scm_desc struct and have no special reason to be a function argument (or hard-coded in the case of owner [1]). Moving them to be part of qcom_scm_desc struct improves readability. [1]: Example of SCM function using owner vale other than hard-coded SIP value: https://source.codeaurora.org/quic/la/kernel/msm-4.9/tree/drivers/soc/qcom/smcinvoke.c?h=kernel.lnx.4.9.r28-rel#n35 Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07firmware: qcom_scm-64: Make SMC macros less magicalElliot Berman1-3/+3
Improve understandability of SMC macros by reversing the logic as they are all functions of how many arguments can be shoved in registers and how many SCM arguments are supported. There aren't 4 register arguments because are 7 arguments that go into a buffer - there are up to 7 arguments that are overflowed into a buffer because only 4 registers are allocated for arguments. Reviewed-by: Stephen Boyd <[email protected]> Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07firmware: qcom_scm: Remove unused qcom_scm_get_versionElliot Berman2-38/+0
Remove unused qcom_scm_get_version. Reviewed-by: Bjorn Andersson <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07firmware: qcom_scm: Apply consistent naming scheme to command IDsElliot Berman4-72/+64
Create a consistent naming scheme for command IDs. The scheme is QCOM_SCM_##svc_##cmd. Remove unused macros QCOM_SCM_FLAG_HLOS, QCOM_SCM_FLAG_COLDBOOT_MC, QCOM_SCM_FLAG_WARMBOOT_MC, QCOM_SCM_CMD_CORE_HOTPLUGGED, and QCOM_SCM_BOOT_ADDR_MC. Reviewed-by: Bjorn Andersson <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07firmware: qcom_scm: Rename macros and structuresElliot Berman2-60/+64
Rename legacy-specific structures and macros with legacy prefix; rename smc-specific structures and macros with smc prefix. This should make it clearer which structures are generic to "SCM" and which are specfically for implementing the convention. Tested-by: Brian Masney <[email protected]> # arm32 Tested-by: Stephan Gerhold <[email protected]> Signed-off-by: Elliot Berman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07soc: qcom: rpmhpd: Set 'active_only' for active only power domainsDouglas Anderson1-0/+2
The 'active_only' attribute was accidentally never set to true for any power domains meaning that all the code handling this attribute was dead. NOTE that the RPM power domain code (as opposed to the RPMh one) gets this right. Acked-by: Rajendra Nayak <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Fixes: 279b7e8a62cc ("soc: qcom: rpmhpd: Add RPMh power domain driver") Signed-off-by: Douglas Anderson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-07memory: samsung: Rename Exynos to lowercaseKrzysztof Kozlowski2-2/+2
Fix up inconsistent usage of upper and lowercase letters in "Exynos" name. "EXYNOS" is not an abbreviation but a regular trademarked name. Therefore it should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-01-07soc: samsung: Rename Samsung and Exynos to lowercaseKrzysztof Kozlowski10-17/+17
Fix up inconsistent usage of upper and lowercase letters in "Samsung" and "Exynos" names. "SAMSUNG" and "EXYNOS" are not abbreviations but regular trademarked names. Therefore they should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Although advertisement materials usually use uppercase "SAMSUNG", the lowercase version is used in all legal aspects (e.g. on Wikipedia and in privacy/legal statements on https://www.samsung.com/semiconductor/privacy-global/). Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-01-06Merge tag 'renesas-drivers-for-v5.6-tag1' of ↵Olof Johansson2-6/+10
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers Renesas driver updates for v5.6 - Remove now unused ARCH_R8A7796 config symbol, - Fix a sparse warning, - Add split R-Car H3 ES1.x and ES2.0+ config symbols. * tag 'renesas-drivers-for-v5.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: Add ARCH_R8A7795[01] for existing R-Car H3 soc: renesas: rcar-rst: Fix __iomem on configure call soc: renesas: Remove ARCH_R8A7796 Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-06Merge tag 'tee-optee-pldrv-for-5.6' of ↵Olof Johansson1-89/+64
git://git.linaro.org:/people/jens.wiklander/linux-tee into arm/drivers Model OP-TEE as a platform device/driver * tag 'tee-optee-pldrv-for-5.6' of git://git.linaro.org:/people/jens.wiklander/linux-tee: optee: model OP-TEE as a platform device/driver Link: https://lore.kernel.org/r/20200103090025.GA11243@jax Signed-off-by: Olof Johansson <[email protected]>
2020-01-06Merge tag 'scmi-updates-5.6' of ↵Olof Johansson16-12/+245
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers ARM SCMI updates for v5.6 1. Addition of multiple device support per protocol to enable use of some procotols by multiple kernel subsystems simultaneously and corresponding updates to the existing scmi drivers 2. Addition of trace events around the scmi transfer code to measure any delays and capture anomalies that can also be used during investigation of some platform firmware related issues * tag 'scmi-updates-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: drivers: firmware: scmi: Extend SCMI transport layer by trace events include: trace: Add SCMI header with trace events reset: reset-scmi: Match scmi device by both name and protocol id hwmon: (scmi-hwmon) Match scmi device by both name and protocol id cpufreq: scmi: Match scmi device by both name and protocol id clk: scmi: Match scmi device by both name and protocol id firmware: arm_scmi: Skip protocol initialisation for additional devices firmware: arm_scmi: Stash version in protocol init functions firmware: arm_scmi: Match scmi device by both name and protocol id firmware: arm_scmi: Add versions and identifier attributes using dev_groups firmware: arm_scmi: Add names to scmi devices created firmware: arm_scmi: Skip scmi mbox channel setup for addtional devices firmware: arm_scmi: Add support for multiple device per protocol Link: https://lore.kernel.org/r/20191230182956.GA29349@bogus Signed-off-by: Olof Johansson <[email protected]>
2020-01-06soc: renesas: Add ARCH_R8A7795[01] for existing R-Car H3Geert Uytterhoeven1-0/+8
Despite using the same compatible values ("r8a7795"-based) because of historical reasons, R-Car H3 ES1.x (R8A77950) and R-Car H3 ES2.0+ (R8A77951) are really different SoCs, with different part numbers. Reflect this in the SoC configuration, by adding CONFIG_ARCH_R8A77950 and CONFIG_ARCH_R8A77951 as new config symbols. These are intended to replace CONFIG_ARCH_R8A7795, and will allow making support for early SoC revisions optional. Note that for now, CONFIG_ARCH_R8A7795 is retained, and just selects CONFIG_ARCH_R8A77950 and CONFIG_ARCH_R8A77951. This relaxes dependencies of other subsystems on the SoC configuration symbol, and provides a smooth transition path for config files through "make oldconfig". Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Tested-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-01-06soc: renesas: rcar-rst: Fix __iomem on configure callBen Dooks (Codethink)1-1/+1
The configure call back takes a register pointer, so should have been marked with __iomem. Add this to silence the following sparse warnings: drivers/soc/renesas/rcar-rst.c:33:22: warning: incorrect type in initializer (incompatible argument 1 (different address spaces)) drivers/soc/renesas/rcar-rst.c:33:22: expected int ( *configure )( ... ) drivers/soc/renesas/rcar-rst.c:33:22: got int ( * )( ... ) drivers/soc/renesas/rcar-rst.c:97:40: warning: incorrect type in argument 1 (different address spaces) drivers/soc/renesas/rcar-rst.c:97:40: expected void *base drivers/soc/renesas/rcar-rst.c:97:40: got void [noderef] <asn:2> *[assigned] base Signed-off-by: Ben Dooks (Codethink) <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-01-06reset: Add Broadcom STB RESCAL reset controllerJim Quinlan3-0/+115
On BCM7216 there is a special purpose reset controller named RESCAL (reset calibration) which is necessary for SATA and PCIe0/1 to operate correctly. This commit adds support for such a reset controller to be available. Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Florian Fainelli <[email protected]> Signed-off-by: Philipp Zabel <[email protected]>
2020-01-06dt-bindings: reset: Document BCM7216 RESCAL reset controllerJim Quinlan1-0/+37
BCM7216 has a special purpose RESCAL reset controller for its SATA and PCIe0/1 instances. This is a simple reset controller with #reset-cells set to 0. Signed-off-by: Jim Quinlan <[email protected]> [florian: Convert to YAML binding] Signed-off-by: Florian Fainelli <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Philipp Zabel <[email protected]>
2020-01-06firmware: scm: Add stubs for OCMEM and restore_sec_cfg_availableKrzysztof Kozlowski1-0/+6
Add few more stubs (for OCMEM-related functions and qcom_scm_restore_sec_cfg_available()) in case of !CONFIG_QCOM_SCM. These are actually not necessary for builds but provide them for completeness. Reviewed-by: Brian Masney <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-05soc: bcm: brcmstb: biuctrl: Update programming for 7211Florian Fainelli1-6/+7
Add a matching entry for 7211 which can be programmed with the same BIUCTRL settings as other Brahma-B53 based SoCs. While at it, rename the function to include a72 in the name to reflect this applies to both types of 64-bit capable CPUs that we support (Brahma-B53 and Cortex-A72). Signed-off-by: Florian Fainelli <[email protected]>
2020-01-05soc: bcm: brcmstb: biuctrl: Update layout for A72 on 7211Florian Fainelli1-0/+8
The BIUCTRL layout is a little different on 7211 which is equipped with a Cortex-A72, account for those register offset differences. We will match 7211 specifically in a subsequent commit. Signed-off-by: Florian Fainelli <[email protected]>
2020-01-05soc: bcm: brcmstb: biuctrl: Tune interface for 7255 and 7216Florian Fainelli1-0/+2
7255 and 7216 are some of the latest chips that were produced and support the full register range configuration for the BIU, add the two entries to get the expected programming. Signed-off-by: Florian Fainelli <[email protected]>
2020-01-05soc: bcm: brcmstb: biuctrl: Tune 7260 BIU interfaceFlorian Fainelli1-2/+5
7260A0 and B0 are both supported, and 7260A0 has a small difference in that it does not support the write-back control register, which is why we have a different array of registers. Update the comment above b53_cpubiuctrl_no_wb_regs to denote that difference. Signed-off-by: Florian Fainelli <[email protected]>
2020-01-04dt-bindings: power: rpmpd: Convert rpmpd bindings to yamlSibi Sankar2-150/+170
Convert RPM/RPMH power-domain bindings to yaml. Reviewed-by: Rajendra Nayak <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-01-03reset: intel: Add system reset controller driverDilip Kota3-0/+272
Add driver for the reset controller present on Intel Gateway SoCs for performing reset management of the devices present on the SoC. Driver also registers a reset handler to peform the entire device reset. Signed-off-by: Dilip Kota <[email protected]> Signed-off-by: Philipp Zabel <[email protected]>
2020-01-03dt-bindings: reset: Add YAML schemas for the Intel Reset controllerDilip Kota1-0/+63
Add YAML schemas for the reset controller on Intel Gateway SoC. Signed-off-by: Dilip Kota <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Philipp Zabel <[email protected]>
2020-01-03optee: model OP-TEE as a platform device/driverArd Biesheuvel1-89/+64
To simplify adding ACPI support to the OP-TEE driver, model it as a platform driver. This will permit us to use the generic device property layer for parsing additional properties, regardless of whether DT or ACPI is being used. Note that this change will result in the OP-TEE driver to be loaded automatically on systems that advertise the presence of OP-TEE via the device tree. Acked-by: Sumit Garg <[email protected]> Signed-off-by: Ard Biesheuvel <[email protected]> Signed-off-by: Jens Wiklander <[email protected]>
2020-01-02arm64: dts: Convert to the hierarchical CPU topology layout for MSM8916Ulf Hansson1-4/+53
To enable the OS to better support PSCI OS initiated CPU suspend mode, let's convert from the flattened layout to the hierarchical layout. In the hierarchical layout, let's create a power domain provider per CPU and describe the idle states for each CPU inside the power domain provider node. To group the CPUs into a cluster, let's add another power domain provider and make it act as the master domain. Note that, the CPU's idle states remains compatible with "arm,idle-state", while the cluster's idle state becomes compatible with "domain-idle-state". Co-developed-by: Lina Iyer <[email protected]> Signed-off-by: Lina Iyer <[email protected]> Signed-off-by: Ulf Hansson <[email protected]> Reviewed-by: Sudeep Holla <[email protected]>
2020-01-02cpuidle: psci: Add support for PM domains by using genpdUlf Hansson3-2/+284
When the hierarchical CPU topology layout is used in DT and the PSCI OSI mode is supported by the PSCI FW, let's initialize a corresponding PM domain topology by using genpd. This enables a CPU and a group of CPUs, when attached to the topology, to be power-managed accordingly. To trigger the attempt to initialize the genpd data structures let's use a subsys_initcall, which should be early enough to allow CPUs, but also other devices to be attached. The initialization consists of parsing the PSCI OF node for the topology and the "domain idle states" DT bindings. In case the idle states are compatible with "domain-idle-state", the initialized genpd becomes responsible of selecting an idle state for the PM domain, via assigning it a genpd governor. Note that, a successful initialization of the genpd data structures, is followed by a call to psci_set_osi_mode(), as to try to enable the OSI mode in the PSCI FW. In case this fails, we fall back into a degraded mode rather than bailing out and returning error codes. Co-developed-by: Lina Iyer <[email protected]> Signed-off-by: Lina Iyer <[email protected]> Signed-off-by: Ulf Hansson <[email protected]> Reviewed-by: Sudeep Holla <[email protected]> Acked-by: Rafael J. Wysocki <[email protected]>
2020-01-02PM / Domains: Introduce a genpd OF helper that removes a subdomainUlf Hansson2-0/+46
We already have the of_genpd_add_subdomain() helper, but no corresponding of_genpd_remove_subdomain(), so let's add it. Subsequent changes starts to make use of it. Signed-off-by: Ulf Hansson <[email protected]> Acked-by: Rafael J. Wysocki <[email protected]>
2020-01-02cpuidle: psci: Support CPU hotplug for the hierarchical modelUlf Hansson2-1/+45
When the hierarchical CPU topology is used and when a CPU is put offline, that CPU prevents its PM domain from being powered off, which is because genpd observes the corresponding attached device as being active from a runtime PM point of view. Furthermore, any potential master PM domains are also prevented from being powered off. To address this limitation, let's add add a new CPU hotplug state (CPUHP_AP_CPU_PM_STARTING) and register up/down callbacks for it, which allows us to deal with runtime PM accordingly. Signed-off-by: Ulf Hansson <[email protected]> Reviewed-by: Sudeep Holla <[email protected]> Acked-by: Rafael J. Wysocki <[email protected]>
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