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2023-09-26drm/amd/display: remove unused mmhub_reg_offsetsQingqing Zhuo1-10/+0
[Why & How] mmhub_reg_offsets never used in code. Remove it. Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdkfd: fix some race conditions in vram buffer alloc/free of svm codeXiaogang Chen1-4/+4
This patch fixes: 1: ref number of prange's svm_bo got decreased by an async call from hmm. When wait svm_bo of prange got released we shoul also wait prang->svm_bo become NULL, otherwise prange->svm_bo may be set to null after allocate new vram buffer. 2: During waiting svm_bo of prange got released in a while loop should reschedule current task to give other tasks oppotunity to run, specially the the workque task that handles svm_bo ref release, otherwise we may enter to softlock. Signed-off-by: Xiaogang.Chen <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdkfd: Move dma unmapping after TLB flushPhilip Yang3-12/+35
Otherwise GPU may access the stale mapping and generate IOMMU IO_PAGE_FAULT. Move this to inside p->mutex to prevent multiple threads mapping and unmapping concurrently race condition. After kfd_mem_dmaunmap_attachment is removed from unmap_bo_from_gpuvm, kfd_mem_dmaunmap_attachment is called if failed to map to GPUs, and before free the mem attachment in case failed to unmap from GPUs. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdgpu: further move TLB hw workarounds a layer upChristian König2-51/+42
For the PASID flushing we already handled that at a higher layer, apply those workarounds to the standard flush as well. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdgpu: rework lock handling for flush_tlb v2Christian König5-20/+11
Instead of each implementation doing this more or less correctly move taking the reset lock at a higher level. v2: fix typo Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdgpu: drop error return from flush_gpu_tlb_pasidChristian König7-29/+24
That function never fails, drop the error return. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdgpu: fix and cleanup gmc_v11_0_flush_gpu_tlb_pasidChristian König1-44/+19
The same PASID can be used by more than one VMID, reset each of them. Use the common KIQ handling. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdgpu: cleanup gmc_v10_0_flush_gpu_tlb_pasidChristian König1-47/+19
The same PASID can be used by more than one VMID, reset each of them. Use the common KIQ handling. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdgpu: fix and cleanup gmc_v9_0_flush_gpu_tlb_pasidChristian König3-79/+102
Testing for reset is pointless since the reset can start right after the test. The same PASID can be used by more than one VMID, invalidate each of them. Move the KIQ and all the workaround handling into common GMC code. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdgpu: fix and cleanup gmc_v8_0_flush_gpu_tlb_pasidChristian König1-10/+10
Testing for reset is pointless since the reset can start right after the test. Grab the reset semaphore instead. The same PASID can be used by more than once VMID, build a mask of VMIDs to invalidate instead of just restting the first one. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Shashank Sharma <[email protected]> Acked-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdgpu: fix and cleanup gmc_v7_0_flush_gpu_tlb_pasidChristian König1-9/+10
Testing for reset is pointless since the reset can start right after the test. Grab the reset semaphore instead. The same PASID can be used by more than once VMID, build a mask of VMIDs to invalidate instead of just restting the first one. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Shashank Sharma <[email protected]> Acked-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdgpu: cleanup gmc_v11_0_flush_gpu_tlbChristian König2-69/+43
Remove leftovers from copying this from the gmc v10 code. v2: squash in fix from Yifan Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdgpu: rework gmc_v10_0_flush_gpu_tlb v2Christian König5-119/+99
Move the SDMA workaround necessary for Navi 1x into a higher layer. v2: use dev_err Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdgpu: change if condition for bad channel bitmap updateTao Zhou1-2/+4
The amdgpu_ras_eeprom_control.bad_channel_bitmap is u32 type, but the channel index could be larger than 32. For the ASICs whose channel number is more than 32, the amdgpu_dpm_send_hbm_bad_channel_flag interface is not supported, so we simply bypass channel bitmap update under this condition. v2: replace sizeof with BITS_PER_TYPE, we should check bit number instead of byte number. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdgpu: fix value of some UMC parameters for UMC v12Tao Zhou2-1/+5
Prepare for bad page retirement. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amd/pm: add unique_id for gc 11.0.3Kenneth Feng1-0/+1
add unique_id for gc 11.0.3 Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amd/display: fix some style issuesAlex Deucher2-9/+7
Fixes a few style issues: - Only calculate the dto_params and dp_hpo_inst when dccg is present. - Fix indentation - Drop empty else block Fixes: 7f7925e25828 ("drm/amd/display: Fix MST recognizes connected displays as one") Cc: Muhammad Ahmed <[email protected]> Cc: Michel Dänzer <[email protected]> Cc: Stylon Wang <[email protected]> Reviewed-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdkfd: Don't use sw fault filter if retry cam enabledPhilip Yang1-1/+4
If retry cam enabled, we don't use sw retry fault filter and add fault into sw filter ring, so we shouldn't remove fault from sw filter. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdgpu: fix and cleanup gmc_v9_0_flush_gpu_tlbChristian König1-11/+18
The KIQ code path was ignoring the second flush. Also avoid long lines and re-calculating the register offsets over and over again. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26gpu: drm: amd: display: fix kernel-doc warningsSwarup Laxman Kotiaklapudi1-0/+6
Fix kernel-doc warnings discovered in AMD gpu display driver. Fixes these warnings: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'overlap_only' not described in 'mpcc_blnd_cfg'. ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'bottom_gain_mode' not described in 'mpcc_blnd_cfg'. ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'background_color_bpc' not described in 'mpcc_blnd_cfg'. ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'top_gain' not described in 'mpcc_blnd_cfg'. ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'bottom_inside_gain' not described in 'mpcc_blnd_cfg'. ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:110: warning: Function parameter or member 'bottom_outside_gain' not described in 'mpcc_blnd_cfg'. Tested-by: Randy Dunlap <[email protected]> Acked-by: Randy Dunlap <[email protected]> Signed-off-by: Swarup Laxman Kotiaklapudi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdgpu: Increase IH soft ring size for GFX v9.4.3 dGPUPhilip Yang1-1/+1
On GFX v9.4.3 dGPU, applications have random timeout failure when XNACK on, dmesg log has "amdgpu: IH soft ring buffer overflow 0x900, 0x900", because dGPU mode has 272 cam entries. After increasing IH soft ring to 512 entries, no more IH soft ring overflow message and application passed. Fixes: bf80d34b6c58 ("drm/amdgpu: Increase soft IH ring size") Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amdgpu: Restore partition mode after resetLijo Lazar4-8/+28
On a full device reset, PSP FW gets unloaded. Hence restore the partition mode by placing a new request. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Acked-by: Alex Deucher <[email protected]> Tested-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amd/display: 3.2.252Aric Cyr1-1/+1
This version brings along the following: - Use optc32 instead of optc30 in DC - Optimize OLED T7 delay - Multiple fixes for MST, register mas, and others - Update driver and IPS interop - Improve z8 watermark mask - DCN35 updates - Enable replay for DCN35 - Temporarily disable clock gating Tested-by: Daniel Wheeler <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amd/display: Drop unused link FPGA codeRodrigo Siqueira6-138/+2
There are multiple parts of the code that DC does not use anymore, and this commit drops those dead codes. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amd/display: Enable DCN low mem power by defaultMuhammad Ahmed1-1/+1
Enable DCN low mem power by default. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Muhammad Ahmed <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amd/display: Expand DML to better support replayMuhammad Ahmed1-0/+47
Update with extended blank Vstartup adjustment for replay. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Muhammad Ahmed <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amd/display: Use optc32 instead of optc30 in DCOvidiu Bunea4-3/+5
Change DC to use optc32, which uses REG_UPDATE instead of REG_SET. REG_SET clears OTG_H_TIMING_DIV_MODE_MANUAL which must be set to 1 in some specific HDMI configurations. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Ovidiu Bunea <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-26drm/amd/display: Optimize OLED T7 delayAgustin Gutierrez1-1/+2
[Why] Driver doesn't need T7 delay for OLED panels, since it doesn't control power sequence. [How] This delay can be skipped to optimize resume times. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Reviewed-by: Swapnil Patel <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Agustin Gutierrez <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdkfd: Remove svm range validated_once flagPhilip Yang2-4/+1
The validated_once flag is not used after the prefault was removed, The prefault was needed to ensure validate all system memory pages at least once before mapping or migrating the range to GPU. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: Add more fields to IP versionLijo Lazar3-13/+35
Include subrevision and variant fileds also to IP version. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: print channel index for UMC bad pageTao Zhou1-4/+6
Print channel index for UMC v12. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdkfd: Separate dma unmap and free of dma address array operationsXiaogang Chen3-12/+21
We do not need free dma address array of svm_range each time we do dma unmap for pages in svm_range as we can reuse the same array. Only free it when free svm_range. Separate these two operations and use them accordingly. Signed-off-by: Xiaogang Chen <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/pm: Remove SMUv13.0.6 unsupported featureLijo Lazar1-1/+0
Selectively updating feature mask is not supported in SMU v13.0.6. Remove the callback corresponding to that. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Yang Wang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/pm: Round Q10 format values in SMU v13.0.6Lijo Lazar1-34/+36
Instead of neglecting fractional part, round the Q10 format values in SMU v13.0.6 metrics table. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: update IP count INFO querySathishkumar S1-29/+61
update the query to return the number of functional instances where there is more than an instance of the requested type and for others continue to return one. v2: count must reflect the actual number of engines (Alex) v3: fix wrong number of engines for vcn (Alex) Signed-off-by: Sathishkumar S <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: Fix false positive error logStanley.Yang1-5/+5
It should first check block ras obj whether be set, it should return 0 directly if block ras obj or hw_ops is not set. If block doesn't support RAS just return 0 is fine. Changed from V1: return 0 directly if block ras obj or hw ops is not set Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu/jpeg: skip set pg for sriovVignesh Chander2-11/+12
Host handles PG. Signed-off-by: Vignesh Chander <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdkfd: Use gpu_offset for user queue's wptrYuBiao Wang1-1/+1
Directly use tbo's start address will miss the domain start offset. Need to use gpu_offset instead. Signed-off-by: YuBiao Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: 3.2.251Aric Cyr1-1/+1
Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: [FW Promotion] Release 0.0.183.0Anthony Koo1-0/+31
- Add new IPS ALLOW masks - Add new Replay power configuration options Tested-by: Daniel Wheeler <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Fix MST recognizes connected displays as oneMuhammad Ahmed2-25/+74
MST now recognizes both connected displays Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Muhammad Ahmed <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: fix some non-initialized register mask and settingCharlene Liu6-160/+33
Fix some non-initialized register mask and update golden setting. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Duncan Ma <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Enable replay for dcn35Roman Li1-0/+1
Enable the display replay feature for DCN35. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Qingqing Zhuo <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Add option to flip ODM optimizationGabe Teeger1-0/+1
Add a config option to disable odm dispclk optimization for debug purpose. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Gabe Teeger <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: disable IPSMuhammad Ahmed1-0/+1
Disable IPS by default till it is ready. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Duncan Ma <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Muhammad Ahmed <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Add IPS control flagSung Joon Kim5-35/+51
[why] Currently, driver is not aware if IPS is supported. After PMFW helps implement new message query functionality, driver will set IPS capability flag. [how] Create new SMU hook function to query IPS capability. Based on the cap, set appropriate flags to false for power-gating purposes. This will avoid keeping SMU busy and offloading tasks to DMUB/driver. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Update driver and IPS interopDuncan Ma2-0/+6
[Why] Two issues fixed: 1. Currently, driver does not allow idle prior to PSR entry. Once PSR1+IPS is enabled, there is intermittent hang due to DCN access from IrqMgr during IPS2. 2. Driver is sending multiple commands to PMFW and dmcub to exit IPS even during IPS0. [How] 1. Set driver allow optimization prior to entering PSR mode with the condition for eDP display only. Unregister all interrupts before allowing driver idle and re-register interrupts when exiting from idle. This will prevent IrqMgr to access DCN during IPS2. 2. Block sending PMFW and dmcub exit low power state commands when driver is not in idle state. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Reviewed-by: Jun Lei <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Duncan Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Correct z8 watermark maskCharlene Liu2-10/+8
Correct z8_watermark mask from 16bit to 20bit. Also, do not set dcn35 dprefclk in clk_mgr_construct. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Muhammad Ahmed <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: STREAM_MAPPER_CONTROL register offset on DCN35Artem Grishin1-1/+2
[Why] The STREAM_MAPPER_CONTROL register offset was left uninitialized, causing warning in the driver log at runtime [How] A temporary solution to add it into dcn35_create_resource_pool. [TODO] Remove duplication between SE_DCN35_REG_LIST_RI in dcn35_resource.h and SE_DCN35_REG_LIST in dcn35_dio_stream_encoder.h Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Artem Grishin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Update pipe resource interfaces for DCN35Wenjing Liu1-0/+1
Pipe resource interfaces were changed. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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