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2017-03-29drm/amdgpu: add psp firmware header infoHuang Rui1-0/+9
Defines the header info for the psp firmware. Acked-by: Christian König <[email protected]> Signed-off-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: rework common ucode handling for vega10Huang Rui3-23/+53
Handle ucode differences in vega10. Acked-by: Christian König <[email protected]> Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: don't validate TILE_SPLIT on GFX9Marek Olšák1-1/+4
Signed-off-by: Marek Olšák <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add tiling flags for GFX9 (v2)Alex Deucher1-2/+8
v2: Marek: allow shifts >32 in AMDGPU_TILING_SET/GET Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: Add asic family for vega10Alex Deucher1-0/+1
Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add NGG parametersAlex Deucher4-0/+65
NGG (Next Generation Graphics) is a new feature in GFX9.0. This adds the relevant parameters. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add PTE defines for MTYPEAlex Deucher1-0/+4
New on SOC-15 asics. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add IV trace pointChristian König2-0/+40
This allows us to grab IVs without spamming the log. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: update IH IV ring entry for soc-15Alex Deucher1-1/+4
Reflect the new format on soc-15 asics. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: use atomfirmware interfaces for scratch reg save/restoreAlex Deucher1-4/+16
If the board is atomfirmware based. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: Add MTYPE flags to GPU VM IOCTL interfaceAlex Xie2-1/+13
Signed-off-by: Alex Xie <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add 64bit doorbell assignmentsKen Wang1-0/+68
Signed-off-by: Ken Wang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: gb_addr_config structAndrey Grodzovsky1-0/+10
Acked-by: Christian König <[email protected]> Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: use new flag to handle different firmware loading methodHuang Rui10-20/+90
This patch introduces a new flag named "amdgpu_firmware_load_type" to handle different firmware loading method. Since Vega10, there are three ways to load firmware. It would be better to use a flag and a fw_load_type kernel parameter to configure it. Acked-by: Christian König <[email protected]> Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add clinetid definition for vega10ken1-2/+40
Signed-off-by: ken <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add vega10 chip nameKen Wang2-0/+2
Acked-by: Christian König <[email protected]> Signed-off-by: Ken Wang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add common soc15 headersKen Wang3-0/+377
These are used by various IP modules. Acked-by: Christian König <[email protected]> Signed-off-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add SDMA 4.0 packet headerAlex Deucher1-0/+3335
Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add gfx9 clearstate headerAlex Deucher1-0/+941
Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd: Add MQD structs for GFX V9Felix Kuehling1-0/+675
This header defines the gfx v9 MEC structures. Acked-by: Christian König <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Shaoyun Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add the VCE 4.0 register headersAlex Deucher3-0/+818
These are the Video Compression Engine registers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add the UVD 7.0 register headersAlex Deucher3-0/+1160
These are the Unifed Video Decoder registers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add THM 9.0 register headersAlex Deucher3-0/+1871
These are the THerMal control registers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add SMUIO 9.0 register headersAlex Deucher3-0/+533
These are the System Managment Unit IO registers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add SDMA 4.0 register headersAlex Deucher6-0/+5316
These are the System DMA register headers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add OSSSYS 4.0 register headersAlex Deucher3-0/+1699
These are the OS Services register headers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add NBIO 6.1 register headersAlex Deucher3-0/+159873
These are the Bus IO registers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add NBIF 6.1 register headersAlex Deucher3-0/+13240
These are the Bus InterFace registers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add MP 9.0 register headersAlex Deucher3-0/+2180
MP is the system management controller on vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add the MMHUB 1.0 register headersAlex Deucher3-0/+13105
Add the MultiMedia Hub registers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add the HDP 4.0 register headersAlex Deucher3-0/+927
These are the Host Data Path registers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add the GC 9.0 register headersAlex Deucher3-0/+40971
Add the Graphics Core register headers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: Add the DCE 12.0 register headersAlex Deucher3-0/+92697
These are the register headers for the Display and Composition Engine on vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: Add ATHUB 1.0 register headersAlex Deucher3-0/+2739
ATHUB is part of the memory controller on soc15 asics. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add vega10_enum.hAlex Deucher1-0/+22531
This adds the register bitfield enums for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add soc15ip.hAlex Deucher1-0/+1343
This header defines the IP layout for soc15 based SoCs. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add basic support for atomfirmware.h (v3)Alex Deucher5-13/+172
This adds basic support for asics that use atomfirmware.h to define their vbios tables. v2: rebase v3: squash in num scratch reg fix Acked-by: Christian König <[email protected]> Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: move atom scratch setup into amdgpu_atombios.cAlex Deucher5-28/+32
There will be a slightly different version for atomfirmware. Acked-by: Christian König <[email protected]> Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29amdgpu: detect if we are using atomfirmware or atombios for vbios (v2)Alex Deucher2-7/+24
Supposedly atomfirmware rom header is 3.3 atombios is 1.1. v2: rebased on newer kernel Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add the new atomfirmware interface headerAlex Deucher3-0/+2720
soc15 asics have a new vbios interface. These headers define that interface. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add optional fence out-parameter to amdgpu_vm_clear_freedNicolai Hähnle4-9/+19
We will add the fence to freed buffer objects in a later commit, to ensure that the underlying memory can only be re-used after all references in page tables have been cleared. Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/powerplay: restore disabling power containment on Fiji (v2)Eric Huang1-0/+7
Power containment will degrade performance in some compute tests. Restore disabling it as before code refining in powerplay. v2: only in the compute profile Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx8: further KIQ parameter cleanupAlex Deucher1-13/+11
The ring structure already has what we need. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx8: store the eop gpu addr in the ring structureAlex Deucher2-8/+7
Avoids passing around additional parameters during setup. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx8: reduce the functon params for mpq setupAlex Deucher1-18/+14
Everything we need is in the ring structure. No need to pass all the bits explicitly. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx8: reserve kiq eop object before unmapping itAlex Deucher1-0/+4
It's required. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx8: fold loops in kiq_resume()Alex Deucher1-4/+0
No need to loop through the compute queues twice. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx8: test KIQ before compute ringsAlex Deucher1-6/+7
If KIQ isn't working, the compute rings won't work either. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx8: reserve mqd objects before mapping themAlex Deucher1-11/+21
It's required. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx8: rename some functionsAlex Deucher1-6/+6
To better match where they are used. Called from sw_init and sw_fini. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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