aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2017-03-29drm/amdgpu/gfx9: use hweight for calculating num_rbsAlex Deucher1-5/+2
Match what we do for other asics. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: refine the logic in amdgpu_need_post()Alex Deucher1-1/+1
We check the mem config register to make sure it's been programmed by the vbios to determine if we need to post so we check for a non-0 value. However, when the asic comes out of reset, we may see all ones here, so check for that too. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: Add interrupt entries for CRTC_VERTICAL_INTERRUPT0.Andrey Grodzovsky1-0/+99
This used by DAL ISR logic for VBLANK handling. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:changes in gfx DMAframe scheme (v2)Monk Liu5-57/+88
1) Adapt to vulkan: Now use double SWITCH BUFFER to replace the 128 nops w/a, because when vulkan introduced, umd can insert 7 ~ 16 IBs per submit which makes 256 DW size cannot hold the whole DMAframe (if we still insert those 128 nops), CP team suggests use double SWITCH_BUFFERs, instead of tricky 128 NOPs w/a. 2) To fix the CE VM fault issue when MCBP introduced: Need one more COND_EXEC wrapping IB part (original one us for VM switch part). this change can fix vm fault issue caused by below scenario without this change: >CE passed original COND_EXEC (no MCBP issued this moment), proceed as normal. >DE catch up to this COND_EXEC, but this time MCBP issued, thus DE treats all following packages as NOP. The following VM switch packages now looks just as NOP to DE, so DE dosen't do VM flush at all. >Now CE proceeds to the first IBc, and triggers VM fault, because DE didn't do VM flush for this DMAframe. 3) change estimated alloc size for gfx9. with new DMAframe scheme, we need modify emit_frame_size for gfx9 4) No need to insert 128 nops after gfx8 vm flush anymore because there was double SWITCH_BUFFER append to vm flush, and for gfx7 we already use double SWITCH_BUFFER following after vm_flush so no change needed for it. 5) Change emit_frame_size for gfx8 v2: squash in BUG removal from Monk Signed-off-by: Monk Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:fix missing programing critical registersMonk Liu3-1/+21
those MC_VM registers won't be programed by VBIOS in VF so driver is responsible to programe them. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:fix ring_write_multipleMonk Liu1-2/+2
ring_write_multiple should use buf_mask instead of ptr_mask Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:fix gmc_v9 vm fault process for SRIOVMonk Liu1-8/+16
for SRIOV we cannot use access register when in IRQ routine with regular KIQ method Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:no cg for soc15 of SRIOVMonk Liu1-0/+3
no CG for SRIOV on SOC15 Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:two fixings for sdma v4 for SRIOVMonk Liu1-0/+6
no hw_fini for SRIOV, otherwise other VF will be affected no CG for SRIOV Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:change sequence of SDMA v4 initMonk Liu1-10/+27
must set minor_update.enable before write smaller value to wptr/doorbell, so for sriov we need set that register bit in hw_init period. this could fix the SDMA ring test fail after guest reboot Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:fix ring init sequenceMonk Liu2-4/+4
ring->buf_mask need be set prior to ring_clear_ring invoke and fix ring_clear_ring as well which should use buf_mask instead of ptr_mask Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:virt_init_setting invoke is missed!Monk Liu1-0/+4
this must be invoked during early init Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29uapi/drm:add new flag for PreemptionMonk Liu1-0/+3
when MCBP supported, we will set pre_enb bit for those IBs with PREEMPT flag tagged Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29uapi/drm:change Preamble DescriptionMonk Liu1-1/+1
Preamble in linux doesn't mean it is CE PREAMBLE IB, instead it means this IB could be dropped if no ctx switch happens. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:enable MCBP for SR-IOV (v2)Monk Liu2-0/+4
Apply the new IB during IB emit for SRIOV with MCBP v2: agd: use define instead of magic number Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:enable mcbp for gfx9(v2)Monk Liu2-0/+4
set bit 21 of IB.control filed to actually enable MCBP for SRIOV v2: add flag for preemption enable bit for soc15 and use this flag instead of hardcode. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:implement cond_exec for gfx8Monk Liu1-0/+30
when MCBP enabled for gfx8, the cond_exec must also be implemented, otherwise there will be odds to meet cross engine (ce and me) deadlock when world switch happens. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:fix the check in cs_ib_fill for SRIOVMonk Liu1-9/+10
1,the check is only appliable for SRIOV GFX engine. 2,use chunk_ib instead of ib. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:protect cs submitMonk Liu1-1/+12
to prevent submit two or more IBs with PREEMPT flags. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:fix cs_ib_fillMonk Liu1-1/+1
should use chunk_ib instead of ib, otherwise the logic is incorrect. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: clear freed mappings immediately when BO may be freedNicolai Hähnle1-0/+12
Also, add the fence of the clear operations to the BO to ensure that the underlying memory can only be re-used after all PTEs pointing to it have been cleared. This avoids the following sequence of events that could be triggered by user space: 1. Submit a CS that accesses some BO _without_ adding that BO to the buffer list. 2. Free that BO. 3. Some other task re-uses the memory underlying the BO. 4. The CS is submitted to the hardware and accesses memory that is now already in use by somebody else. By clearing the page tables immediately in step 2, a GPU VM fault will be triggered in step 4 instead of wild memory accesses. v2: use amdgpu_bo_fence directly Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: enable four level VMPT for gmc9Chunming Zhou1-1/+1
Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: set page table depth by num_levelChunming Zhou2-2/+3
Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: adapt vm size for multi vmptChunming Zhou1-0/+6
Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: limit block size to one pageChunming Zhou1-0/+8
Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: abstract block size to one functionChunming Zhou1-27/+32
Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add alloc/free for multi level PDs V2Christian König1-69/+106
Allocate and free page directories on demand. V2: a. clear entries allocation b. fix entries index calculation c. need alloc sub level even parent bo was allocated Signed-off-by: Christian König <[email protected]> (v1) Reviewed-by: Alex Deucher <[email protected]> (v1) Signed-off-by: Chunming Zhou <[email protected]> (v2) Acked-by: Alex Deucher <[email protected]> (v2) Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: handle multi level PD during PT updatesChristian König1-5/+34
Not the best solution, but good enough for now. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: handle multi level PD updates V2Christian König4-37/+68
Update all levels of the page directory. V2: a. sub level pdes always are written to incorrect place. b. sub levels need to update regardless of parent updates. Signed-off-by: Christian König <[email protected]> (V1) Reviewed-by: Alex Deucher <[email protected]> (V1) Signed-off-by: Chunming Zhou <[email protected]> (V2) Acked-by: Alex Deucher <[email protected]> (V2) Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: handle multi level PD in the LRUChristian König1-9/+27
Move all levels to the end after command submission. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: handle multi level PD during validationChristian König1-15/+42
All page directory levels should be in place after this. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: handle multi level PD size calculation (v2)Christian König1-12/+22
Allows us to get the size for all levels as well. v2: agd: fix warning Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: generalize page table levelChristian König3-50/+50
No functional change, but the base for multi level page tables. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add num_level to the VM managerChristian König5-0/+5
Needs to be filled with handling. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add the VM pointer to the amdgpu_pte_update_params as wellChristian König1-10/+11
This way we save passing it through the different functions. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: rename page_directory_fence to last_dir_updateChristian König3-6/+6
Decribes better what this is used for. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/powerplay: reduce sample period timeRex Zhu1-1/+1
for power readings. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add get_clockgating callback for mmhub v1Huang Rui1-0/+20
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add get_clockgating for sdma v4Huang Rui1-0/+20
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add get_clockgating callback for soc15 (v3)Huang Rui2-0/+40
v2: squash register typo fix from Ray v3: fix spelling Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add get_clockgating callback for nbio v6.1Huang Rui3-0/+17
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add get_clockgating callback for gfx v9Huang Rui2-0/+45
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx9: further KIQ parameter cleanupAlex Deucher1-11/+11
The ring structure already has what we need. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx9: store the eop gpu addr in the ring structureAlex Deucher1-8/+6
Avoids passing around additional parameters during setup. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx9: reduce the functon params for mpq setupAlex Deucher1-16/+14
Everything we need is in the ring structure. No need to pass all the bits explicitly. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx9: reserve kiq eop object before unmapping itAlex Deucher1-0/+4
It's required. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx9: reserve mqd objects before mapping themAlex Deucher1-11/+21
It's required. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx9: rename some functionsAlex Deucher1-4/+4
To better match where they are used. Called from sw_init and sw_fini. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx9: whitespace cleanupAlex Deucher1-6/+5
Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/amdgpu: Fix some warnings in vce4Harry Wentland1-4/+4
Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.