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2015-08-28drm/nouveau/tmr: cosmetic changesBen Skeggs13-122/+121
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/therm: cosmetic changesBen Skeggs15-466/+440
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/pmu: cosmetic changesBen Skeggs3-47/+45
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/mxm: cosmetic changesBen Skeggs2-12/+8
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/mmu: cosmetic changesBen Skeggs9-173/+162
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/mc: cosmetic changesBen Skeggs8-73/+67
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/ltc: cosmetic changesBen Skeggs5-149/+149
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/imem: cosmetic changesBen Skeggs12-198/+194
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/ibus: cosmetic changesBen Skeggs4-109/+97
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/i2c: cosmetic changesBen Skeggs9-50/+38
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/gpio: cosmetic changesBen Skeggs2-5/+5
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/fuse: cosmetic changesBen Skeggs5-43/+34
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/fb: cosmetic changesBen Skeggs51-663/+649
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/devinit: cosmetic changesBen Skeggs16-205/+205
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/clk: cosmetic changesBen Skeggs12-776/+765
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/bus: cosmetic changesBen Skeggs9-100/+94
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/bios: cosmetic changesBen Skeggs3-5/+5
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/bar: cosmetic changesBen Skeggs5-135/+127
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/device: include core/device.h automatically for subdevs/enginesBen Skeggs78-159/+65
Pretty much every subdev/engine is going to need access to nvkm_device shortly to touch registers and/or output messages. The odd placement of the includes is necessary to work around some inter-dependencies that currently exist. This will be fixed later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/device: add direct pointer to struct deviceBen Skeggs2-0/+3
A future commit will hide the platform/pci specifics from nvkm_device, but it's still very useful in a lot of places to have access to the Linux device struct. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/device: add direct pointers to subdevs from nvkm_deviceBen Skeggs2-7/+96
Will be used in upcoming commits to remove the need for lookup/runtime type-checking functions when accessing foreign subdevs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/subdev: add direct pointer to nvkm_deviceBen Skeggs6-10/+15
Will be utilised in upcoming commits to remove the need for heuristics to lookup the device a subdev belongs to. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/lib: various tweaksBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/pmu/gk104: implement a hackish workaround for a hw bugBen Skeggs1-0/+51
Only a handful of machines have this enabled by default, where it's been proven to work. The workaround can be explicitly enabled with a module option also. Still waiting on feedback from NVIDIA for a proper idea of exactly what this fix is doing, and how to implement it properly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/disp/dp: gm1xx appears to have same dp lane ordering as gm2xxBen Skeggs3-10/+7
Fixes 2-lane DP on Quadro K620. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/disp/dp: fix some tx_pu mishandlingBen Skeggs4-6/+7
We only need to mask 0x0f on GM2xx, and want to keep the higher bits on earlier cards. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/bios/dp: use alternate set of drvctl values where necessaryBen Skeggs1-5/+4
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/bios/dcb: accept "maxwell" lane count values for dcb 4.0Ben Skeggs2-27/+25
We previously assumed that the values "2" and "4" were new in DCB 4.1, however, there's at least one GM107 DCB 4.0 board (Quadro K620) that uses the newer values. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/fb/sddr3: add WR/CWL values seen on a GK208Ilia Mirkin1-2/+2
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/nv46: Change mc subdev oclass from nv44 to nv4cHans de Goede1-1/+1
MSI interrupts appear to not work for nv46 based cards. Change the mc subdev oclass for these cards from nv44 to nv4c, the nv4c mc code is identical to the nv44 mc code except that it does not use msi (it does not define a msi_rearm callback). BugLink: https://bugs.freedesktop.org/show_bug.cgi?id=90435 Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/pm/gf100: only use PBFB_BROADCAST.PM_UNK100 for PBFB signalsSamuel Pitoiset5-54/+19
High level hardware events related to PBFB will monitor all partitions. While we are at it, fix bitfield for this mux. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/pm/gf100: remove multiple definitions of GPC_DOM signal 0x0eSamuel Pitoiset1-5/+4
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/pm/gf100: remove undefined TEX.PM_UNKC8 muxSamuel Pitoiset1-4/+0
This mux only exists on GF108+ (except for GF110 one), but since it is not used by the userspace we can drop it for now. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/pm: allow zeroed signals to enable sourcesSamuel Pitoiset1-2/+2
Hardware signals index 0x00 are defined for some domains and they have to be allowed to enable sources like the others. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/pm/nv50: TPC[0x3] must be used for PGRAPH muxs on G80Samuel Pitoiset3-20/+28
I thought that using TPC[0x0] like for G84:GT215 was sufficient on G80, but it's actually not the case. According to NVIDIA PerfKit on Windows, we have to configure PGRAPH related muxs on TPC[0x3] for this chipset. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/pm/nv50: fix wrong addr for ZCULL source on G80:GT215Samuel Pitoiset1-1/+1
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/bios: add opcodes 0x73 and 0x77Ilia Mirkin1-0/+37
No known VBIOSes use these, but they are present in the actual VBIOS table parsing logic. No harm in adding these too. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/platform: recognize GM20BAlexandre Courbot1-0/+1
Allow the platform driver to recognize GM20B. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/device: recognize GM20BAlexandre Courbot1-0/+20
Recognize GM20B and assign the right engines and subdevs. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/gr: add GM20B supportAlexandre Courbot10-6/+217
Add support for GM20B's graphics engine, based on GK20A. Note that this code alone will not allow the engine to initialize on released devices which require PMU-assisted secure boot. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/fifo: add GM20B fifoAlexandre Courbot5-1/+41
GM20B has a 512-channels FIFO similar to GK104. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/gr/gk20a: use same initialization sequence as nvgpuAlexandre Courbot5-30/+421
GK20A's initialization was based on GK104, but differences exist in the way the initial context is built and the initialization process itself. This patch follows the same initialization sequence as nvgpu performs to avoid bad surprises. Since the register bundles initialization also differ considerably from GK104, the register packs are now loaded from firmware files, again similarly to what is done with nvgpu. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/gr: use NVIDIA-provided external firmwaresAlexandre Courbot1-12/+19
NVIDIA will officially start providing GR firmwares through linux-firmware for GPUs that require it. Change the GR firmware lookup function to use these files. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/pm/gk104: add compute signals/sourcesSamuel Pitoiset3-1/+93
These signals and sources have been reverse engineered from CUPTI (Linux). Graphics signals exposed by PerfKit (Windows only) will be added later. I need to reverse engineer them and it's a bit painful. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/pm/gk104: re-use gf100_pm_ctor()Samuel Pitoiset3-56/+14
gk104_pm_ctor() is equal to gf100_pm_ctor(). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/pm/nv40: rename pcounter domains to 'pc' instead of 'pm'Samuel Pitoiset1-1/+1
This trivial patch makes thing more consistent since hardware signals names are prefixed by 'pcXX'. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/pm: expose name of domainsSamuel Pitoiset2-0/+2
This is going to be very useful for GF100+ because each GPC can have its own domain of counters. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/drm/nouveau/clk: fix tstate to pstate calculationWei Ni1-1/+1
According to the tstate calculation in nvkm_clk_tstate(), the range of tstate is from -(clk->state_nr - 1) to 0, it mean the tstate is negative value. But in nvkm_pstate_work(), it use (clk->state_nr - 1 - clk->tstate) to limit pstate, it's not correct. This patch fix it to use (clk->state_nr - 1 + clk->tstate) to limit pstate. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/pm: some fixes related to sourcesSamuel Pitoiset1-5/+16
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/pm: fix signals/sources for GT200+Samuel Pitoiset2-6/+5
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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