aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2019-06-22drm/amd/display: navi10 bring up skip dsc encoder confighersen wu1-0/+8
not needed for bring up. Signed-off-by: hersen wu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: skip dsc config for navi10 bring uphersen wu2-1/+10
[why] we meet a bug when program dsc register even dsc mode is not enabled. disable dsc config for now. we will re-visit this issue. Signed-off-by: hersen wu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: do not need otg lock if otg is not activehersen wu1-1/+10
[todo] need find caller bug. tempooariy fix Signed-off-by: hersen wu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: disable dcn20 abm feature for bring uphersen wu1-4/+7
[WHY] dcn20 enable usb-c dp ALT mode in dmcu. There is bug when enable abm feature which cause system crash. dal team will debug this bug later. [HOW] disable dcn abm feature for dcn20. Signed-off-by: hersen wu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: Refactor DIO stream encoderEric Bernstein4-9/+18
* Pull duplicate audio_clock_info struct to stream_encoder.h * Generalize sec_gsp7* to sec_gsp_pps* * Expose enc1 and enc2 stream encoder audio funcs Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: fix pstate allow handling in dcn2Jun Lei2-10/+9
[why] pstate allow/block is not being handled properly on DCN2 [how] DML needs to be updated to calculate pstate support at both min and max mpc combine rather than just min clock manager needs to update current to new pstate support before sending to pplib/smu Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: Add writeback_config to VBA varsIlya Bakoulin3-1/+3
Adding writeback_config enum to vba_vars_st, replacing old flag. Initialize to dm_normal. Signed-off-by: Ilya Bakoulin <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: Refactor clk_mgr functionsEric Yang5-82/+71
[Why] Some HW specific implementations can be pulled out into clk_mgr.c. [How] - Pull get_active_display_cnt out to clk_mgr. - Pull out shared logic in set_dispclk and set_dprefclk Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: dcn2 dmcu wait_for_loop update with dispclk.Charlene Liu1-0/+2
[Description] DMUB is using DPREF CLK, but DMCU still use displayclk. This is for updating DMCU wait_for_loop after display clock change. Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Krunoslav Kovac <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: do not power on eDP power rail earlyAnthony Koo1-3/+0
[Why] Modern Standby may toggle display adapter state between D0 and D3 state unpredictably. But events that cause transition to D0 are not always resulting in a display light up scenario. Modern eDP panels should be able to power on panel logic quickly upon VDD going high. Based on spec, the T3 time between VDD on and HPD high can be between 0 and 80 ms. Doing any tricky sorts of optimization by powering on panel VDD early during D0 transition on can negatively impact other features due to unnecessary power drain and toggling when final system state does not intend for the panel to be lit up. We need OEMs to source higher end panels that have T3 time close to 0 if they want quick S3/Modern Standby resume times. [How] Remove panel VDD power on in init_hw Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: Move link functions from dc to dc_linkChris Park1-0/+27
[Why] link-specific functions should reside in dc_link.c [How] Move them there. Signed-off-by: Chris Park <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: update calculated bounding box logic for NVJun Lei1-31/+24
[why] Current calculation of bounding box will cause DML to increase voltage state due to DPP or DISPCLK, this is unnecessary since from DML perspective we can max DPP/DISP can be supported at DPM0. This is because increasing voltage for DPP/DISP is done separately via actual minimum values of DISP and DPP CLK [how] For each calculated state, DPP, DISP, PHY, and DSC clk should always be set to maximum. FCLK, SOCCLK, and DCFCLK should be based of UCLK. Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: disable PSR/ABM before destroy DMCU structPaul Hsieh1-0/+3
[Why] 1. DMCU is not running on some platform but driver still send ABM command. It may cause assert due to DMCU is not alive. 2. To make sure PSR disable when driver disable [How] 1. Add dmcu_is_running in ABM struct, driver can check this flag to determine driver should send ABM command or not. 2. Send PSR disable command when destroy PSR Signed-off-by: Paul Hsieh <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: Ensure DRR triggers in BPEryk Brol3-2/+37
[Why] In the previous implementation DRR event sometimes came in during FP2 region which is a keep-out zone. This would cause the frame not to latch until the next frame which resulted in heavy flicker. To fix this we need to make sure that it triggers in the BP. [How] 1. Remove DRR programming during flip 2. Setup manual trigger for DRR event and trigger it after surface programming is complete Signed-off-by: Eryk Brol <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display/dc: fix azalia workaround sw implementation bughersen wu1-2/+2
caller of pp_nv_set_pme_wa_enable pass incorrect pp_smu: dc->res_pool->pp_smu. it should be dc->res_pool->pp_smu->nv_funcs.pp_smu. with incorrect input, pp->dm = NULL. This causes system crash. Signed-off-by: hersen wu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: Program VTG params after programming Global Sync for DCN2Joshua Aberback2-0/+7
[Why] VTG has a parameter FP2, which is defined as: if VSTARTUP is before VSYNC: FP2 = number of lines in between VSTARTUP and VSYNC else FP2 = 0 Currently, FP2 is only programmed during "program_timing". However, the position of VSTARTUP is affected by the prefetching requirements on all pipes, so the position might change when we do memory request control on another pipe, so we need to make sure that FP2 stays up-to-date whenever we adjust VSTARTUP. [How] - refactor VTG_CONTROL programming into a new function "set_vtg_params" - call it after calling "program_global_sync" - make sure it's called after because it relies on the cached dlg params Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Acked-by: Jun Lei <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: Add DSC support for Navi (v2)Harry Wentland48-0/+5440
Add support for DCN2 DSC (Display Stream Compression) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | | DWB | +--------+ +--------+ | v ^ +--------+ | | MPC | | +--------+ | | | v | +-------+ +-------+ | | OPP | <--> | DSC | | +-------+ +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ v2: rebase (Alex) Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amdgpu: Enable DC support for Navi10Harry Wentland2-0/+5
Enable the IP for navi10. Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)Harry Wentland3-1/+24
Enable DCN2 support in DM (Display Manager). v2: fix spurious raven change (Alex) Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: update dcn2 dc_plane_capAlex Deucher1-3/+18
To deal with rebasing the code. Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: updates for dcn20_update_bandwidthAlex Deucher1-1/+1
Pass extra parameter to validate_bandwidth() callback. Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: add fast_validate parameter to dcn20_validate_bandwidthAlex Deucher2-2/+4
To deal with changes from rebasing. Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: hook navi10 pplib functionshersen wu1-8/+271
during bring up time, before window dc-ppplib interface design, linux dc use raven dc-pplib interface. now nvai10 dc-pplib-smu interface is changed and verified under window, navi10 need its specific dc-pplib-smu interface. todo: hook set_hard_min_uclk_by_freq, get_maximum_sustainable_clocks Signed-off-by: hersen wu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/powerplay: add interface to get uclk dpm tablehersen wu1-0/+4
dc needs get uclk dpm table for bandwidth calculation Signed-off-by: hersen wu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/powrplay: add interface for dc to get max clock valueshersen wu2-0/+35
dc (display component) needs maximum clock values of uclock, socclk, dcefclk, to calculate display bandwidth. Signed-off-by: hersen wu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/armada: use mode_valid to validate the adjusted modeRussell King1-5/+14
Validate the adjusted mode in the CRTC mode_fixup() call to ensure that any encoder or bridge doesn't supply us with a mode we can't support. Signed-off-by: Russell King <[email protected]>
2019-06-22drm/armada: improve Dove clock selectionRussell King3-37/+183
Improve the Dove (Armada 510) LCD clock selection and divider calculation, limiting to the valid divisor values, and reporting an error if the clock is not achievable within the bounds of HDMI clocking requirements. Signed-off-by: Russell King <[email protected]>
2019-06-21drm/amd/display: Add DC core changes for DCN2Harry Wentland9-4/+728
Core DC changes for DCN2. Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 HW Sequencer and ResourceHarry Wentland13-1/+5246
Add DCN2 resource definition and HW Sequencer changes. Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 VMIDHarry Wentland2-0/+153
Add support to program DCN2 VMID (Virtual Memory Support) Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 IPPHarry Wentland2-0/+67
Add support to program DCN2 cursor (IPP) Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 DWBHarry Wentland9-0/+2427
Add support to program the DCN2 DWB (Display Writeback) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | | DWB | +--------+ +--------+ | v ^ +--------+ | | MPC | | +--------+ | | | v | +-------+ | | OPP | | +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 MMHUBBUBHarry Wentland2-0/+867
Add support to program the DCN2 MMHUBBUB (Multimedia HUB interface) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 HUBP and HUBBUBHarry Wentland9-2/+1739
Add support to program the DCN2 HUBP (Display to data fabric interface pipe) and HUBBUB (DCN memory HUB interface) HW Blocks: +--------++------+ | HUBBUB || HUBP | +--------++------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 DPPHarry Wentland8-0/+2261
Add support to program the DCN2 DPP (Multiple pipe and plane combine) HW Blocks: +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 MPCHarry Wentland5-1/+955
Add support to program the DCN2 MPC (Multiple pipe and plane combine) HW Blocks: +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 OPPHarry Wentland4-0/+550
Add support to program the DCN2 OPP (Output Plane Processing) HW Blocks: +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 OPTCHarry Wentland5-2/+614
Add support for programming the DCN2 OPTC (Output Timing Controller) HW Blocks: +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 clk mgrHarry Wentland12-83/+999
Adds support for handling of clocking relevant to the DCN2 block, including programming of the DCCG (Display Controller Clock Generator) block: HW Blocks: +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 DIOHarry Wentland9-0/+1397
Add support for the DIO (Display IO) block of DCN2, which entails our stream and link encoders. HW Blocks: +--------+ | DIO | +--------+ Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 changes to DMLHarry Wentland11-4/+8693
Update DML (Display Mode Lib) to support DCN2 Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 IRQ handlingHarry Wentland3-0/+405
Add support to program DCN2 IRQ handling Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 BIOS parsingHarry Wentland2-0/+10
Handle BIOS parsing for DCN2 Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add GPIO support for DCN2Harry Wentland9-0/+759
Adding support to program GPIO HW block of DCN2 Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: add AUX and I2C for DCN2Harry Wentland3-0/+64
Adding support to program DCN2 AUX and I2C HW. Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 and NV ASIC IDHarry Wentland2-0/+9
DCN2.0 (Display Core Next) is the display block in Navi10. Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: use fixed-width data type for soc bounding box structXiaojie Yuan1-15/+15
since it's firmware. Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: Split gpu_info_soc_bounding_box out from amdgpu_ucode.hLeo Li2-56/+84
DC needs to include the soc bounding box when initializing HW resources. Including amdgpu_ucode.h directly will cause warnings, since amdgpu.h is required to define amdgpu_device. The solution here is to split the bounding box structs into a different header, then include it in both amdgpu_ucode.h, and relevant DC HW resource files. Signed-off-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Read soc_bounding_box from gpu_info (v2)Harry Wentland5-1/+91
[WHY] We don't want to expose sensitive ASIC information before ASIC release. [HOW] Encode the soc_bounding_box in the gpu_info FW (for Linux) and read it at driver load. v2: fix warning when CONFIG_DRM_AMD_DC_DCN2_0 is not set (Alex) Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: notify smu with active display counthersen wu1-0/+1
when dc update clocks via smu, smu needs to know how many displays active. this interface is for dc notify number of active displays to smu. Signed-off-by: hersen wu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.