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2010-10-27ipv6: fix refcnt problem related to POSTDAD stateUrsula Braun1-1/+3
After running this bonding setup script modprobe bonding miimon=100 mode=0 max_bonds=1 ifconfig bond0 10.1.1.1/16 ifenslave bond0 eth1 ifenslave bond0 eth3 on s390 with qeth-driven slaves, modprobe -r fails with this message unregister_netdevice: waiting for bond0 to become free. Usage count = 1 due to twice detection of duplicate address. Problem is caused by a missing decrease of ifp->refcnt in addrconf_dad_failure. An extra call of in6_ifa_put(ifp) solves it. Problem has been introduced with commit f2344a131bccdbfc5338e17fa71a807dee7944fa. Signed-off-by: Ursula Braun <[email protected]> Cc: David S. Miller <[email protected]> Cc: Herbert Xu <[email protected]> Acked-by: Herbert Xu <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2010-10-27net: NETIF_F_HW_CSUM does not imply FCoE CRC offloadBen Hutchings1-3/+3
NETIF_F_HW_CSUM indicates the ability to update an TCP/IP-style 16-bit checksum with the checksum of an arbitrary part of the packet data, whereas the FCoE CRC is something entirely different. Signed-off-by: Ben Hutchings <[email protected]> Cc: [email protected] [2.6.32+] Signed-off-by: David S. Miller <[email protected]>
2010-10-27net: Fix some corner cases in dev_can_checksum()Ben Hutchings1-10/+6
dev_can_checksum() incorrectly returns true in these cases: 1. The skb has both out-of-band and in-band VLAN tags and the device supports checksum offload for the encapsulated protocol but only with one layer of encapsulation. 2. The skb has a VLAN tag and the device supports generic checksumming but not in conjunction with VLAN encapsulation. Rearrange the VLAN tag checks to avoid these. Signed-off-by: Ben Hutchings <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2010-10-27gianfar: Fix crashes on RX path (Was Re: [Bugme-new] [Bug 19692] New: ↵Jarek Poplawski1-3/+3
linux-2.6.36-rc5 crash with gianfar ethernet at full line rate traffic) The rx_recycle queue is global per device but can be accesed by many napi handlers at the same time, so it needs full skb_queue primitives (with locking). Otherwise, various crashes caused by broken skbs are possible. This patch resolves, at least partly, bugzilla bug 19692. (Because of some doubts that there could be still something around which is hard to reproduce my proposal is to leave this bug opened for a month.) Fixes commit: 0fd56bb5be6455d0d42241e65aed057244665e5e ("gianfar: Add support for skb recycling") Reported-by: emin ak <[email protected]> Tested-by: emin ak <[email protected]> Signed-off-by: Jarek Poplawski <[email protected]> CC: Andy Fleming <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2010-10-27MN10300: Save frame pointer in thread_info struct rather than global varDavid Howells15-146/+76
Save the current exception frame pointer in the thread_info struct rather than in a global variable as the latter makes SMP tricky, especially when preemption is also enabled. This also replaces __frame with current_frame() and rearranges header file inclusions to make it all compile. Signed-off-by: David Howells <[email protected]> Acked-by: Akira Takeuchi <[email protected]>
2010-10-27MN10300: Change "Matsushita" to "Panasonic".Akira Takeuchi3-5/+5
Change externally visible "Matsushita" instances to "Panasonic" throughout the MN10300 arch code. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Create a defconfig for the ASB2364 boardAkira Takeuchi1-0/+98
Create a defconfig for the ASB2364 board. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Update the ASB2303 defconfigAkira Takeuchi1-0/+2
Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: ASB2364: Add support for SMSC911X and SMC911XAkira Takeuchi8-3/+256
Add support for SMSC911X and SMC911X for the ASB2364 unit. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]> cc: [email protected] cc: [email protected]
2010-10-27MN10300: ASB2364: Handle the IRQ multiplexer in the FPGADavid Howells7-19/+166
Handle the IRQ multiplexer in the FPGA by implementing a cascade interrupt driver for it. Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Generic time supportMark Salter12-115/+401
Implement generic time support for MN10300. Signed-off-by: Mark Salter <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Specify an ELF HWCAP flag for MN10300 Atomic Operations Unit supportMark Salter1-0/+10
Use an ELF HWCAP flag to indicate to the process that the CPU provides LL/SC equivalent atomic operations unit support in addition to BSET/BCLR. Signed-off-by: Mark Salter <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Map userspace atomic op regs as a vmalloc pageMark Salter2-0/+24
The AM34 processor has an atomic operation that's the equivalent of LL/SC on other architectures. However, rather than being done through a pair of instructions, it's driven by writing to a pair of memory-mapped CPU control registers. One set of these registers (AARU/ADRU/ASRU) is available for use by userspace, but for userspace to access them a PTE must be set up to cover the region. This is done by dedicating the first vmalloc region page to this purpose, setting the permissions on its PTE such that userspace can access the page. glibc is hardcoded to expect the registers to be there. The way atomic ops are done through these registers is straightforward: (1) Write the address of the word you wish to access into AARU. This causes the CPU to go and fetch that word and load it into ADRU. The status bits are also cleared in ASRU. (2) The current data value is read from the ADRU register and modified. (3) To alter the data in RAM, the revised data is written back to the ADRU register, which causes the CPU to attempt to write it back. (4) The ASRU.RW flag (ASRU read watch), ASRU.LW flag (bus lock watch), ASRU.IW (interrupt watch) and the ASRU.BW (bus error watch) flags then must be checked to confirm that the operation wasn't aborted. If any of the watches have been set to true, the operation was aborted. Signed-off-by: Mark Salter <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: And Panasonic AM34 subarch and implement SMPAkira Takeuchi80-482/+4495
Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for MN10300. Also implement support for the MN2WS0060 processor and the ASB2364 evaluation board which are AM34 based. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Delete idle_timestamp from irq_cpustat_tAkira Takeuchi2-3/+0
Delete idle_timestamp from irq_cpustat_t as it's an unread relic. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Make various interrupt priority settings configurableAkira Takeuchi2-6/+76
Make the settings of interrupt priorities used by various services configurable at run time. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Optimise do_csum()Akira Takeuchi1-27/+22
Optimise do_csum() to gang up the loads so they're less likely to get interruptions between. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Implement atomic ops using atomic ops unitMark Salter2-47/+351
Implement atomic ops using the atomic ops unit available in the AM34 CPU. This allows the equivalent of the LL/SC instructions to be found on other CPUs. Signed-off-by: Mark Salter <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Make the FPU operate in non-lazy mode under SMPAkira Takeuchi14-248/+440
Make the FPU operate in non-lazy mode under SMP so that when the process that is currently using the FPU migrates to a different CPU, we don't have to ping its previous CPU to flush the FPU context. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: SMP TLB flushingAkira Takeuchi4-29/+290
Implement global TLB flushing for MN10300. This will be used by the AM34 which is SMP capable. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB controlAkira Takeuchi3-47/+65
Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control as the bits are a more suitable layout. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Make the use of PIDR to mark TLB entries controllableAkira Takeuchi4-62/+84
Make controllable the use of the PIDR register to mark TLB entries as belonging to particular processes. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Rename __flush_tlb*() to local_flush_tlb*()David Howells6-28/+42
Rename __flush_tlb*() to local_flush_tlb*() as it's more appropriate, and ready to differentiate local from global TLB flushes when SMP is introduced. Whilst we're at it, get rid of __flush_tlb_global() and make local_flush_tlb_page() take an mm_struct pointer rather than VMA pointer. Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: AM34 erratum requires MMUCTR read and write on exception entryAkira Takeuchi3-6/+37
An AM34 erratum requires MMUCTR read and write on entry to certain exceptions, prior to EPSW.NMID being cleared to allow NMIs to happen. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Make the boot wrapper able to use writeback cachingAkira Takeuchi1-1/+48
Make the boot wrapper able to use writeback caching, including flushing the cache before jumping to the main kernel. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Cache: Implement SMP global cache flushingAkira Takeuchi9-15/+535
Implement SMP global cache flushing for MN10300. This will be used by the AM34 which is SMP capable. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Allow some cacheflushes to be avoided if cache snooping is availableDavid Howells9-96/+309
The AM34 core is able to do cache snooping, and so can skip some of the cache flushing. Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: AM34: Add cacheflushing by using the AM34 purge registersAkira Takeuchi4-1/+678
The AM34 CPU core provides an automated way of purging the cache rather than manually iterating over all the tags in the cache. Make it possible to use these. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: SMP: Differentiate local cache flushingAkira Takeuchi4-112/+289
Differentiate local cache flushing from global cache flushing so that they can be done differently on SMP systems. Rename the cache functions from: mn10300_[id]cache_*() to: mn10300_[id]_localcache_*() and on a UP system, assign the global labels to the local labels. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Cacheflush functions should take unsigned long addressesAkira Takeuchi2-15/+15
The functions that perform cache flushing should take addresses of unsigned long type, not unsigned int. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: AM34: The current cacheflush routines operate by controlling tag regsDavid Howells4-2/+23
The current cache flush and invalidate routines operate by controlling the cache tag registers. Rename the files and add config items to select them. This makes it easier to support the use of other cache flush methods instead, such as the use of AM34's area purge registers, if available. Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Reorder asm/cacheflush.h to put primitives firstDavid Howells1-44/+44
Reorder asm/cacheflush.h to put arch primitives first, before the main functions so that the main functions can be inline asm rather than #defines when non-trivial. Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Provide a MN10300_CACHE_ENABLED config optionDavid Howells6-10/+13
Provide a MN10300_CACHE_ENABLED config option as inverted logic of MN10300_CACHE_DISABLED to make things simpler. Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Cache: Split cache bits out of arch KconfigDavid Howells2-28/+33
Split the cache bits out of arch/mn10300/Kconfig as they're quite complex. Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Remove monitor/JTAG functionsAkira Takeuchi4-55/+2
Remove the monitor trap function and the set_jtag_stub function as they're not really necessary. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Add CPU register bits for AM34Akira Takeuchi2-5/+74
Add CPU register declarations for the AM34 subarch. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Don't hard code the cacheline size in register defsAkira Takeuchi1-5/+9
Don't hard code the cacheline size in the cache control register definitions. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Move DMA engine control reg defs to MN103E010 processor directoryAkira Takeuchi2-86/+103
Move the DMA engine control register definitions to the MN103E010 processor directory so that the MN2WS0050 processor can have its own. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Differentiate AM33_2 and AM33_3 in configAkira Takeuchi1-2/+9
Differentiate AM33_2 and AM33_3 CPU cores in configuration. The MN103E010 processor contains an AM33_2 core. Whilst we're at it, prepare for AM34-based stuff by declaring AM34_2 too. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Provide the functions to fully disable maskable interruptsAkira Takeuchi1-0/+77
The local_irq_disable() function and co. merely raise the interrupt mask on the MN10300 arch to exclude normal interrupts. This still lets other, higher priority maskable interrupts through, such as are used to service gdbstub's serial port and the MN10300 on-chip serial port virtual FIFOs. Provide functions to allow the maskable interrupts to be fully disabled, which will exclude those interrupts. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Add reads[bwl]() and writes[bwl]()Akira Takeuchi1-0/+13
Add reads[bwl]() and writes[bwl]() for MN10300. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: Don't cast away the volatile in test_bit()Akira Takeuchi1-1/+1
Don't cast away the volatile in test_bit()'s parameter when we change its type from const volatile void * so that we can dereference it. Signed-off-by: Akira Takeuchi <[email protected]> Signed-off-by: Kiyoshi Owada <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27Typedef SMP call function pointerDavid Howells2-13/+14
Typedef the pointer to the function to be called by smp_call_function() and friends: typedef void (*smp_call_func_t)(void *info); as it is used in a fair number of places. Signed-off-by: David Howells <[email protected]> cc: [email protected]
2010-10-27MN10300: Prevent cnt32_to_63() from being preempted in sched_clock()David Howells1-0/+5
Prevent cnt32_to_63() from being preempted in sched_clock() because it may read its internal counter, get preempted, get delayed for more than the half period of the 'TSC' and then write the internal counter, thus corrupting it. Whilst some callers of sched_clock() have interrupts disabled or hold spinlocks, not all do, and so preemption must be held here. Note that sched_clock() is called from lockdep, but that shouldn't be a problem because although preempt_disable() calls into lockdep, lockdep has a recursion counter to deal with this. Signed-off-by: David Howells <[email protected]>
2010-10-27mn10300: Use pci_claim_resourceDavid Howells1-10/+6
Instead of open-coding pci_find_parent_resource and request_resource, just call pci_claim_resource. Signed-off-by: Matthew Wilcox <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27bitops: Change the bitmap index from int to unsigned long [mn10300]Justin Chen2-8/+8
Change the index to unsigned long in all bitops for [mn10300] Signed-off-by: Justin Chen <[email protected]> Reviewed-by: Bjorn Helgaas <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27MN10300: BUG to BUG_ON changesStoyan Gaydarov5-10/+5
Signed-off-by: Stoyan Gaydarov <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27Partially revert patch that encloses asm-offset.h numbers in bracketsDavid Howells1-1/+1
Partially revert patch: commit 3234282f33b29d349bcada40204fc7c8fda7fe72 Author: Jan Beulich <[email protected]> Date: Tue Oct 19 14:52:26 2010 +0100 x86, asm: Fix CFI macro invocations to deal with shortcomings in gas This breaks MN10300 arch as this changes many instances of instructions similar to the following: MOV number,D0 which represents an immediate value load into: MOV (number),D0 which the assembler then interprets as a load from absolute address. arch/mn10300/kernel/entry.S:64: Error: Invalid opcode/operands arch/mn10300/kernel/entry.S:65: Error: junk at end of line, first unrecognized character is `0' arch/mn10300/kernel/entry.S:74: Error: Invalid opcode/operands arch/mn10300/kernel/entry.S:74: Error: junk at end of line, first unrecognized character is `1' arch/mn10300/kernel/entry.S:75: Error: Invalid opcode/operands arch/mn10300/kernel/entry.S:76: Error: junk at end of line, first unrecognized character is `0' cc: Jan Beulich <[email protected]> cc: Alexander van Heukelum <[email protected]> cc: H. Peter Anvin <[email protected]> cc: Ingo Molnar <[email protected]> Signed-off-by: David Howells <[email protected]>
2010-10-27percpu: Remove the multi-page alignment facilityIngo Molnar1-12/+0
[DECLARE|DEFINE]_PER_CPU_MULTIPAGE_ALIGNED never really worked because the head percpu section was only page aligned. Now that the last user is gone (32-bit IRQ stacks), remove the generic percpu facility. Cc: Brian Gerst <[email protected]> Acked-by: Tejun Heo <[email protected]> Acked-by: Linus Torvalds <[email protected]> LKML-Reference: <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
2010-10-27x86-32: Allocate irq stacks seperate from percpu areaBrian Gerst3-13/+2
The percpu allocator cannot handle alignments larger than one page. Allocate the irq stacks seperately, and only keep the pointers as percpu data. Signed-off-by: Brian Gerst <[email protected]> Acked-by: Linus Torvalds <[email protected]> Cc: [email protected] LKML-Reference: <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
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