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2021-05-31arm64: dts: qcom: sc7180: lazor: Simplify disabling of charger thermal zoneMatthias Kaehlcke4-27/+9
Commit f73558cc83d1 ("arm64: dts: qcom: sc7180: Disable charger thermal zone for lazor") disables the charger thermal zone for specific lazor revisions due to an unsupported thermistor type. The initial idea was to disable the thermal zone for older revisions and leave it enabled for newer ones that use a supported thermistor. Finally the thermistor won't be changed on newer revisions, hence the thermal zone should be disabled for all lazor (and limozeen) revisions. Instead of disabling it per revision do it once in the shared .dtsi for lazor. Signed-off-by: Matthias Kaehlcke <[email protected]> Reviewed-by: Douglas Anderson <[email protected]> Link: https://lore.kernel.org/r/20210322094628.v4.1.I6d587e7ae72a5a47253bb95dfdc3158f8cc8a157@changeid Signed-off-by: Bjorn Andersson <[email protected]>
2021-05-31arm64: dts: qcom: sc7180: Remove QUP-CORE ICC pathRoja Rani Yarubandi1-4/+0
We had introduced the QUP-CORE ICC path to put proxy votes from QUP wrapper on behalf of earlycon, if other users of QUP-CORE turn off this clock before the real console is probed, unclocked access to HW was seen from earlycon. With ICC sync state support proxy votes are no longer need as ICC will ensure that the default bootloader votes are not removed until all it's consumer are probed. We can safely remove ICC path for QUP-CORE clock from QUP wrapper device. Signed-off-by: Roja Rani Yarubandi <[email protected]> Signed-off-by: Akash Asthana <[email protected]> Reviewed-by: Matthias Kaehlcke <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-05-31arm64: dts: qcom: sm8350: fix the node unit addressesVinod Koul1-3/+3
Some node unit addresses were put wrongly in the dts, resulting in below warning when run with W=1 arch/arm64/boot/dts/qcom/sm8350.dtsi:693.34-702.5: Warning (simple_bus_reg): /soc@0/thermal-sensor@c222000: simple-bus unit address format error, expected "c263000" arch/arm64/boot/dts/qcom/sm8350.dtsi:704.34-713.5: Warning (simple_bus_reg): /soc@0/thermal-sensor@c223000: simple-bus unit address format error, expected "c265000" arch/arm64/boot/dts/qcom/sm8350.dtsi:1180.32-1185.5: Warning (simple_bus_reg): /soc@0/interconnect@90e0000: simple-bus unit address format error, expected "90c0000" Fix by correcting to the correct address as given in reg node Reviewed-by: Robert Foss <[email protected]> Signed-off-by: Vinod Koul <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-05-31arm64: dts: qcom: sm8350: use interconnect enumsVinod Koul1-2/+3
Add interconnect enums instead of numbers now that interconnect is in mainline. Reviewed-by: Bhupesh Sharma <[email protected]> Signed-off-by: Vinod Koul <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-05-31arm64: dts: qcom: sm8150: Add DMA nodesFelipe Balbi1-0/+70
With this patch, DMA has a chance of probing and doing something useful. Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Signed-off-by: Felipe Balbi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-05-31arm64: dts: qcom: msm8916-alcatel-idol347: enable touchscreenVincent Knecht1-0/+26
Enable the MStar msg2638 touchscreen. Reviewed-by: Stephan Gerhold <[email protected]> Signed-off-by: Vincent Knecht <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-05-31arm64: dts: qcom: msm8996: Rename speedbin nodeLoic Poulain1-2/+2
The speedbin value blown in the efuse is used to determine is used to determine the voltage and frequency value for different IPs, including GPU, CPUs... So it's really not a gpu specific information. This patch simply renames 'gpu_speed_bin' node to 'speedbin'. Signed-off-by: Loic Poulain <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-05-31arm64: dts: qcom: ipq8074: disable USB phy by defaultRobert Marko1-0/+1
One of the QUSB USB PHY-s has been left enabled by default, this is probably just a mistake as other USB PHY-s are disabled by default. It makes no sense to have it enabled by default as not all board implement USB ports, so disable it. Reviewed-by: Kathiravan T <[email protected]> Signed-off-by: Robert Marko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-05-31ARM: dts: qcom: Enable NAND + USB for RB3011Jonathan McDowell1-0/+58
Enable the NAND + USB devices for the MikroTik RB3011 platform now they're in the main IPQ806x DT. Signed-off-by: Jonathan McDowell <[email protected]> Link: https://lore.kernel.org/r/1e5c89ba0d2491ca374f10e0446e21d0e42afd34.1621531633.git.noodles@earth.li Signed-off-by: Bjorn Andersson <[email protected]>
2021-05-31ARM: dts: qcom: add L2CC and RPM for IPQ8064Jonathan McDowell1-0/+29
This adds the L2CC IPC resource and RPM devices to the IPQ8064 device tree. Tested on a Mikrotik RB3011. Signed-off-by: Jonathan McDowell <[email protected]> Link: https://lore.kernel.org/r/a99eb2a27214b8f41070d7f1faec591e35666b21.1621531633.git.noodles@earth.li Signed-off-by: Bjorn Andersson <[email protected]>
2021-05-31ARM: dts: qcom: Add USB port definitions to ipq806xJonathan McDowell1-0/+88
Signed-off-by: Jonathan McDowell <[email protected]> Link: https://lore.kernel.org/r/ad2121defc539abdb339b23eef80a8930b5f086e.1621531633.git.noodles@earth.li Signed-off-by: Bjorn Andersson <[email protected]>
2021-05-31ARM: dts: qcom: Add tsens details to ipq806xJonathan McDowell1-0/+241
Signed-off-by: Jonathan McDowell <[email protected]> Link: https://lore.kernel.org/r/f7ebf47ca9e7e973e696e6b9b4fff3a2ac5da40d.1621531633.git.noodles@earth.li Signed-off-by: Bjorn Andersson <[email protected]>
2021-05-31ARM: dts: qcom: Add ADM DMA + NAND definitions to ipq806xJonathan McDowell1-0/+67
Now the ADM driver is in mainline add the appropriate definitions for it and the NAND controller to get NAND working on IPQ806x platforms, Signed-off-by: Jonathan McDowell <[email protected]> Link: https://lore.kernel.org/r/17f88a26860f5976ad08dd3c12ea079ba474b6fd.1621531633.git.noodles@earth.li Signed-off-by: Bjorn Andersson <[email protected]>
2021-05-31ARM: dts: exynos: Disable unused camera input for I9100Timon Baetz1-2/+4
As the back camera is not implemented disable the second pair of fimc child nodes as they are not functional. This prevents creating the associated /dev/videoX devices. Signed-off-by: Timon Baetz <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2021-05-31ARM: dts: stm32: Rework LAN8710Ai PHY reset on DHCOM SoMMarek Vasut1-1/+7
The Microchip LAN8710Ai PHY requires XTAL1/CLKIN external clock to be enabled when the nRST is toggled according to datasheet Microchip LAN8710A/LAN8710Ai DS00002164B page 35 section 3.8.5.1 Hardware Reset: " A Hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held low for the minimum time detailed in Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on page 59 to ensure a proper transceiver reset. During a Hardware reset, an external clock must be supplied to the XTAL1/CLKIN signal. " This is accidentally fulfilled in the current setup, where ETHCK_K is used to supply both PHY XTAL1/CLKIN and is also fed back through eth_clk_fb to supply ETHRX clock of the DWMAC. Hence, the DWMAC enables ETHRX clock, that has ETHCK_K as parent, so ETHCK_K clock are also enabled, and then the PHY reset toggles. However, this is not always the case, e.g. in case the PHY XTAL1/CLKIN clock are supplied by some other clock source than ETHCK_K or in case ETHRX clock are not supplied by ETHCK_K. In the later case, ETHCK_K would be kept disabled, while ETHRX clock would be enabled, so the PHY would not be receiving XTAL1/CLKIN clock and the reset would fail. Improve the DT by adding the PHY clock phandle into the PHY node, which then also requires moving the PHY reset GPIO specifier in the same place and that then also requires correct PHY reset GPIO timing, so add that too. A brief note regarding the timing, the datasheet says the reset should stay asserted for at least 100uS and software should wait at least 200nS after deassertion. Set both delays to 500uS which should be plenty. Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2021-05-31dt-bindings: clock: tegra: Convert to schemaDmitry Osipenko7-352/+184
Convert NVIDIA Tegra clock bindings to schema. Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2021-05-31ARM: dts: sun8i: v3s: enable emac for zero DockAndreas Rehn1-4/+13
dwmac-sun8i supports v3s and Licheepi-zero Dock provides an ethernet port furthermore, align nodes in alphabetical order Signed-off-by: Andreas Rehn <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-05-31ARM: tegra: ouya: Enable memory frequency thermal throttling using ACTMONDmitry Osipenko1-1/+3
The ACTMON module monitors activity of memory clients and then devfreq driver makes decisions about a required memory frequency based on info from ACTMON. Add ACTMON device to the thermal zone of Ouya in order to use it as a cooling device which throttles memory freq on overheat. Tested-by: Peter Geis <[email protected]> Tested-by: Matt Merhar <[email protected]> Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2021-05-31ARM: tegra: nexus7: Enable memory frequency thermal throttling using ACTMONDmitry Osipenko1-1/+3
The ACTMON module monitors activity of memory clients and then devfreq driver makes decisions about a required memory frequency based on info from ACTMON. Add ACTMON device to the thermal zone of Nexus 7 in order to use it as a cooling device which throttles memory freq on overheat. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2021-05-31ARM: tegra: Add cooling cells to ACTMON device-tree nodeDmitry Osipenko2-2/+4
The ACTMON module monitors activity of memory clients and decisions about a minimum required memory frequency are made based on info from ACTMON. Add cooling cells to ACTMON device-tree node in order to turn it into a cooling device that will throttle memory freq on overheat. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2021-05-31ARM: tegra: nexus7: Correct 3v3 regulator GPIO of PM269 variantDmitry Osipenko1-1/+1
The 3v3 regulator GPIO is GP6 and not GP7, which is the DDR regulator. Both regulators are always-on, nevertheless the DT model needs to be corrected, fix it. Reported-by: Svyatoslav Ryhel <[email protected]> Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2021-05-31ARM: tegra: nexus7: Remove monitored-battery propertyDmitry Osipenko1-1/+0
The bq27541 Linux kernel driver will try to reprogram controller based on the values from monitored-battery node, but it fails to do so because controller was locked by manufacturer. Still this is a very undesirable behaviour, hence let's remove the optional battery node. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2021-05-31ARM: tegra: nexus7: Improve thermal zonesDmitry Osipenko1-9/+2
Remove unused thermal zone just to clean up device-tree and set critical temperature further apart from the passive cooling trip point since during or thermal testing of Asus Transformer devices we found that CPU could reach the critical temperature in a certain kernel configurations for a brief moment if critical trip point is set close to the passive trip point and then device will be immediately shut off without getting a chance to cool down using passive cooling. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2021-05-31ARM: tegra: nexus7: Add i2c-thermtrip nodeDmitry Osipenko2-0/+18
Add i2c-thermtrip node which enables emergency shutdown by PMC on SoC die overheat detected by TSENSOR. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2021-05-31ARM: tegra: paz00: Add CPU thermal zoneDmitry Osipenko1-2/+40
Add thermal zone with a passive cooling trip for CPU. Attach it to the LM90 sensor which monitors CPU temperature. Now CPU frequencies will be throttled once trip point is reached, preventing critical overheat. Tested-by: Agneli <[email protected]> Tested-by: Paul Fertser <[email protected]> Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2021-05-31ARM: tegra: wm8903: Fix polarity of headphones-detection GPIO in device-treesDmitry Osipenko8-8/+8
All Tegra boards which use WM8903 audio codec are specifying a wrong polarity for the headphones detection GPIO. The kernel driver hardcodes the polarity to active-low, which is the correct polarity, so we can fix the device-trees safely. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2021-05-31ARM: tegra: Add reg property to Tegra20 EMC table device-tree nodesDmitry Osipenko2-0/+5
The reg property is now specified for the emc-tables nodes in the Tegra20 device-tree binding. Add reg property to the EMC table device-tree nodes of Tegra20 board device-trees in order to silence dt_binding_check warning about the missing property. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2021-05-31ARM: tegra: acer-a500: Bump thermal trips by 10CDmitry Osipenko1-4/+4
It's possible to hit the temperature of the thermal zone in a very warm environment under a constant load, like watching a video using software decoding. It's even easier to hit the limit with a slightly overclocked CPU. Bump the temperature limit by 10C in order to improve user experience. Acer A500 has a large board and 10" display panel which are used for the heat dissipation, the SoC is placed far away from battery, hence we can safely bump the temperature limit. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2021-05-31ARM: tegra: acer-a500: Specify proper voltage for WiFi SDIO busDmitry Osipenko1-1/+1
Tegra20 has v2.00 SDMMC controller which doesn't support voltage switching and the WiFi SDIO bus voltage is fixed to 1.8v in accordance to the board's schematics, while MMC core confusingly saying that it's 3.3v because of the v2.00. Let's correct the voltage in the device-tree just for consistency. This is a minor improvement which doesn't fix any problems. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2021-05-31ARM: tegra: acer-a500: Improve microphone detectionDmitry Osipenko1-1/+4
Use edge-triggered interrupt and set delay to 100ms for microphone hook detection. This doesn't fix any known problems, but there is a smaller chance to miss insertion of the microphone now, which previously happened rarely. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2021-05-31ARM: dts: silk: Configure pull-up for SOFT_SW GPIO keysGeert Uytterhoeven1-1/+9
The GPIO pins connected to the 4 Software Switches ("SOFT_SW", SW12) do not have external pull-up resistors, but rely on internal pull-ups being enabled. Fortunately this is satisfied by the initial state of these pins. Make this explicit by enabling bias-pull-up, to remove the dependency on initial state and/or boot loader configuration. While at it, rename the surrounding device node from "gpio-keys" to "keyboard", to comply with generic node name recommendations. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/45f38a5333feba9bea80efeb5a41a6c3f60deda2.1619785905.git.geert+renesas@glider.be
2021-05-31ARM: dts: gose: Configure pull-up for SOFT_SW GPIO keysGeert Uytterhoeven1-1/+9
The GPIO pins connected to the 4 Software Switches ("SOFT_SW", SW2) do not have external pull-up resistors, but rely on internal pull-ups being enabled. Fortunately this is satisfied by the initial state of these pins. Make this explicit by enabling bias-pull-up, to remove the dependency on initial state and/or boot loader configuration. While at it, rename the surrounding device node from "gpio-keys" to "keyboard", to comply with generic node name recommendations. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/1cdec892b1491309b12bdaf7bc8428b3a19b1ed5.1619785905.git.geert+renesas@glider.be
2021-05-31ARM: dts: blanche: Configure pull-up for SOFT_SW and SW25 GPIO keysGeert Uytterhoeven1-0/+8
The GPIO pins connected to the 4 Software Switches (SW2) and the second Tact Switch (SW25) do not have external pull-up resistors, but rely on internal pull-ups being enabled. Fortunately this is satisfied by the initial state of these pins. Make this explicit by enabling bias-pull-up, to remove the dependency on initial state and/or boot loader configuration. Note that the GPIO pin connected to the first Tact Switch (SW24) does have an external pull-up resistor. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/011e4c461767f2dd690b655b3dd501eb554184c1.1619785905.git.geert+renesas@glider.be
2021-05-31ARM: dts: lager: Configure pull-up for SOFT_SW GPIO keysGeert Uytterhoeven1-0/+8
The GPIO pins connected to the 4 Software Switches (SW2) do not have external pull-up resistors, but rely on internal pull-ups being enabled. Fortunately this is satisfied by the initial state of these pins. Make this explicit by enabling bias-pull-up, to remove the dependency on initial state and/or boot loader configuration. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Wolfram Sang <[email protected]> Tested-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/9fae3c0c2c0000f6b43c9ce87fe64a594b30a7da.1619785905.git.geert+renesas@glider.be
2021-05-31arm64: dts: renesas: r8a7796[01]: Fix OPP table entry voltagesGeert Uytterhoeven2-6/+6
Correct the voltages in the "Power Optimized" (<= 1.5 GHz) Cortex-A57 operating point table entries for the R-Car M3-W and M3-W+ SoCs from 0.82V to 0.83V, as per the R-Car Gen3 EC Manual Errata for Revision 0.53. Based on a patch for R-Car M3-W in the BSP by Takeshi Kihara <[email protected]>. Fixes: da7e3113344fda50 ("arm64: dts: renesas: r8a7796: Add OPPs table for cpu devices") Fixes: f51746ad7d1ff6b4 ("arm64: dts: renesas: Add Renesas R8A77961 SoC support") Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/b9e9db907514790574429b83d070c823b36085ef.1619699909.git.geert+renesas@glider.be
2021-05-31arm64: dts: renesas: Add missing opp-suspend propertiesGeert Uytterhoeven3-0/+3
Tag the highest "Power Optimized" (1.5 GHz) Cortex-A57 operating point table entries for the RZ/G2M, R-Car M3-W and M3-W+ SoCs with the "opp-suspend" property. This makes sure the system will enter suspend in the same performance state as it will be resumed by the firmware later, avoiding state inconsistencies after resume. Based on a patch for R-Car M3-W in the BSP by Takeshi Kihara <[email protected]>. Fixes: 800037e815b91d8c ("arm64: dts: renesas: r8a774a1: Add operating points") Fixes: da7e3113344fda50 ("arm64: dts: renesas: r8a7796: Add OPPs table for cpu devices") Fixes: f51746ad7d1ff6b4 ("arm64: dts: renesas: Add Renesas R8A77961 SoC support") Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Niklas Söderlund <[email protected]> Link: https://lore.kernel.org/r/45a061c3b0463aac7d10664f47c4afdd999da50d.1619699721.git.geert+renesas@glider.be
2021-05-28arm64: tegra: Consolidate audio card namesThierry Reding6-9/+9
The current scheme for audio card names is suboptimal because it causes the automatically generated names (for ID and driver) to be truncated, which in turn can cause conflicts. Introduce a new scheme which reuses the board model for the names and appends the "HDA" and "APE" suffixes for the HDA and APE, respectively. As a side-effect these suffixes end up being used as the ID of the SoC sound cards which makes it easy for users to select them when using the ALSA command-line utilities, for example. As a separate measure, the driver name for the cards is now set by the corresponding audio driver (either tegra-hda or tegra-ape), making it a more useful identifier than the currently normalized card name. Signed-off-by: Thierry Reding <[email protected]>
2021-05-28arm64: tegra: Add PMU node for Tegra194Jon Hunter1-0/+14
Populate the device-tree node for the PMU device on Tegra194. This also fixes the following warning that is observed on booting Tegra194. ERR KERN kvm: pmu event creation failed -2 Signed-off-by: Jon Hunter <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2021-05-28arm64: dts: meson-sm1: add Banana PI BPI-M5 board dtsNeil Armstrong2-0/+647
Banana Pi BPI-M5 is a credit card format SBC with the following features: - Amlogic S905X3 quad core Cortex-A55 - Mali-G31 GPU - 4GB LPDDR4 - 16GB eMMC flash - 4 USB 3.0 - 1 GbE ethernet - HDMI output - 2x LEDS - SDCard - 2.5mm Jack with Stereo Audio + CVBS - Infrared Received - ADC Button - GPIO Button - 40 pins header + 3pins debug header Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Martin Blumenstingl <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-05-28dt-bindings: arm: amlogic: add Banana PI M5 bindingsNeil Armstrong1-0/+1
Add bindings for the Banana PI M5 board. Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Martin Blumenstingl <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-05-28arm64: dts: meson-sm1: add toacodec nodeNeil Armstrong1-0/+10
Add toacodec node for Amlogic SM1 SoCs. Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-05-28arm64: dts: meson: vim3: enable hdmi audio loopbackJerome Brunet2-4/+50
Enable audio capture frontends and a tdm decoder. This makes it possible to loopback the audio played on the hdmi codec, which is the only output interface at the moment. Of course, one TODDR device would be enough to do that but since the 3 FRDDRs are enabled on the playback side, let's do the same on the capture side. Signed-off-by: Jerome Brunet <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Kevin Hilman <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-05-27ARM: dts: alt: Add SW2 as GPIO keysWolfram Sang1-0/+42
SW2 on Alt is connected as on Lager board. So, use the same GPIO settings. Signed-off-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-05-27ARM: dts: OMAP2+: Replace underscores in sub-mailbox node namesSuman Anna8-20/+20
A number of sub-mailbox node names in various OMAP2+ dts files are currently using underscores. This is not adhering to the node name convention, fix all of these to use hiphens. These nodes are already using the prefix mbox, so they will be in compliance with the sub-mailbox node name convention being added in the OMAP Mailbox YAML binding as well. Signed-off-by: Suman Anna <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2021-05-27ARM: dts: AM33xx/AM43xx: Rename wkup_m3 sub-mailbox nodeSuman Anna2-2/+2
The OMAP sub-mailbox used to communicate with the Wakeup M3 remote processor is currently named wkup_m3. This name can be confused with the remote processor node. So, rename this to mbox-wkup-m3 to remove the ambiguity and to also adhere to the sub-mailbox node name convention being added in the OMAP Mailbox YAML binding. Signed-off-by: Suman Anna <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2021-05-27ARM: dts: OMAP2/OMAP3: Rename processor sub-mailbox nodesSuman Anna3-4/+4
The OMAP sub-mailbox used to communicate with the DSP and IVA remote processors are currently named after the processor name. These can be confused with the remote processors themselves. Rename them to remove the ambiguity and use the prefix mbox to also adhere to the sub-mailbox node name convention being added in the OMAP Mailbox YAML binding. Signed-off-by: Suman Anna <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2021-05-27ARM: dts: OMAP2420: Drop interrupt-names from mailbox nodeSuman Anna1-1/+0
The interrupt-names property is neither defined nor used in either of the OMAP Mailbox binding or the driver. So, drop them. This is in preparation for converting the OMAP Mailbox binding to YAML format. Signed-off-by: Suman Anna <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2021-05-27ARM: dts: am437x-l4: Drop ti,omap2-uart entry from UART nodesVignesh Raghavendra1-6/+6
ti,omap2-uart was kept around to work with legacy omap-serial driver. Now that we have completed move to 8250-omap.c drop legacy compatible. This will simplify writing YAML schema. Signed-off-by: Vignesh Raghavendra <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2021-05-27ARM: dts: dra7-l4: Drop ti,omap4-uart entry from UART nodesVignesh Raghavendra1-10/+10
ti,omap4-uart was kept around to work with legacy omap-serial driver. Now that we have completed move to 8250-omap.c drop legacy compatible. This will simplify writing YAML schema. Signed-off-by: Vignesh Raghavendra <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2021-05-27ARM: dts: am335x: fix ti,no-reset-on-init flag for gpiosGrygorii Strashko5-6/+6
The ti,no-reset-on-init flag need to be at the interconnect target module level for the modules that have it defined. The ti-sysc driver handles this case, but produces warning, not a critical issue. Signed-off-by: Grygorii Strashko <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
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