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2024-06-17dt-bindings: pinctrl: aspeed,ast2500-pinctrl: Describe SGPMAndrew Jeffery1-0/+1
Squash warnings such as: arch/arm/boot/dts/aspeed/aspeed-ast2500-evb.dtb: pinctrl@80: sgpm_default:groups:0: 'SGPM' is not one of ['ACPI', 'ADC0', 'ADC1', 'ADC10', 'ADC11', 'ADC12', 'ADC13', 'ADC14', 'ADC15', 'ADC2', 'ADC3', 'ADC4', 'ADC5', 'ADC6', 'ADC7', 'ADC8', 'ADC9', 'BMCINT', 'DDCCLK', 'DDCDAT', 'ESPI', 'FWSPICS1', 'FWSPICS2', 'GPID0', 'GPID2', 'GPID4', 'GPID6', 'GPIE0', 'GPIE2', 'GPIE4', 'GPIE6', 'I2C10', 'I2C11', 'I2C12', 'I2C13', 'I2C14', 'I2C3', 'I2C4', 'I2C5', 'I2C6', 'I2C7', 'I2C8', 'I2C9', 'LAD0', 'LAD1', 'LAD2', 'LAD3', 'LCLK', 'LFRAME', 'LPCHC', 'LPCPD', 'LPCPLUS', 'LPCPME', 'LPCRST', 'LPCSMI', 'LSIRQ', 'MAC1LINK', 'MAC2LINK', 'MDIO1', 'MDIO2', 'NCTS1', 'NCTS2', 'NCTS3', 'NCTS4', 'NDCD1', 'NDCD2', 'NDCD3', 'NDCD4', 'NDSR1', 'NDSR2', 'NDSR3', 'NDSR4', 'NDTR1', 'NDTR2', 'NDTR3', 'NDTR4', 'NRI1', 'NRI2', 'NRI3', 'NRI4', 'NRTS1', 'NRTS2', 'NRTS3', 'NRTS4', 'OSCCLK', 'PEWAKE', 'PNOR', 'PWM0', 'PWM1', 'PWM2', 'PWM3', 'PWM4', 'PWM5', 'PWM6', 'PWM7', 'RGMII1', 'RGMII2', 'RMII1', 'RMII2', 'RXD1', ' RXD2', 'RXD3', 'RXD4', 'SALT1', 'SALT10', 'SALT11', 'SALT12', 'SALT13', 'SALT14', 'SALT2', 'SALT3', 'SALT4', 'SALT5', 'SALT6', 'SALT7', 'SALT8', 'SALT9', 'SCL1', 'SCL2', 'SD1', 'SD2', 'SDA1', 'SDA2', 'SGPS1', 'SGPS2', 'SIOONCTRL', 'SIOPBI', 'SIOPBO', 'SIOPWREQ', 'SIOPWRGD', 'SIOS3', 'SIOS5', 'SIOSCI', 'SPI1', 'SPI1CS1', 'SPI1DEBUG', 'SPI1PASSTHRU', 'SPI2CK', 'SPI2CS0', 'SPI2CS1', 'SPI2MISO', 'SPI2MOSI', 'TIMER3', 'TIMER4', 'TIMER5', 'TIMER6', 'TIMER7', 'TIMER8', 'TXD1', 'TXD2', 'TXD3', 'TXD4', 'UART6', 'USB11BHID', 'USB2AD', 'USB2AH', 'USB2BD', 'USB2BH', 'USBCKI', 'VGABIOSROM', 'VGAHS', 'VGAVS', 'VPI24', 'VPO', 'WDTRST1', 'WDTRST2'] Signed-off-by: Andrew Jeffery <[email protected]> Acked-by: Rob Herring (Arm) <[email protected]> Link: https://lore.kernel.org/r/20240531-dt-warnings-gpio-ast2600-pinctrl-funcs-groups-v1-2-a6fe2281a1b8@codeconstruct.com.au Signed-off-by: Linus Walleij <[email protected]>
2024-06-17dt-bindings: pinctrl: aspeed: Use block syntax for function and groupsAndrew Jeffery3-83/+774
The expansion makes the documents a lot longer, but it's easier to review changes to functions and groups when we're not having to deal with line wrapping. Signed-off-by: Andrew Jeffery <[email protected]> Acked-by: Rob Herring (Arm) <[email protected]> Link: https://lore.kernel.org/r/20240531-dt-warnings-gpio-ast2600-pinctrl-funcs-groups-v1-1-a6fe2281a1b8@codeconstruct.com.au Signed-off-by: Linus Walleij <[email protected]>
2024-06-17Merge tag 'renesas-pinctrl-for-v6.11-tag1' of ↵Linus Walleij6-236/+652
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.11 - Add support for the new RZ/V2H(P) (R9A09G057) Soc, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: keembay: Fix func conversion in keembay_build_functions()Nathan Chancellor1-1/+1
A recent refactoring to use the func member in struct function_desc missed converting one uses of name in keembay_build_functions(), resulting in a build failure: drivers/pinctrl/pinctrl-keembay.c: In function 'keembay_build_functions': drivers/pinctrl/pinctrl-keembay.c:1630:35: error: 'struct function_desc' has no member named 'name' 1630 | if (!fdesc->name) { | ^~ Perform the same conversion to resolve the build error. Fixes: 73ee52205e5a ("pinctrl: keembay: Convert to use func member") Signed-off-by: Nathan Chancellor <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/20240611-pinctrl-keembay-fix-func-conversion-v1-1-3197f2ded3f7@kernel.org Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: imx: support SCMI pinctrl protocol for i.MX95Peng Fan3-0/+367
The generic pinctrl-scmi.c driver could not be used for i.MX95 because i.MX95 SCMI firmware not supports functions, groups or generic 'Pin Configuration Type and Enumerations' listed in SCMI Specification. i.MX95 System Control Management Interface(SCMI) firmware only supports below pin configuration types which are OEM specific types: 192: PIN MUX 193: PIN CONF 194: DAISY ID 195: DAISY VAL To Support fsl,pins property together with SCMI OEM protocol, add this driver. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Cristian Marussi <[email protected]> Acked-by: Sudeep Holla <[email protected]> Reviewed-by: Dong Aisheng <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: scmi: add blocklistPeng Fan1-0/+9
i.MX95 will have its own pinctrl scmi driver, so need block pinctrl-scmi driver for i.MX95, otherwise there will be two pinctrl devices for a single scmi protocol@19. Signed-off-by: Peng Fan <[email protected]> Acked-by: Sudeep Holla <[email protected]> Reviewed-by: Dong Aisheng <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17dt-bindings: firmware: arm,scmi: Add properties for i.MX95 Pinctrl OEM ↵Peng Fan2-1/+56
extensions i.MX95 Pinctrl is managed by System Control Management Interface(SCMI) firmware using OEM extensions. No functions, no groups are provided by the firmware. So add i.MX95 specific properties. To keep aligned with current i.MX pinctrl bindings, still use "fsl,pins" for i.MX95. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]> Reviewed-by: Dong Aisheng <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: qcom: sdm670: add pdc wakeirq mapRichard Acayan1-0/+19
The PDC was hooked up as a wakeup parent in the DTS in commit 71f080633d1e ("arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM"), but the wakeirq mapping was not defined so it had no effect. Add the mapping for wakeup interrupts on the PDC to their corresponding pins. Configuring a pin IRQ as dual-edge would break it unless the wakeirq_dual_edge_errata flag is set. Signed-off-by: Richard Acayan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: cy8c95x0: Use REGCACHE_MAPLEPatrick Rudolph1-1/+1
Use REGCACHE_MAPLE instead of REGCACHE_FLAT. Signed-off-by: Patrick Rudolph <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: cy8c95x0: Use regmap rangesPatrick Rudolph1-126/+53
Instead of implementing a custom register paging mechanism in the driver use the existing regmap ranges feature. Signed-off-by: Patrick Rudolph <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: cy8c95x0: Use single I2C lockPatrick Rudolph1-15/+17
Currently there are 3 locks being used when accessing the chip, one in the driver and one in each regmap. Reduce that to one driver only lock that protects all regmap and regcache accesses. Signed-off-by: Patrick Rudolph <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: pinmux: Remove unused members from struct function_descAndy Shevchenko1-9/+0
All drivers are converted to use embedded struct pinfunction. Remove unused members from struct function_desc. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: mediatek: moore: Convert to use func memberAndy Shevchenko2-8/+6
Convert drivers to use func member embedded in struct function_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin function description. Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: keembay: Convert to use func memberAndy Shevchenko1-11/+11
Convert drivers to use func member embedded in struct function_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin function description. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: ingenic: Convert to use func memberAndy Shevchenko1-9/+7
Convert drivers to use func member embedded in struct function_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin function description. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: imx: Convert to use func memberAndy Shevchenko1-7/+7
Convert drivers to use func member embedded in struct function_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin function description. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: pinmux: Embed struct pinfunction into struct function_descAndy Shevchenko2-6/+9
struct function_desc is a particular version of the struct pinfunction with associated opaque data. Start switching pin control core and drivers to use it explicitly. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: pinmux: Add a convenient define PINCTRL_FUNCTION_DESC()Andy Shevchenko3-8/+14
Add PINCTRL_FUNCTION_DESC() macro for inline use. While at it, fix adjective form in the comment of PINCTRL_GROUP_DESC(). Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: mediatek: moore: Provide a helper macro PINCTRL_PIN_FUNCTION()Andy Shevchenko6-76/+84
Provide a helper macro to assign the struct function_desc entries. This helps further refactoring. Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: ingenic: Provide a helper macro INGENIC_PIN_FUNCTION()Andy Shevchenko1-345/+352
Provide a helper macro to assign the struct function_desc entries. This helps further refactoring. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: equilibrium: Make use of struct pinfunctionAndy Shevchenko2-23/+13
Since pin control provides a generic data type for the pin function, use it in the driver. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: berlin: Make use of struct pinfunctionAndy Shevchenko2-18/+9
Since pin control provides a generic data type for the pin function, use it in the driver. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: rockchip: update rk3308 iomux routesDmitry Yashin1-15/+2
Some of the rk3308 iomux routes in rk3308_mux_route_data belong to the rk3308b SoC. Remove them and correct i2c3 routes. Fixes: 7825aeb7b208 ("pinctrl: rockchip: add rk3308 SoC support") Signed-off-by: Dmitry Yashin <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: pinctrl-zynqmp: Use pin numbers stored in pin descriptorSwati Agarwal1-1/+1
Use pin numbers stored in the pin descriptors instead of index value while creating the pin groups. Pin Id's are not same as Index values for Xilinx Versal platform, so use the pin values from descriptor which works for both ZynqMP and Versal platforms. Signed-off-by: Swati Agarwal <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/2413a1f99278d70313960f13daecda9ef54172d8.1716807432.git.michal.simek@amd.com Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: ralink: mt76x8: fix pinmux functionWeihao Li1-61/+27
The current version of the pinctrl driver has some issues: 1. Duplicated "gpio" pmx function The common code will add a "gpio" pmx functon to every pin group, so it's not necessary to define a separate "gpio" pmx function in pin groups. 2. Duplicated pmx function name There are some same function name in different pin groups, which will cause some problems. For example, when we want to use PAD_GPIO0 as refclk output function, the common clk framework code will search the entire pin function lists, then return the first one matched, in this case the matched function list only include the PAD_CO_CLKO pin group because there are three "refclk" pin function, which is added by refclk_grp, spi_cs1_grp and gpio_grp. To solve this problem, a simple way is just add a pingrp refix to function name like mt7620 pinctrl driver does. 3. Useless "-" or "rsvd" functon It's really unnecessary to add a reserved pin mux function to the function lists, because we never use it. Signed-off-by: Weihao Li <[email protected]> Link: https://lore.kernel.org/r/20240527022036.31985-1-user@blabla Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: pinctrl-tps6594: make tps65224_muxval_remap and ↵Nirmala Devi Mal Nadar1-2/+2
tps6594_muxval_remap as static to fix sparse warning pinctrl: tps6594: Fix sparse warning. warning: symbol 'tps65224_muxval_remap' was not declared. Should it be static? warning: symbol 'tps6594_muxval_remap' was not declared. Should it be static? Signed-off-by: Nirmala Devi Mal Nadar <[email protected]> Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Link: https://lore.kernel.org/r/0109018f85002ae1-6fb831b2-74c2-4559-98f1-a3ef25e72558-000000@ap-south-1.amazonses.com Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: qcom: spmi: Add PMC8380Konrad Dybcio1-0/+1
PMC8380 is a new chip, featuring 10 GPIOs. Describe it. Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17dt-bindings: pinctrl: qcom,pmic-gpio: Document PMC8380Konrad Dybcio1-0/+2
PMC8380 is a new PMIC used with X1 SoCs. Document it Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: core: reset gpio_device in loop in pinctrl_pins_show()Léo DUBOIN1-0/+1
We were not resetting the pointer to the associated gpio_device once we are done displaying a pin's information. This meant that once we reached the end of a gpio-range, if there were pins right after it that did not belong to any known range, they would be associated with the previous range's gpio device. This resulted in those pins appearing as <4294966783:old_gdev> instead of the expected <0:?> (due to gpio_num being -1). Signed-off-by: Léo DUBOIN <[email protected]> Link: https://lore.kernel.org/r/c40d0634abefa19e689ffd450e0f48a8d63c4fc4.1714049455.git.lduboin@freebox.fr Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: core: take into account the pins array in pinctrl_pins_show()Léo DUBOIN1-4/+13
We previously only looked at the 'pin_base' of the pinctrl_gpio_ranges struct for determining if a pin matched a GPIO number. This value is present only if the 'pins' array is not NULL, and is 0 otherwise. This means that GPIO ranges declared using gpiochip_add_pingroup_range(), thus making use of pins, were always matched by the pins in the range [0-npins] even if they contained pins in a completely separate range. Signed-off-by: Léo DUBOIN <[email protected]> Link: https://lore.kernel.org/r/6df39bd47942156be5713f8f4e317d2ad3e0ddeb.1714049455.git.lduboin@freebox.fr Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: nuvoton: Add ma35d1 pinctrl and GPIO driverJacky Huang5-0/+3059
Add common pinctrl and GPIO driver for Nuvoton MA35 series SoC, and add support for ma35d1 pinctrl. Signed-off-by: Jacky Huang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17dt-bindings: pinctrl: Document nuvoton ma35d1 pin controlJacky Huang1-0/+178
Add documentation to describe nuvoton ma35d1 pin control and GPIO. Signed-off-by: Jacky Huang <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17dt-bindings: reset: Add syscon to nuvoton ma35d1 system-management nodeJacky Huang1-1/+2
Add a compatible 'syscon' to the system management node since the system control registers are mapped by this driver. The other driver must access the system control registers through 'regmap' using a phandle that references this node. Signed-off-by: Jacky Huang <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Acked-by: Philipp Zabel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: st: Use scope based of_node_put() cleanupsPeng Fan1-26/+11
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Patrice Chotard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: stm32: Use scope based of_node_put() cleanupsPeng Fan1-3/+1
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Patrice Chotard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17pinctrl: imx: Add pinctrl driver support for i.MX91Peng Fan3-0/+279
Add NXP i.MX91 pinctrl driver Signed-off-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-17dt-bindings: pinctrl: imx: Support i.MX91 IOMUXCPeng Fan1-3/+5
i.MX91 and i.MX93 share similar design. They could share same dt-binding doc, so rename fsl,imx93-pinctrl.yaml to fsl,imx9-pinctrl.yaml and add i.MX91 compatible string Signed-off-by: Peng Fan <[email protected]> Acked-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-06-11pinctrl: renesas: rzg2l: Add support for RZ/V2H SoCLad Prabhakar1-3/+371
Add pinctrl driver support for RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-11dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoCLad Prabhakar1-4/+33
Add documentation for the pin controller found on the Renesas RZ/V2H(P) (R9A09G057) SoC. The RZ/V2H PFC varies slightly compared to the RZ/G2L family: - Additional bits need to be set during pinmuxing, - The GPIO pin count is different. Hence, a SoC-specific compatible string, 'renesas,r9a09g057-pinctrl', is added for the RZ/V2H(P) SoC. Also, add the 'renesas,output-impedance' property. The drive strength settings on RZ/V2H(P) depend on the different power rails coming out from the PMIC (connected via I2C). These power rails (required for drive strength) can be 1.2V, 1.8V, or 3.3V. Pins are grouped into 4 groups: Group 1: Impedance - 150/75/38/25 ohms (at 3.3V) - 130/65/33/22 ohms (at 1.8V) Group 2: Impedance - 50/40/33/25 ohms (at 1.8V) Group 3: Impedance - 150/75/37.5/25 ohms (at 3.3V) - 130/65/33/22 ohms (at 1.8V) Group 4: Impedance - 110/55/30/20 ohms (at 1.8V) - 150/75/38/25 ohms (at 1.2V) The 'renesas,output-impedance' property, as documented, can be [0, 1, 2, 3], these correspond to register bit values that can be set in the PFC_IOLH_mn register, which adjusts the drive strength value and is pin-dependent. As power rail information may not be available very early in the boot process, the 'renesas,output-impedance' property is added instead of reusing the 'output-impedance-ohms' property. Also, allow bias-disable, bias-pull-down and bias-pull-up properties as these can be used to configure the pins. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-11pinctrl: renesas: rzg2l: Acquire lock in rzg2l_pinctrl_pm_setup_pfc()Lad Prabhakar1-0/+3
To keep consistency with rzg2l_pinctrl_set_pfc_mode(), acquire the lock in rzg2l_pinctrl_pm_setup_pfc() during PFC setup. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-11pinctrl: renesas: rzg2l: Add support for custom parametersLad Prabhakar1-0/+12
In preparation for passing custom params for RZ/V2H(P) SoC assign the custom params that are being passed via struct rzg2l_pinctrl_data. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-11pinctrl: renesas: rzg2l: Pass pincontrol device to ↵Lad Prabhakar1-1/+1
pinconf_generic_parse_dt_config() Pass the pincontrol device pointer to pinconf_generic_parse_dt_config() in preparation for passing custom params. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-11pinctrl: renesas: rzg2l: Add support for pull-up/downLad Prabhakar1-0/+72
Add support to configure bias-disable, bias-pull-up, and bias-pull-down properties of the pin. Two new function pointers, hw_to_bias_param() and bias_param_to_hw(), are introduced in the struct rzg2l_pinctrl_data to configure bias settings, as the values in the PUPD register differ when compared to the RZ/G2L family and the RZ/V2H(P) SoC. Value | RZ/G2L | RZ/V2H --------------------------------- 00b: | Bias Disabled | Pull up/down disabled 01b: | Pull-up | Pull up/down disabled 10b: | Pull-down | Pull-down 11b: | Prohibited | Pull-up Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-11pinctrl: renesas: rzg2l: Add support to configure slew-rateLad Prabhakar1-0/+18
Add support to configure slew-rate property of the pin. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-11pinctrl: renesas: rzg2l: Add function pointers for OEN register accessLad Prabhakar1-2/+10
Introduce function pointers oen_read() and oen_write(), in the struct rzg2l_pinctrl_data to facilitate reading and writing to the PFC_OEN register. On the RZ/V2H(P) SoC, unlocking the PWPR.REGWE_B bit before writing to the PFC_OEN register is necessary, and the PFC_OEN register has more bits compared to the RZ/G2L family. To handle these differences between RZ/G2L and RZ/V2H(P) and to reuse the existing code for RZ/V2H(P), these function pointers are introduced. Additionally, populate these function pointers with appropriate data for existing SoCs. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-11pinctrl: renesas: rzg2l: Add function pointer for PMC register writeLad Prabhakar1-1/+10
Introduces pmc_writeb() function pointer, in the struct rzg2l_pinctrl_data to facilitate writing to the PMC register. On the RZ/V2H(P) SoC, unlocking the PWPR.REGWE_A bit before writing to PMC registers is required, whereas this is not the case for the existing RZ/G2L family. This addition enables the reuse of existing code for RZ/V2H(P). Additionally, populate this function pointer with appropriate data for existing SoCs. Note that this functionality is only handled in rzg2l_gpio_request(), as PMC unlock/lock during PFC setup will be taken care of in the pwpr_pfc_lock_unlock() function pointer. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-11pinctrl: renesas: rzg2l: Add function pointer for PFC register lockingLad Prabhakar1-17/+27
On the RZ/G2L SoC, the PFCWE bit controls writing to PFC registers. However, on the RZ/V2H(P) SoC, the PFCWE (REGWE_A on RZ/V2H) bit controls writing to both PFC and PMC registers. Additionally, BIT(7) B0WI is undocumented for the PWPR register on RZ/V2H(P) SoC. To accommodate these differences across SoC variants, introduce the pwpr_pfc_lock_unlock() function pointer. Note, in rzg2l_pinctrl_set_pfc_mode() the pwpr_pfc_lock_unlock(.., false) is now called before PMC read/write and pwpr_pfc_lock_unlock(.., true) is now called after PMC read/write this is to keep changes minimal for RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-11pinctrl: renesas: rzg2l: Validate power registers for SD and ETHLad Prabhakar1-4/+8
On RZ/V2H(P) SoC, the power registers for SD and ETH do not exist, resulting in invalid register offsets. Ensure that the register offsets are valid before any read/write operations are performed. If the power registers are not available, both SD and ETH will be set to '0'. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-11pinctrl: renesas: rzg2l: Enable variable configuration for allLad Prabhakar1-3/+1
Enable parsing of variable configuration for all architectures. This prepares for adding support for the RZ/V2H SoC, which utilizes the ARM64 architecture and features port pins with variable configuration. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-11pinctrl: renesas: rzg2l: Drop struct rzg2l_variable_pin_cfgLad Prabhakar1-133/+54
Drop the rzg2l_variable_pin_cfg struct and instead use the RZG2L_VARIABLE_PIN_CFG_PACK() macro for the variable pin configuration. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Tested-by: Claudiu Beznea <[email protected]> # on RZ/G3S Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
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