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2016-06-24arm64: dts: msm8996: add blsp2_uart1 pinctrlSrinivas Kandagatla2-0/+66
This patch adds 2pin and 4 pin uart pinctrl support for blsp2_uart1 Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2016-06-24arm64: dts: msm8996: add msmgpio labelSrinivas Kandagatla1-1/+1
This patch adds msmgpio label for pin and gpio controller so that it can referenced in dedicated pins file and other board level gpios. Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2016-06-23ARM64: DTS: meson-gxbb: switch ethernet to real clockKevin Hilman1-1/+2
With the clock driver upstream, switch to the real clock. Signed-off-by: Kevin Hilman <[email protected]>
2016-06-23arm64: dts: gxbb clock controllerMichael Turquette1-0/+6
Add the clock controller node for the AmLogic GXBB machine. Signed-off-by: Michael Turquette <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
2016-06-22arm64: dts: rockchip: Provide emmcclk to PHY for rk3399Douglas Anderson1-0/+4
Previous changes in this series allowed exposing the card clock from the rk3399 SDHCI device and allowed consuming the card clock in the rk3399 eMMC PHY. Hook things up in the main rk3399 dtsi file. Signed-off-by: Douglas Anderson <[email protected]> Tested-by: Heiko Stuebner <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2016-06-22arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399Douglas Anderson1-0/+1
On rk3399 we'd like to be able to properly set corecfg registers in the Arasan SDHCI component. Specify the syscon to enable that. Signed-off-by: Douglas Anderson <[email protected]> Tested-by: Heiko Stuebner <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2016-06-21arm64: dts: juno: add thermal zones for scpi sensorsJavi Merino3-0/+74
The juno dts have entries for the hwmon scpi, let's create thermal zones for the temperature sensors described in the Juno ARM Development Platform Implementation Details. Cc: Liviu Dudau <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> Acked-by: Punit Agrawal <[email protected]> Signed-off-by: Javi Merino <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2016-06-21arm64: dts: juno: add SCPI power domains for device power managementSudeep Holla1-0/+18
This patch adds power domain information to coresight devices using SCPI power domains. Cc: Lorenzo Pieralisi <[email protected]> Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2016-06-21arm64: dts: juno: add coresight supportSudeep Holla4-0/+369
Most of the debug-related components on Juno are located in the coreSight subsystem while others are located in the Cortex-Axx clusters, the SCP subsystem, and in the main system. Each core in the two processor clusters contain an Embedded Trace Macrocell(ETM) which generates real-time trace information that trace tools can use and an ATB trace output that is sent to a funnel before going to the CoreSight subsystem. The trace output signals combine with two trace expansions using another funnel and fed into the Embedded Trace FIFO(ETF0). The output trace data stream of the funnel is then replicated before it is sent to either the: - Trace Port Interface Unit(TPIU), that sends it out using the trace port. - ETR that can write the trace data to memory located in the application memory space Cc: Lorenzo Pieralisi <[email protected]> Acked-by: Liviu Dudau <[email protected]> Acked-by: Mathieu Poirier <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2016-06-21clk: renesas: r8a7795: Add THS/TSC clockKhiem Nguyen1-0/+1
Signed-off-by: Khiem Nguyen <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-06-21clk: renesas: r8a7795: Add DRIF clockRamesh Shanmugasundaram1-0/+8
This patch adds DRIF module clocks for r8a7795 SoC. Signed-off-by: Ramesh Shanmugasundaram <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-06-21clk: renesas: r8a7795: Correct lvds clock parentGeert Uytterhoeven1-1/+1
According to the latest information, the parent clock of the LVDS module clock is the S0D4 clock, not the S2D1 clock. Note that this change has no influence on actual operation, as the rcar-du LVDS encoder driver doesn't use the parent clock's rate. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]>
2016-06-21clk: renesas: r8a7795: Provide FDP1 clocksKieran Bingham1-0/+3
Reviewed-by: Laurent Pinchart <[email protected]> Signed-off-by: Kieran Bingham <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-06-21clk: renesas: Add R8A7792 supportSergei Shtylyov2-0/+2
Renesas R-Car V2H (R8A7792) clocks are handled by R-Car gen2 clock driver. Signed-off-by: Sergei Shtylyov <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-06-21clk: renesas: mstp: Document R8A7792 supportSergei Shtylyov1-0/+1
Renesas R8A7792 SoC also has the CPG MSTP clocks... Signed-off-by: Sergei Shtylyov <[email protected]> Acked-by: Simon Horman <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-06-21clk: renesas: rcar-gen2: Document R8A7792 supportSergei Shtylyov1-0/+1
Renesas R8A7792 SoC is a member of the R-Car gen2 family and so has CPG... Signed-off-by: Sergei Shtylyov <[email protected]> Acked-by: Simon Horman <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-06-21arm64: dts: ls2080a: Add cache nodes for cacheinfo supportLi Yang1-0/+24
Adds the cache nodes and next-level-cache property for the cacheinfo to work. Signed-off-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2016-06-21arm64: dts: ls1043a: Add cache nodes for cacheinfo supportLi Yang1-0/+8
Adds the cache nodes and next-level-cache property for the cacheinfo to work. Signed-off-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2016-06-20arm64: dts: apm: Remove unused qmlclk node on X-Gene 1Duc Dang1-10/+0
Node qmlclk has no consumer, so remove it. Signed-off-by: Duc Dang <[email protected]>
2016-06-20arm64: dts: apm: Fix timer interrupt polarity for X-Gene 2 SoCDuc Dang1-4/+4
Correct X-Gene 2 timer interrupt polarity as low-level triggered. Signed-off-by: Duc Dang <[email protected]>
2016-06-20arm64: dts: apm: Remove leading '0x' from unit addressesBjorn Helgaas1-16/+16
Unit addresses should not have a leading '0x'. Remove them. Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Duc Dang <[email protected]>
2016-06-20arm64: dts: apm: Use lowercase consistently for hex constantsBjorn Helgaas3-40/+40
The convention in these files is to use lowercase for "0x" prefixes and for the hex constants themselves, but a few changes didn't follow that convention, which makes the file annoying to read. Use lowercase consistently for the hex constants. No functional change intended. Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Duc Dang <[email protected]>
2016-06-19Merge tag 'arm-soc/for-4.8/devicetree-arm64' of ↵Olof Johansson3-0/+157
http://github.com/Broadcom/stblinux into next/dt64 This pull request contains Device Tree changes for Broadcom ARM64-based SoCS: - Anup adds nodes for the AHCI and SATA3 PHY peripherals to the Northstar2 SoCs - Dhanajay enables pinctrl for the Northstar2 SoCs - Jon Mason enables all of the UART peripherals found in the NS2 SVK and finally adds the CCI-400 and PMU nodes * tag 'arm-soc/for-4.8/devicetree-arm64' of http://github.com/Broadcom/stblinux: arm64: dts: NS2: Add CCI-400 PMU support arm64: dts: NS2: Add all of the UARTs arm64: dts: Enable GPIO for Broadcom NS2 SoC arm64: dts: enable pinctrl for Broadcom NS2 SoC arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2 dt-bindings: ata: add compatible string for iProc AHCI controller Signed-off-by: Olof Johansson <[email protected]>
2016-06-19Merge tag 'amlogic-dt64' of ↵Olof Johansson5-1/+192
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt64 Amlogic DT 64-bit changes for v4.8 - add pinctrl driver and pins for several devices - add reset driver * tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM64: dts: amlogic: Enable Reset Controller on GXBB-based platforms ARM64: dts: amlogic: gxbb: add ethernet ARM64: dts: amlogic: gxbb: pinctrl: add/update UART ARM64: dts: amlogic: add pins for EMMC, SD ARM64: dts: amlogic: Enable pin controller on GXBB-based platforms documentation: Add compatibles for Amlogic Meson GXBB pin controllers ARM64: dts: amlogic: Add hiu and periphs buses Signed-off-by: Olof Johansson <[email protected]>
2016-06-18arm64: dts: rockchip: fixes the gic400 2nd region size for rk3368Caesar Wang1-1/+1
The 2nd additional region is the GIC virtual cpu interface register base and size. As the gic400 of rk3368 says, the cpu interface register map as below : -0x0000 GICC_CTRL . . . -0x00fc GICC_IIDR -0x1000 GICC_IDR Obviously, the region size should be greater than 0x1000. So we should make sure to include the GICC_IDR since the kernel will access it in some cases. Fixes: b790c2cab5ca ("arm64: dts: add Rockchip rk3368 core dtsi and board dts for the r88 board") Signed-off-by: Caesar Wang <[email protected]> Reviewed-by: Shawn Lin <[email protected]> Cc: [email protected] [added Fixes and stable-cc] Signed-off-by: Heiko Stuebner <[email protected]>
2016-06-18arm64: dts: rockchip: add i2c nodes for rk3399David Wu1-0/+144
We've got 9 (count em!) i2c controllers on rk3399, some of which are in the PMU power domain and some of which are normal peripherals. Add them all to the main rk3399 dtsi file so future patches can turn them on in the board dts files. Note: by default we try to set the i2c clock rate to 200 MHz so that we can achieve good i2c functional clock rates. 200 MHz gives us the ability to make very close to 100 kHz / 400 kHz / 1 MHz rates. If boards want to tune clock rates further they can always override. Possibly boards could want to tune this if: - they wanted to save an infinitesimal amount of power and they knew their i2c bus was slow anyway. Since we gate the functional clock when the i2c bus is not active, power savings would only be while i2c transfers were happening and probably won't be very big anyway. - they wanted to eek out a bit more speed by carefully tuning the source clock to make divisions work out perfectly, accounting for the rise / fall time measured on an actual board. Note also that we still request 200 MHz for the PMU i2c busses even though we expect that we won't make that exactly (currently PPLL is 676 MHz which gives us 169 MHz). Signed-off-by: David Wu <[email protected]> Signed-off-by: Jianqun Xu <[email protected]> [dianders: wrote desc; put in assigned-clocks; reordered nodes] Signed-off-by: Douglas Anderson <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2016-06-17clk: tegra: Enable sor1 and sor1_src on Tegra210Thierry Reding2-1/+3
Make the sor1 and sor1_src clocks available on Tegra210. They will be used by the display driver to support HDMI and DP. Signed-off-by: Thierry Reding <[email protected]>
2016-06-17clk: tegra: Squash sor1 safe/brick/src into a single muxThierry Reding2-12/+12
The sor1 clock on Tegra210 is structured in the following way: +-------+ | pllp |---+ +-------+ | +--------------+ +-----------+ +----| | | sor_safe | +-------+ | | +-----------+ | plld |--------| | | +-------+ | | +-----------+ | sor1_src |-------| | +-------+ | | +-----------+ | plld2 |--------| | | +-------+ | | | +----| | | +-------+ | +--------------+ | | clkm |---+ +-----------+ +-------+ +--------------+ | | | sor1_brick |-------| sor1 | +--------------+ | | +-----------+ This is impractical to represent in a clock tree, though, because there is no name for the mux that has sor_safe and sor1_src as parents. It is also much more cumbersome to deal with the additional mux because users of these clocks (the display driver) would have to juggle with an extra mux for no real reason. To simply things, the above is squashed into two muxes instead, so that it looks like this: +-------+ | pllp |---+ +-------+ | +--------------+ +-----------+ +----| | | sor_safe | +-------+ | | +-----------+ | plld |--------| | | +-------+ | | +-----------+ | sor1_src |-------| sor1 | +-------+ | | +-----------+ | plld2 |--------| | | | +-------+ | | | | +----| | | | +-------+ | +--------------+ | | | clkm |---+ | | +-------+ +--------------+ | | | sor1_brick |-----------+---+ +--------------+ This still very accurately represents the hardware. Note that sor1 has sor1_brick as input twice, that's because bit 1 in the mux selects the sor1_brick irrespective of bit 0. Signed-off-by: Thierry Reding <[email protected]>
2016-06-17clk: tegra: Disable spread spectrum on pll_d2Thierry Reding1-2/+3
Enabling spread spectrum on pll_d2 can lead to issues with display modes. HDMI monitors, for example, would report "Signal Error" and some modes driven over DisplayPort would generate fuzzy horizontal bands. Signed-off-by: Thierry Reding <[email protected]>
2016-06-16arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodesLiu Gang1-0/+3
The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance. Signed-off-by: Liu Gang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2016-06-16bindings: PCI: layerscape: Add 'dma-coherent' propertyLiu Gang1-0/+4
Add 'dma-coherent' description for PCI nodes. The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance. Signed-off-by: Liu Gang <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2016-06-15ARM64: dts: meson-gxbb: Add Hardware Random Generator nodeNeil Armstrong1-0/+5
Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
2016-06-15dt-bindings: hwrng: Add Amlogic Meson Hardware Random Generator bindingsNeil Armstrong1-0/+14
Acked-by: Rob Herring <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
2016-06-14arm64: dts: uniphier: add /memreserve/ for spin-table release addressMasahiro Yamada1-0/+2
As Documentation/arm64/booting.txt says, the cpu-release-addr location should be reserved. Signed-off-by: Masahiro Yamada <[email protected]> Acked-by: Mark Rutland <[email protected]> Signed-off-by: Olof Johansson <[email protected]>
2016-06-14arm64: dts: uniphier: change cpu-release-addressMasahiro Yamada1-4/+4
At first, 256 byte of the head of DRAM space was reserved for some reasons. However, as the progress of development, it turned out unnecessary, and it was never used in the end. Move the CPU release address to leave no space. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Olof Johansson <[email protected]>
2016-06-14arm64: dts: uniphier: add SoC-Glue node to UniPhier 64bit SoCsMasahiro Yamada1-3/+7
This node consists of various system-level configuration registers. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Olof Johansson <[email protected]>
2016-06-13Merge tag 'renesas-arm64-dt-for-v4.8' of ↵Olof Johansson2-41/+71
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64 Renesas ARM64 Based SoC DT Updates for v4.8 * Fix W=1 dtc warnings and other cleanups * Enable watchdog timer * Enable DMA for I2C * Increase the size of GIC-400 mapped registers: be nicer to hypervisors * Support RTS/CTS hardware flow control * tag 'renesas-arm64-dt-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: arm64: dts: r8a7795: Drop 0x from unit address of gic arm64: dts: salvator-x: Fix W=1 dtc warnings arm64: dts: r8a7795: Fix W=1 dtc warnings arm64: dts: r8a7795: Use SYSC "always-on" PM Domain for RWDT node arm64: dts: salvator-x: Enable watchdog timer arm64: dts: r8a7795: Add RWDT node arm64: dts: r8a7795: enable DMA for I2C arm64: dts: r8a7795: Increase the size of GIC-400 mapped registers arm64: dts: salvator-x: SCIF1 supports RTS/CTS hardware flow control Signed-off-by: Olof Johansson <[email protected]>
2016-06-12ARM: dts: msm8916: Update reserved-memoryBjorn Andersson1-3/+38
Update reserved-memory in accordance with memory the detailed memory map for 8916, so that we will be able to reference the firmware memory regions. Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2016-06-12arm64: dts: msm8916: Add SCM firmware nodeAndy Gross1-0/+8
This adds the devicetree node for the SCM firmware. Acked-by: Bjorn Andersson <[email protected]> Signed-off-by: Andy Gross <[email protected]> Reviewed-by: Stephen Boyd <[email protected]>
2016-06-12arm64: dts: qcom: Add msm8916 PMU nodeStephen Boyd1-0/+5
Add the PMU so we can get proper perf event support on this SoC. Signed-off-by: Stephen Boyd <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2016-06-12ARM64: dts: Add PSCI cpuidle support for MSM8916Lina Iyer1-0/+24
Add device bindings for CPUs to suspend using PSCI as the enable-method. Cc: <[email protected]> Signed-off-by: Lina Iyer <[email protected]> Tested-by: Andy Gross <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2016-06-12arm64: dts: qcom: apq8016-sbc: enable bam dma node.Srinivas Kandagatla1-0/+4
This patch enables bam dma node, dma is used for both tx and rx on spi and on high speed serial. Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2016-06-12arm64: dts: apq8016-sbc: Add DT node for the uSD SDHC interfaceGeorgi Djakov1-0/+12
Add the necessary properties to enable the SD-card on db410c boards. Signed-off-by: Georgi Djakov <[email protected]> Tested-by: Kevin Hilman <[email protected]> Signed-off-by: Andy Gross <[email protected]>
2016-06-11arm64: dts: ls1043a: Add dis_rxdet_inp3_quirk property to USB3 nodeRajesh Bhagat1-0/+3
Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property is used to disable rx detection in P3 PHY mode. Signed-off-by: Rajesh Bhagat <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2016-06-11arm64: dts: ls2080a: Add dis_rxdet_inp3_quirk property to USB3 nodeRajesh Bhagat1-0/+2
Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property is used to disable rx detection in P3 PHY mode. Signed-off-by: Rajesh Bhagat <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2016-06-10clk: tegra: Fixup post dividers on Tegra210Thierry Reding1-47/+47
Commit 86c679a52294 ("clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate") changed the PLL divider computation logic to consistently use P-divider values from tables as real dividers rather than the hardware values. Unfortunately for some reason many of the Tegra210 clocks didn't have their tables updated (most likely an over- sight by me when applying the patches). This commit fixes them all up. Cc: Jon Hunter <[email protected]> Cc: Rhyland Klein <[email protected]> Acked-by: Rhyland Klein <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2016-06-09arm64: dts: fsl: Update address-cells and reg properties of cpu nodesAlison Wang2-14/+14
MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1, since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update the #address-cells and reg properties accordingly. Signed-off-by: Alison Wang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2016-06-07ARM: bcm2837: dt: Add the ethernet to the device treesGerd Hoffmann1-0/+1
Signed-off-by: Gerd Hoffmann <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
2016-06-07Merge tag 'bcm2835-dt-ethernet' into HEADEric Anholt7-0/+44
This merge brings over the DT ethernet nodes from 32-bit (used so that we can get the MAC address for it) so that we can expose it on arm64 as well.
2016-06-07ARM: bcm2835: Add devicetree for the Raspberry Pi 3.Eric Anholt3-0/+106
While this devicetree also works for booting in 32-bit mode, it's placed in arm64 since it's a 64-bit CPU (as suggested by Arnd). Signed-off-by: Eric Anholt <[email protected]> Acked-by: Stephen Warren <[email protected]> (v1) Signed-off-by: Gerd Hoffmann <[email protected]>
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