aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2023-07-12phy: zynqmp: Allow variation in refclk rateSean Anderson1-1/+4
Due to limited available frequency ratios, the reference clock rate may not be exactly the same as the required rate. Allow a small (100 ppm) deviation. Signed-off-by: Sean Anderson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom-qmp-ufs: populate offsets configurationDmitry Baryshkov1-0/+10
Populate offsets configuration for the rest of UFS PHYs to make it possible to switch them to the new (single-node) bindings style. Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12dt-bindings: phy: migrate QMP UFS PHY bindings to qcom,sc8280xp-qmp-ufs-phy.yamlDmitry Baryshkov2-231/+45
Migrate legacy bindings (described in qcom,msm8996-qmp-ufs-phy.yaml) to qcom,sc8280xp-qmp-ufs-phy.yaml. This removes a need to declare the child PHY node or split resource regions. Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: starfive: Add JH7110 PCIE 2.0 PHY driverMinda Chen4-1/+218
Add Starfive JH7110 SoC PCIe 2.0 PHY driver support. PCIe 2.0 PHY default connect to PCIe controller. PCIe PHY can connect to USB 3.0 controller. Signed-off-by: Minda Chen <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: starfive: Add JH7110 USB 2.0 PHY driverMinda Chen6-0/+176
Add Starfive JH7110 SoC USB 2.0 PHY driver support. USB 2.0 PHY default connect to Cadence USB controller. Signed-off-by: Minda Chen <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12dt-bindings: phy: Add StarFive JH7110 PCIe PHYMinda Chen1-0/+58
Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding. PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY. Signed-off-by: Minda Chen <[email protected]> Reviewed-by: Hal Feng <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12dt-bindings: phy: Add StarFive JH7110 USB PHYMinda Chen1-0/+50
Add StarFive JH7110 SoC USB 2.0 PHY dt-binding. Signed-off-by: Minda Chen <[email protected]> Reviewed-by: Hal Feng <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: cadence: Sierra: Add single link SGMII register configurationMarcin Wierzbicki1-0/+98
Add single link SGMII register configuration for no SSC for cdns,sierra-phy-t0 compatibility string. The configuration is based on Sierra Programmer's Guide and validated in Cisco CrayAR SoC. Co-developed-by: Bartosz Wawrzyniak <[email protected]> Signed-off-by: Bartosz Wawrzyniak <[email protected]> Signed-off-by: Marcin Wierzbicki <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: add more supported pre-pll ratesAlex Bee1-25/+173
This adds a bunch of new pixel clock- and tmds rates to the pre-pll table which are required to get more VESA and some DMT rates working. It has been completely re-calculated to match the min- and max-vco of (750 MHz - 3.2 GHz) requirements. If more than one configuration would have been possible the lowest fbdiv and refdiv (and therefore lowest vco rate) has been preferred. It's important to note, that RK3228 version of the phy does not support fractional dividers. To support the most possible rates for this version also in both 8-bit and 10-bit variant, some rates are not exact. The maximum deviation of the pixel clock is 0.26, which perfectly fits into VESA DMT recommendation of 0.5%. I tested all possible rates on several screens from different manufacturers with both RK3228 and RK3328. Both pre- and post-PLL locking are slighlty faster now. Signed-off-by: Alex Bee <[email protected]> Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: force set_rate on power_onHuicong Xu1-0/+13
Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and not in pixel clock rate. When the hdmiphy clock is configured with the same pixel clock rate using clk_set_rate() the clock framework do not signal the hdmi phy driver to set_rate when switching between 8-bit and Deep Color. This result in pre/post pll not being re-configured when switching between regular 8-bit and Deep Color video formats. Fix this by calling set_rate in power_on to force pre pll re-configuration. Signed-off-by: Huicong Xu <[email protected]> Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg writeJonas Karlman1-2/+4
inno_write is used to configure 0xaa reg, that also hold the POST_PLL_POWER_DOWN bit. When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not taken into consideration. Fix this by keeping the power down bit until configuration is complete. Also reorder the reg write order for consistency. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: remove unused no_c from rk3328 recalc_rateJonas Karlman1-4/+1
no_c is not used in any calculation, lets remove it. Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: round fractal pixclock in rk3328 recalc_rateZheng Yang1-3/+5
inno_hdmi_phy_rk3328_clk_recalc_rate() is returning a rate not found in the pre pll config table when the fractal divider is used. This can prevent proper power_on because a tmdsclock for the new rate is not found in the pre pll config table. Fix this by saving and returning a rounded pixel rate that exist in the pre pll config table. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Zheng Yang <[email protected]> Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: use correct vco_div_5 macro on rk3328Jonas Karlman1-2/+2
inno_hdmi_phy_rk3328_clk_set_rate() is using the RK3228 macro when configuring vco_div_5 on RK3328. Fix this by using correct vco_div_5 macro for RK3328. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom: qmp-combo: extract common function to setup clocksDmitry Baryshkov1-37/+26
Extact qmp_combo_configure_dp_clocks(), a common function to setup PHY clocks depending on the selected link rate. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom: qmp-combo: drop qmp_v6_dp_aux_init()Dmitry Baryshkov1-32/+12
The only difference between qmp_v6_dp_aux_init() and qmp_v4_dp_aux_init() is the address of COM_BIAS_EN_CLKBUFLR_EN register. Move it to register layout and drop the duplicate function. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom: qmp-combo: drop similar functionsDmitry Baryshkov1-121/+2
The functions qmp_v5_configure_dp_phy() and qmp_v6_configure_dp_phy() are now copies of qmp_v4_configure_dp_phy(). Drop them and use the v4 function in all the cases. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom: qmp-combo: reuse register layouts for some more registersDmitry Baryshkov2-12/+24
Use register layout for TX_HIGHZ_DRVR_EN and TX_TRANSCEIVER_BIAS_EN registers. This will allow us to unify qmp_v[456]_configure_dp_phy() functions in the next commit. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom: qmp-combo: reuse register layouts for even more registersDmitry Baryshkov3-33/+76
Instead of passing additional registers to qmp_combo_configure_dp_swing(), reuse qphy_reg_layout and add those registers to register layout maps. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom: qmp-combo: reuse register layouts for more registersDmitry Baryshkov1-36/+64
Instead of passing additional registers to qmp_v456_configure_dp_phy(), reuse qphy_reg_layout and add those registers to register layout maps. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom: qmp-combo: correct bias0_en programmingDmitry Baryshkov1-2/+2
It seems the commit a2e927b0e50d ("phy: qcom-qmp-combo: Add sc8280xp USB/DP combo phys") contained a typo for selecting bias0_en values. First, bias0_en and bias1_en are expected to be symmetrical, and then the vendor driver also uses `flipped : 0x3E : 0x15` statement for bias0_en. Correct bias0_en programming to follow this. Fixes: 49742e9edab3 ("phy: qcom-qmp-combo: Add support for SM8550") Fixes: a2e927b0e50d ("phy: qcom-qmp-combo: Add sc8280xp USB/DP combo phys") Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: xilinx: phy-zynqmp: dynamic clock support for power-savePiyush Mehta1-46/+15
Enabling clock for all the lanes consumes power even PHY is active or inactive. To resolve this, enable/disable clocks in phy_init/phy_exit. By default clock is disabled for all the lanes. Whenever phy_init called from USB, SATA, or display driver, etc. It enabled the required clock for requested lane. On phy_exit cycle, it disabled clock for the active PHYs. During the suspend/resume cycle, each USB/ SATA/ display driver called phy_exit/phy_init individually. It disabled clock on exit, and enabled on initialization for the active PHYs. Signed-off-by: Piyush Mehta <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: xilinx: add runtime PM supportPiyush Mehta1-7/+28
Added Runtime power management support to the xilinx phy driver and using DEFINE_RUNTIME_DEV_PM_OPS new macros allows the compiler to remove the unused dev_pm_ops structure and related functions if !CONFIG_PM without the need to mark the functions __maybe_unused. Signed-off-by: Piyush Mehta <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: mediatek: mipi-dsi: Compress of_device_id match entriesAngeloGioacchino Del Regno1-7/+4
All of the entries do fit in a maximum of 82 columns, which is acceptable. While at it, also remove the useless comma on the last entry and add the usual sentinel comment. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: mediatek: mipi-dsi: Use devm variant for of_clk_add_hw_provider()AngeloGioacchino Del Regno1-7/+1
Switch to devm_of_clk_add_hw_provider() in the probe function: this also allows to entirely remove the .remove_new() callback, as its only task was to unregister the clock provider. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: mediatek: mipi-dsi: Convert to register clk_hwAngeloGioacchino Del Regno2-8/+6
Instead of registering a struct clk, directly register clk_hw: this allows us to cleanup a pointer to struct clk from struct mtk_mipi_tx. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom-qmp-usb: split off the legacy USB+dp_com supportDmitry Baryshkov4-556/+1418
When adding support for some of the platforms (sc7180, sc8180x, sdm845, sm8[1234]50), we added USB PHYs for the combo USB+DP QMP PHYs. Now all such usecases were migrated to use USB+DP Combo driver. To simplify the qcom-qmp-usb PHY driver split the legacy USB+dp_com support into a separate driver. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12dt-bindings: phy: qcom,msm8996-qmp-usb3-phy: drop legacy bindingsDmitry Baryshkov1-80/+0
The qcom,msm8996-qmp-usb3-phy.yaml defines bindings for several PHYs which predate USB -> USB+DP migration. Now as sm8150 has been migrated, drop the legacy bindings completely. No device trees use them anymore. Newer USB+DP bindings should use combo bindings from the beginning. Signed-off-by: Dmitry Baryshkov <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom-qmp-combo: add support for the USB+DP PHY on SM8150 platformDmitry Baryshkov1-0/+4
SM8150 and SC8180X are close relatives. Reuse sc8180x data to support USB+DP combo PHY on SM8150 platform. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12dt-bindings: phy: qcom,sc7180-qmp-usb3-dp-phy: add sm8150 USB+DP PHYDmitry Baryshkov1-0/+2
Add bindings for sm8150 USB+DP PHY. These bindings follow the older style as this is a quick conversion to simplify further driver cleanup. Acked-by: Rob Herring <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: phy-rockchip-inno-usb2: improve error messageSebastian Reichel1-2/+1
Printing the OF node is not useful, since we get the same information from the device context. Instead print the reg address, that could not be found. Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: phy-rockchip-inno-usb2: simplify getting match dataSebastian Reichel1-8/+4
Simplify the code by directly getting the match data via device_get_match_data() instead of open coding its functionality. Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: phy-rockchip-inno-usb2: simplify phy clock handlingSebastian Reichel1-13/+6
Simplify phyclk handling by using devm_clk_get_optional_enabled to acquire and enable the optional clock. This also fixes a resource leak in driver remove path and adds proper error handling. Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: phy-rockchip-inno-usb2: add rk3588 phy tuning supportSebastian Reichel1-0/+63
On RK3588 some registers need to be tweaked to support waking up from suspend when a USB device is plugged into a port from a suspended PHY. Without this change USB devices only work when they are plugged at boot time. Apart from that it optimizes settings to avoid devices toggling between fullspeed and highspeed mode. Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: phy-rockchip-inno-usb2: add reset supportSebastian Reichel1-0/+38
Add reset handling support, which is needed for proper operation with RK3588. Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: phy-rockchip-inno-usb2: add rk3588 supportSebastian Reichel1-15/+211
Add basic support for the USB2 PHY found in the Rockchip RK3588. Co-developed-by: William Wu <[email protected]> Signed-off-by: William Wu <[email protected]> Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12dt-bindings: phy: rockchip,inno-usb2phy: add rk3588Sebastian Reichel1-3/+18
Add compatible for the USB2 phy in the Rockchip RK3588 SoC. Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: cadence-torrent: Use key:value pair table for all settingsRoger Quadros1-1176/+485
Instead of a 3D matrix use a key:value pair table for link_cmn_vals, xcvr_diag_vals, pcs_cmn_vals, phy_pma_cmn_vals, cmn_vals, tx_ln_vals and rx_ln_vals. This makes it scaleable for multiple reference clocks. Wherever both CDNS and TI use the same settings, reuse the same data. Introduce CLK_ANY and ANY_SSC enums which are used if the setting is independent of clock rate or SSC type. Signed-off-by: Roger Quadros <[email protected]> Signed-off-by: Swapnil Jakhade <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: cadence-torrent: Add single link USXGMII configuration for 156.25MHz refclkSwapnil Jakhade1-5/+228
Add register sequences for single link USXGMII configuration supporting 156.25MHz reference clock frequency. Signed-off-by: Swapnil Jakhade <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: renesas: r8a779f0-ether-serdes: Convert to devm_platform_ioremap_resource()Yangtao Li1-8/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: rockchip: phy-rockchip-typec: Use devm_platform_get_and_ioremap_resource()Yangtao Li1-2/+1
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: marvell: phy-mvebu-cp110-comphy: Use ↵Yangtao Li1-2/+1
devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-09Linux 6.5-rc1Linus Torvalds1-2/+2
2023-07-09MAINTAINERS 2: Electric BoogalooLinus Torvalds1-46/+46
We just sorted the entries and fields last release, so just out of a perverse sense of curiosity, I decided to see if we can keep things ordered for even just one release. The answer is "No. No we cannot". I suggest that all kernel developers will need weekly training sessions, involving a lot of Big Bird and Sesame Street. And at the yearly maintainer summit, we will all sing the alphabet song together. I doubt I will keep doing this. At some point "perverse sense of curiosity" turns into just a cold dark place filled with sadness and despair. Repeats: 80e62bc8487b ("MAINTAINERS: re-sort all entries and fields") Signed-off-by: Linus Torvalds <[email protected]>
2023-07-09Merge tag 'dma-mapping-6.5-2023-07-09' of ↵Linus Torvalds1-11/+35
git://git.infradead.org/users/hch/dma-mapping Pull dma-mapping fixes from Christoph Hellwig: - swiotlb area sizing fixes (Petr Tesarik) * tag 'dma-mapping-6.5-2023-07-09' of git://git.infradead.org/users/hch/dma-mapping: swiotlb: reduce the number of areas to match actual memory pool size swiotlb: always set the number of areas before allocating the pool
2023-07-09Merge tag 'irq_urgent_for_v6.5_rc1' of ↵Linus Torvalds1-3/+1
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq update from Borislav Petkov: - Optimize IRQ domain's name assignment * tag 'irq_urgent_for_v6.5_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqdomain: Use return value of strreplace()
2023-07-09Merge tag 'x86_urgent_for_v6.5_rc1' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fpu fix from Borislav Petkov: - Do FPU AP initialization on Xen PV too which got missed by the recent boot reordering work * tag 'x86_urgent_for_v6.5_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/xen: Fix secondary processors' FPU initialization
2023-07-09Merge tag 'x86-core-2023-07-09' of ↵Linus Torvalds1-0/+8
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fix from Thomas Gleixner: "A single fix for the mechanism to park CPUs with an INIT IPI. On shutdown or kexec, the kernel tries to park the non-boot CPUs with an INIT IPI. But the same code path is also used by the crash utility. If the CPU which panics is not the boot CPU then it sends an INIT IPI to the boot CPU which resets the machine. Prevent this by validating that the CPU which runs the stop mechanism is the boot CPU. If not, leave the other CPUs in HLT" * tag 'x86-core-2023-07-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/smp: Don't send INIT to boot CPU
2023-07-09Merge tag 'mips_6.5_1' of ↵Linus Torvalds10-53/+46
git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS fixes from Thomas Bogendoerfer: - fixes for KVM - fix for loongson build and cpu probing - DT fixes * tag 'mips_6.5_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: kvm: Fix build error with KVM_MIPS_DEBUG_COP0_COUNTERS enabled MIPS: dts: add missing space before { MIPS: Loongson: Fix build error when make modules_install MIPS: KVM: Fix NULL pointer dereference MIPS: Loongson: Fix cpu_probe_loongson() again
2023-07-09Merge tag 'xfs-6.5-merge-6' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linuxLinus Torvalds1-1/+1
Pull xfs fix from Darrick Wong: "Nothing exciting here, just getting rid of a gcc warning that I got tired of seeing when I turn on gcov" * tag 'xfs-6.5-merge-6' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux: xfs: fix uninit warning in xfs_growfs_data
Powered by cgit, Gruvboxed by Blaster4385.