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2018-09-27drm/scheduler: remove timeout work_struct from drm_sched_job (v3)Nayan Deshmukh4-20/+21
having a delayed work item per job is redundant as we only need one per scheduler to track the time out the currently executing job. v2: the first element of the ring mirror list is the currently executing job so we don't need a additional variable for it v3: squash in fixes for v3d and etnaviv Signed-off-by: Nayan Deshmukh <[email protected]> Suggested-by: Christian König <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-27Merge branch 'clockevents/4.19-fixes' of ↵Thomas Gleixner1-6/+14
https://git.linaro.org/people/daniel.lezcano/linux into timers/urgent Pull another fix from Daniel Lezcano, which felt through the cracks: - Fix a potential memory leak reported by smatch in the atmel timer driver
2018-09-27drm/amd/powerplay: Change id parameter type in ↵Nathan Chancellor2-2/+3
pp_atomfwctrl_get_clk_information_by_clkid Clang generates warnings when one enumerated type is implicitly converted to another. drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/ppatomfwctrl.c:532:57: warning: implicit conversion from enumeration type 'enum atom_smu11_syspll0_clock_id' to different enumeration type 'BIOS_CLKID' (aka 'enum atom_smu9_syspll0_clock_id') [-Wenum-conversion] if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_SOCCLK_ID, &frequency)) In this case, that is expected behavior. To make that clear to Clang without explicitly casting these values, change id's type to uint8_t in pp_atomfwctrl_get_clk_information_by_clkid so no conversion happens. Reported-by: Nick Desaulniers <[email protected]> Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-27drm/amdkfd: Remove the requirement for atomic Ops on vg20Shaoyun Liu1-1/+1
Firmware have the workaround to replace the atomic Ops with read-modify-write on CP side. User should not expect atomic Ops on system memory works normally if system didn't not support it. Signed-off-by: Shaoyun Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-By: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-27xen/blkfront: When purging persistent grants, keep them in the bufferBoris Ostrovsky1-3/+1
Commit a46b53672b2c ("xen/blkfront: cleanup stale persistent grants") added support for purging persistent grants when they are not in use. As part of the purge, the grants were removed from the grant buffer, This eventually causes the buffer to become empty, with BUG_ON triggered in get_free_grant(). This can be observed even on an idle system, within 20-30 minutes. We should keep the grants in the buffer when purging, and only free the grant ref. Fixes: a46b53672b2c ("xen/blkfront: cleanup stale persistent grants") Reviewed-by: Juergen Gross <[email protected]> Signed-off-by: Boris Ostrovsky <[email protected]> Signed-off-by: Jens Axboe <[email protected]>
2018-09-27drm/vmwgfx: Look up objects without taking a referenceThomas Hellstrom2-0/+50
Typically when we look up objects under the rcu lock, we take a reference to make sure the returned object pointer is valid. Now provide a function to look up an object and instead of taking a reference to it, keep the rcu lock held when returning the object pointer. This means that the object pointer is valid as long as the rcu lock is held, but the object may be doomed (its refcount may be zero). Any persistent usage of the object pointer outside of the rcu lock requires a reference to be taken using kref_get_unless_zero(). Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]>
2018-09-27drm/vmwgfx: Make the object handles idr-generatedThomas Hellstrom10-62/+65
Instead of generating user-space object handles based on a, possibly processed, hash of the kernel address of the object, use idr to generate and lookup those handles. This might improve somewhat on security since we loose all connections to the object's kernel address. Also idr is designed to do just this. As a todo-item, since user-space handles are now generated in sequence, we can probably use a much simpler hash function to hash them. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]> Reviewed-by: Deepak Rawat <[email protected]>
2018-09-27drm/vmwgfx: Remove the user resource destructor checkThomas Hellstrom1-3/+0
We were checking that the resource destructor matched that of the intended object type, to make sure the looked up resource was of the right type. But we already have an object type check in place which makes sure the resource is of the right type. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]> Reviewed-by: Deepak Rawat <[email protected]>
2018-09-27drm/vmwgfx: Remove the resource avail fieldThomas Hellstrom10-73/+68
This field was previously used to prevent a lookup of a resource before its constructor had run to its end. This was mainly intended for an interface that is now removed that allowed looking up a resource by its device id. Currently all affected resources are added to the lookup mechanism (its TTM prime object is initialized) late in the constructor where it's OK to look up the resource. This means we can change the device resource_lock to an ordinary spinlock instead of an rwlock and remove a locking sequence during lookup. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]> Reviewed-by: Deepak Rawat <[email protected]>
2018-09-27drm/vmwgfx: Replace unconditional mutex unlocked warnings with lockdep ↵Thomas Hellstrom3-6/+6
counterpart Replace instances of WARN_ON[_ONCE](!mutex_is_held()) with lockdep_assert_held(). This makes sure the checking process actually holds the mutex and also removes the checks from release builds Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]> Reviewed-by: Deepak Rawat <[email protected]>
2018-09-27drm/vmwgfx: Reduce the size of buffer object relocationsThomas Hellstrom1-4/+5
With the new allocator this leads to less consumed memory for each user-space command submission Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Deepak Rawat <[email protected]>
2018-09-27drm/vmwgfx: Use a validation context allocator for relocations and validationsThomas Hellstrom4-64/+132
A common trait of these objects are that they are allocated during the command validation phase and freed after command submission. Furthermore they are accessed by a single thread only. So provide a simple unprotected stack-like allocator from which these objects can be allocated. Their memory is freed with the validation context when the command submission is done. Note that the mm subsystem maintains a per-cpu cache of single pages to make single page allocation and freeing efficient. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]>
2018-09-27drm/vmwgfx: Use new validation interface for the modesetting code v2Thomas Hellstrom4-216/+86
Strip the old KMS helpers and use the new validation interface also in the modesetting code. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Deepak Rawat <[email protected]> #v1 Reviewed-by: Sinclair Yeh <[email protected]>
2018-09-27drm/vmwgfx: Adapt execbuf to the new validation apiThomas Hellstrom3-594/+360
Strip the old execbuf validation functionality and use the new API instead. Also use the new API for a now removed execbuf function that was called from the kms code. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]>
2018-09-27drm/vmwgfx: Modify the resource validation interfaceThomas Hellstrom5-9/+12
Allow selecting interruptible or uninterruptible waits to match expectations of callers. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Deepak Rawat <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]>
2018-09-27drm/vmwgfx: Add a validation module v2Thomas Hellstrom3-0/+862
Isolate the functionality needed for reservation, validation and fencing of vmwgfx buffer objects and resources and publish an API for this. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]> Reviewed-by: Deepak Rawat <[email protected]> #v1
2018-09-27drm/ttm, drm/vmwgfx: Move the lock- and object functionality to the vmwgfx ↵Thomas Hellstrom10-38/+15
driver No other driver is using this functionality so move it out of TTM and into the vmwgfx driver. Update includes and remove exports. Also annotate to remove false static analyzer lock balance warnings. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Christian König <[email protected]>
2018-09-27clocksource/drivers/timer-atmel-pit: Properly handle error casesAlexandre Belloni1-6/+14
The smatch utility reports a possible leak: smatch warnings: drivers/clocksource/timer-atmel-pit.c:183 at91sam926x_pit_dt_init() warn: possible memory leak of 'data' Ensure data is freed before exiting with an error. Reported-by: Dan Carpenter <[email protected]> Signed-off-by: Alexandre Belloni <[email protected]> Cc: [email protected] Signed-off-by: Daniel Lezcano <[email protected]>
2018-09-27dt-bindings: display: sun4i-drm: Add R40 mixer compatiblesJernej Skrabec1-0/+2
R40 DE2 mixers are similar to those found in A83T, except it needs different clock settings. Add a compatibles for them. Reviewed-by: Chen-Yu Tsai <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Signed-off-by: Sean Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-09-27Revert "drm/sun4i: Remove R40 display pipeline compatibles"Chen-Yu Tsai3-0/+26
This reverts commit 3510e7a7f91088159bfc67e8abdc9f9e77d28870. During the 4.19 merge window for drm-misc, two patches critical to supporting the display pipeline on the Allwinner R40 SoC were missed. They were applied later but missed the merge window deadline. As a result 4.19-rc1 kernel would crash on the R40 when it couldn't parse the new device tree structure. We ended up removing support for the R40 display pipeline for 4.19. Since the missing patches are already merged for 4.20, we can now revert the commit that removed support. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Sean Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-09-27Merge drm/drm-next into drm-misc-nextSean Paul1436-20443/+99411
Backmerging 4.19-rc5 to pick up sun4i fix Signed-off-by: Sean Paul <[email protected]>
2018-09-26drm/amdgpu/vcn: whitespace cleanupAlex Deucher1-18/+18
Fix some indentation issues. Reviewed-by: Christian König <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu/soc15: fix warnings in register macroAlex Deucher1-1/+1
expects argument of type ‘unsigned int’ has type ‘long int’ Fixes: 52e211c1f04 ("drm/amdgpu:Add error message when register failed to reach expected value") Reviewed-by: Christian König <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu:Enable DPG mode on PCOJames Zhu1-1/+2
Add flag AMD_PG_SUPPORT_DPG to enable DPG mode on Picasso Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu:Add DPG pause mode supportJames Zhu1-2/+159
Add functions to support VCN DPG pause mode. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu:Add DPG pause stateJames Zhu1-0/+11
Add DPG pause state to support VCN DPG mode. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu:Add DPG mode support for vcn 1.0James Zhu1-6/+313
Add DPG mode start/stop/mc_resume/clock_gating to support vcn 1.0 DPG mode. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu:Add DPG mode read/write macroJames Zhu1-0/+20
Some registers read/write needs program through SDRAM pool under DPG mode. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu:Add DPG support flagJames Zhu1-0/+1
Add DPG support flag for VCN DPG mode. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu:Add new register offset/mask to support VCN DPG modeJames Zhu2-0/+33
New register offset/mask need to be added to support VCN DPG mode. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu:Use register UVD_SCRATCH9 for VCN ring/ib testJames Zhu1-8/+8
Use register UVD_SCRATCH9 for VCN ring/ib test. Since those registers can't be directly accessed under DPG(Dynamic Power Gate) mode. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: move more defines into amdgpu_irq.hChristian König35-95/+94
Everything that isn't related to the IH ring. Signed-off-by: Christian König <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: move more interrupt processing into amdgpu_irq.cChristian König3-21/+38
Add a callback to amdgpu_ih_process to remove most of the IV logic. Signed-off-by: Christian König <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: Move fence SW fallback warning v3Andrey Grodzovsky2-5/+9
Only print the warning if there was actually some fence processed from the SW fallback timer. v2: Add return value to amdgpu_fence_process to let amdgpu_fence_fallback know fences were actually processed and then print the warning. v3: Always return true if seq != last_seq Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-off-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: cleanup amdgpu_ih.cChristian König9-102/+84
Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings. Signed-off-by: Christian König <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: make function pointers mandatoryChristian König20-90/+55
We always want those to be setup correctly. Signed-off-by: Christian König <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: drop extra newline in amdgpu_iv traceChristian König1-1/+1
That is superflous here. Signed-off-by: Christian König <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: fix the page fault of raven2Huang Rui2-2/+4
While the apg_end address is 0xffffffff, if add 1 with it, the value will be overflow and roll back to 0. So when 0 is written to mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, the system aperture is actually disabled. And so any access to vram will trigger a page fault. Raven2's HW issue only need increase the vram end address, and needn't do it on the agp. Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/pp: Disable dpm features on smu7/8 when suspendRex Zhu2-18/+32
Need to disable dpm features before halt rlc. Acked-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: Remove redundant code in gfx_v8_0.cRex Zhu1-20/+0
the CG related registers have been programed in golden setting PG register default value is 0. Acked-by: Alex Deucher <[email protected]> Signed-off-by: Hang Zhou <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: Halt rlc/cp in rlc_safe_modeRex Zhu1-27/+59
before halt rlc/cp, need to 1. enter rlc safe mode 2. wait rlc/cp idle Acked-by: Alex Deucher <[email protected]> Signed-off-by: Hang Zhou <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: Refine function nameRex Zhu4-11/+11
change function name gfx_v6/7/8/9_0_gpu_init to gfx_v6/7/8/9_0_constants_init. this function is just for init gfx constants such as max pipes, render backends... Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: Deactivate SW interrupt fallback in amdgpu_fence_process v2Andrey Grodzovsky1-2/+3
Deactivate SW interrupt fallback when all emited fences are completed. Also switch interrupt SW fallback message from INFO to WARN. v2: shorten the warning message a bit and only re-activate the timer during processing if it was already activated before. (Christian) Signed-off-by: Andrey Grodzovsky <[email protected]> Suggested-by: Christian Konig <[email protected]> Reviewed-and-Tested-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdkfd: Vega20 bring up on amdkfd sideShaoyun Liu8-0/+29
Add Vega20 device IDs, device info and enable it in KFD. Signed-off-by: Shaoyun Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Felix Kuehling <[email protected]>
2018-09-26drm/amdgpu: Add vega20 support on kfd probeShaoyun Liu1-0/+1
Add Vega20 support in amdgpu_amdkfd_device_probe. Signed-off-by: Shaoyun Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Felix Kuehling <[email protected]>
2018-09-26drm/amd: Interface change to support 64 bit page_table_baseShaoyun Liu9-23/+28
amdgpu_gpuvm_get_process_page_dir should return the page table address in the format expected by the pm4_map_process packet for all ASIC generations. Signed-off-by: Shaoyun Liu <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]>
2018-09-26drm/amdkfd: Make the number of SDMA queues variableShaoyun Liu4-4/+17
Vega20 supports 8 SDMA queues per engine Signed-off-by: Shaoyun Liu <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of Vega10Emily Deng3-11/+37
Correct the format For vega10 sriov, the sdma doorbell must be fixed as follow to keep the same setting with host driver, or it will happen conflicts. Signed-off-by: Emily Deng <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: Doorbell assignment for 8 sdma user queue per engineShaoyun Liu3-25/+33
Change doorbell assignments to allow routing doorbells for 8 user mode SDMA queues per engine. Signed-off-by: Shaoyun Liu <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu: remove unnecessary forward declarationFelix Kuehling1-2/+0
struct vi_sdma_mqd is defined in vi_structs.h. Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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