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2023-06-13arm64: dts: qcom: sdm845-shift-axolotl: enable pmi8998 chargerCaleb Connolly1-0/+10
Enable the PMI8998/smb2 charger, and denote the secondary SMB1355 charger which is used for parallel charging. Signed-off-by: Caleb Connolly <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sdm845-oneplus: enable pmi8998 chargerCaleb Connolly3-0/+12
Enable the pmi8998 charger on both devices, enabling charging speeds above the default 500mA limit the bootloader sets. Signed-off-by: Caleb Connolly <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: pmi8998: add charger nodeCaleb Connolly1-0/+20
Add a node for the smb2 charger hardware found on the pmi8998 pmic following the DT bindings. Signed-off-by: Caleb Connolly <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: pmi8998: enable rradc by defaultCaleb Connolly5-18/+0
There is no need for the RRADC to be disabled by default, lets just enable it by default and not clutter up DT. Acked-by: Konrad Dybcio <[email protected]> Signed-off-by: Caleb Connolly <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: ipq9574: Enable crypto nodesAnusha Rao1-0/+20
Enable crypto support for ipq9574. Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Anusha Rao <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13Merge branch '[email protected]' into arm64-for-6.5Bjorn Andersson2-0/+5
Merge IPQ9574 Crypto Engine-related DeviceTree bindings, to gain the additional clock defines needed to add the related nodes.
2023-06-13dt-bindings: clock: Add crypto clock and reset definitionsAnusha Rao2-0/+5
Add crypto clock and reset ID definitions for ipq9574. Acked-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Bhupesh Sharma <[email protected]> Signed-off-by: Anusha Rao <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: qdu1000: Add IMEM and PIL info regionKomal Bajaj1-0/+13
Add a simple-mfd representing IMEM on QDU1000 and define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteprocs. Signed-off-by: Komal Bajaj <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: adapt to LP855X bindings changesArtur Weber1-4/+2
Change underscores in ROM node names to dashes, and remove deprecated pwm-period property. Signed-off-by: Artur Weber <[email protected]> Reviewed-by: Daniel Thompson <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: ipq5332: add few more reserved memory regionKathiravan T1-1/+11
In IPQ SoCs, bootloader will collect the system RAM contents upon crash for the post morterm analysis. If we don't reserve the memory region used by bootloader, obviously linux will consume it and upon next boot on crash, bootloader will be loaded in the same region, which will lead to loose some of the data, sometimes we may miss out critical information. So lets reserve the region used by the bootloader. Similarly SBL copies some data into the reserved region and it will be used in the crash scenario. So reserve 1MB for SBL as well. While at it, drop the size padding in the smem memory region. Signed-off-by: Kathiravan T <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: ipq5332: define UART1Kathiravan T1-0/+12
Add the definition for the UART1 found on IPQ5332 SoC. Reviewed-by: Bhupesh Sharma <[email protected]> Signed-off-by: Kathiravan T <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: ipq5332: rename mi01.2 dts to rdp441Kathiravan T2-1/+1
To align with ipq5332-rdp468.dts, lets rename the mi01.2 dts as well to ipq5332-rdp441.dts. Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Kathiravan T <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sm7225-fairphone-fp4: Add BluetoothLuca Weiss1-0/+103
The device has a WCN3988 chip for WiFi and Bluetooth. Configure the Bluetooth node and enable the UART it is connected to, plus the necessary pinctrl that has been borrowed with comments from sc7280-idp.dtsi. Signed-off-by: Luca Weiss <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sm6350: add uart1 nodeLuca Weiss1-0/+63
Add the node describing uart1 incl. opp table and pinctrl. Signed-off-by: Luca Weiss <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sm8550: Flush RSC sleep & wake votesKonrad Dybcio1-0/+1
The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sm6350: Flush RSC sleep & wake votesKonrad Dybcio1-0/+1
The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: 5f82b9cda61e ("arm64: dts: qcom: Add SM6350 device tree") Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sdm845: Flush RSC sleep & wake votesKonrad Dybcio1-0/+1
The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: c83545d95376 ("arm64: dts: sdm845: Add rpmh-rsc node") Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sdm670: Flush RSC sleep & wake votesKonrad Dybcio1-0/+1
The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: 07c8ded6e373 ("arm64: dts: qcom: add sdm670 and pixel 3a device trees") Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sc8180x: Flush RSC sleep & wake votesKonrad Dybcio1-0/+1
The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: 8575f197b077 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: qdu1000: Flush RSC sleep & wake votesKonrad Dybcio1-0/+1
The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: 6bd20c54b589 ("arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs") Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sm6350: Add PSCI idle statesKonrad Dybcio1-0/+141
Add the PSCI idle states so that the CPU (among other things) can reach lower power states. Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: ipq9574: add few more reserved memory regionAnusha Rao1-1/+11
In IPQ SoCs, bootloader will collect the system RAM contents upon crash for post-morterm analysis. If we don't reserve the memory region used by bootloader, obviously linux will consume it and upon next boot on crash, bootloader will be loaded in the same region, which will lead to loss of some data, sometimes we may miss out critical information. So lets reserve the region used by the bootloader. Similarly SBL copies some data into the reserved region and it will be used in the crash scenario. So reserve 1MB for SBL as well. While at it, drop the size padding in the reserved memory region, wherever applicable Signed-off-by: Anusha Rao <[email protected]> Reviewed-by: Kathiravan T <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: ipq5332: add support for the RDP474 variantKathiravan T2-0/+113
Add the initial device tree support for the Reference Design Platform(RDP) 474 based on IPQ5332 family of SoC. This patch carries the support for Console UART, eMMC, I2C and GPIO based buttons. Signed-off-by: Kathiravan T <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13dt-bindings: arm: qcom: document MI01.9 board based on IPQ5332 familyKathiravan T1-0/+2
Document the MI01.9 (Reference Design Platform 474) board based on IPQ5332 family of SoCs. Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Kathiravan T <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sc8280xp: add resets for soundwire controllersSrinivas Kandagatla1-0/+21
Soundwire controllers on sc8280xp needs an explicit reset, add support for this. Signed-off-by: Srinivas Kandagatla <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13Merge branch '[email protected]' into ↵Bjorn Andersson2-0/+77
arm64-for-6.5 Merge the SC8280XP LPASSCC DeviceTree bindings in order to get access to the newly added reset defines.
2023-06-13dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XPSrinivas Kandagatla2-0/+15
The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13dt-bindings: clock: Add LPASSCC and reset controller for SC8280XPSrinivas Kandagatla2-0/+62
The LPASS (Low Power Audio Subsystem) clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sm8550-mtp: add sound cardKrzysztof Kozlowski1-0/+81
Add the sound card node with tested playback over WSA8845 speakers and WCD9385 headset over USB Type-C. The recording links were not tested, but should be similar to previous platforms. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sm8550-qrd: add sound cardKrzysztof Kozlowski1-0/+81
Add the sound card node with tested playback over WSA8845 speakers and WCD9385 headset over USB Type-C. The recording links were not tested, but should be similar to previous platforms. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sm8550-mtp: add WSA8845 speakersKrzysztof Kozlowski1-0/+48
Add Qualcomm WSA8845 Soundwire smart speaker amplifiers. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sm8550-qrd: add WSA8845 speakersKrzysztof Kozlowski1-0/+48
Add Qualcomm WSA8845 Soundwire smart speaker amplifiers. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: Add SDX75 platform and IDP board supportRohit Agarwal3-0/+704
Add basic devicetree support for SDX75 platform and IDP board from Qualcomm. The SDX75 platform features an ARM Cortex A55 CPU which forms the Application Processor Sub System (APSS) along with standard Qualcomm peripherals like GCC, TLMM, UART, QPIC, and BAM etc... Also, there exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem etc.. Signed-off-by: Rohit Agarwal <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13dt-bindings: arm: qcom: Document SDX75 platform and boardsRohit Agarwal1-0/+7
Document the SDX75 platform binding and also the boards using it. Signed-off-by: Rohit Agarwal <[email protected]> Acked-by: Conor Dooley <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13Merge branch '[email protected]' into arm64-for-6.5Bjorn Andersson2-0/+258
Merge the SDX75 GCC DeviceTree binding, in order to get access to the clock defines in the DeviceTree source.
2023-06-13arm64: dts: qcom: sm8550-qrd: enable PMIC Volume and Power buttonsNeil Armstrong1-0/+36
The Volume Down & Power buttons are controlled by the PMIC via the PON hardware, and the Volume Up is connected to a PMIC gpio. Enable the necessary hardware and setup the GPIO state for the Volume Up gpio key. Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/20230525-topic-sm8550-upstream-pm8550-lpg-dt-v4-4-a288f24af81b@linaro.org
2023-06-13arm64: dts: qcom: pmk8550: always enable RTC PMIC deviceNeil Armstrong1-1/+0
There's no reason to keep the RTC disabled, it has been tested and is functional on the SM8550 QRD and MTP boards. Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/20230525-topic-sm8550-upstream-pm8550-lpg-dt-v4-3-a288f24af81b@linaro.org
2023-06-13arm64: dts: qcom: sm8550-qrd: add notification RGB LEDNeil Armstrong1-0/+27
The QRD features a notification LED connected to the pm8550. Configure the RGB led controlled by the PMIC PWM controller. Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/20230525-topic-sm8550-upstream-pm8550-lpg-dt-v4-2-a288f24af81b@linaro.org
2023-06-13arm64: dts: qcom: pm8550: add PWM controllerNeil Armstrong1-0/+10
Add the PWM function to the pm8550 dtsi, this is usually used to drive RGB leds on platforms using this PMIC. Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/20230525-topic-sm8550-upstream-pm8550-lpg-dt-v4-1-a288f24af81b@linaro.org
2023-06-13arm64: dts: qcom: sc8180x: Move DisplayPort for MMCXBjorn Andersson1-3/+3
The DisplayPort blocks are powered by MMCX and should be described as such to ensure that power votes are done on the right resource. This also solves the problem that sync_state is unaware of the DP controllers needing MMCX to be kept alive during boot. As such this change also fixes occasionally seen crashes during boot due to undervoltage of MMCX. Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Signed-off-by: Bjorn Andersson <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sc8180x: Fix adreno smmu compatibleBjorn Andersson1-1/+2
The adreno smmu should be compatible with qcom,adreno-smmu as well for per-process page tables to work. Fixes: 8575f197b077 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by: Bjorn Andersson <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sc8180x-primus: dispcc is already okayBjorn Andersson1-4/+0
&dispcc status was changed to okay by default in the platform, no need to do it again in the board. Fixes: 2ce38cc1e8fe ("arm64: dts: qcom: sc8180x: Introduce Primus") Signed-off-by: Bjorn Andersson <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sm8550: add display port nodesNeil Armstrong1-2/+87
Add the Display Port controller subnode to the MDSS node. Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sm8550: fix low_svs RPMhPD labelsNeil Armstrong1-3/+3
"low" was written "lov", fix this. Fixes: 99d33ee61cb0 ("arm64: dts: qcom: sm8550: Add missing RPMhPD OPP levels") Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13arm64: dts: qcom: sa8540p-ride: Specify ethernet phy OUIAndrew Halaney1-0/+1
With wider usage on more boards, there have been reports of the following: [ 315.016174] qcom-ethqos 20000.ethernet eth0: no phy at addr -1 [ 315.016179] qcom-ethqos 20000.ethernet eth0: __stmmac_open: Cannot attach to PHY (error: -19) which has been fairly random and isolated to specific boards. Early reports were written off as a hardware issue, but it has been prevalent enough on boards that theory seems unlikely. In bring up of a newer piece of hardware, similar was seen, but this time _consistently_. Moving the reset to the mdio bus level (which isn't exactly a lie, it is the only device on the bus so one could model it as such) fixed things on that platform. Analysis on sa8540p-ride shows that the phy's reset is not being handled during the OUI scan if the reset lives in the phy node: # gpio 752 is the reset, and is active low, first mdio reads are the OUI modprobe-420 [006] ..... 154.738544: mdio_access: stmmac-0 read phy:0x08 reg:0x02 val:0x0141 modprobe-420 [007] ..... 154.738665: mdio_access: stmmac-0 read phy:0x08 reg:0x03 val:0x0dd4 modprobe-420 [004] ..... 154.741357: gpio_value: 752 set 1 modprobe-420 [004] ..... 154.741358: gpio_direction: 752 out (0) modprobe-420 [004] ..... 154.741360: gpio_value: 752 set 0 modprobe-420 [006] ..... 154.762751: gpio_value: 752 set 1 modprobe-420 [007] ..... 154.846857: gpio_value: 752 set 1 modprobe-420 [004] ..... 154.937824: mdio_access: stmmac-0 write phy:0x08 reg:0x0d val:0x0003 modprobe-420 [004] ..... 154.937932: mdio_access: stmmac-0 write phy:0x08 reg:0x0e val:0x0014 Moving it to the bus level, or specifying the OUI in the phy's compatible ensures the reset is handled before any mdio access Here is tracing with the OUI approach (which skips scanning the OUI): modprobe-549 [007] ..... 63.860295: gpio_value: 752 set 1 modprobe-549 [007] ..... 63.860297: gpio_direction: 752 out (0) modprobe-549 [007] ..... 63.860299: gpio_value: 752 set 0 modprobe-549 [004] ..... 63.882599: gpio_value: 752 set 1 modprobe-549 [005] ..... 63.962132: gpio_value: 752 set 1 modprobe-549 [006] ..... 64.049379: mdio_access: stmmac-0 write phy:0x08 reg:0x0d val:0x0003 modprobe-549 [006] ..... 64.049490: mdio_access: stmmac-0 write phy:0x08 reg:0x0e val:0x0014 The OUI approach is taken given the description matches the situation perfectly (taken from ethernet-phy.yaml): - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" description: If the PHY reports an incorrect ID (or none at all) then the compatible list may contain an entry with the correct PHY ID in the above form. The first group of digits is the 16 bit Phy Identifier 1 register, this is the chip vendor OUI bits 3:18. The second group of digits is the Phy Identifier 2 register, this is the chip vendor OUI bits 19:24, followed by 10 bits of a vendor specific ID. With this in place the sa8540p-ride's phy is probing consistently, so it seems the floating reset during mdio access was the issue. In either case, it shouldn't be floating so this improves the situation. The below link discusses some of the relationship of mdio, its phys, and points to this OUI compatible as a way to opt out of the OUI scan pre-reset handling which influenced this decision. Link: https://lore.kernel.org/all/[email protected]/ Fixes: 57827e87be54 ("arm64: dts: qcom: sa8540p-ride: Add ethernet nodes") Signed-off-by: Andrew Halaney <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Brian Masney <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13ARM: dts: qcom: msm8226: Provide clocks to mmcc nodeLuca Weiss1-0/+15
The mmcc needs several clocks that are being used as parents. Provide them in dt. Signed-off-by: Luca Weiss <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-13ARM: dts: qcom: msm8226: Use XO from rpmcc where possibleLuca Weiss1-5/+6
The xo clock being used everywhere actually goes via the RPM. Since the rpmcc driver recently got support for this clock we can use this now. Signed-off-by: Luca Weiss <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-06-11arm64: dts: rockchip: Add saradc node to rock5bShreeya Patel1-0/+5
Add ADC support for ROCK 5B. Signed-off-by: Shreeya Patel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2023-06-09arm64: tegra: Enable thermal support on Jetson Orin NanoThierry Reding1-0/+20
Enable the TJ thermal zone and hook up cooling maps for the PWM- controlled fan and two trip points. Acked-by: Jon Hunter <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2023-06-09arm64: tegra: Enable thermal support on Jetson Orin NXThierry Reding3-61/+23
Enable the TJ thermal zone and hook up cooling maps for the PWM- controlled fan and two trip points. This also removes a duplicate definition of the PWM fan and changes its cooling levels. This should have no effect, though, because the fan wasn't previously connected to anything and by default would be turned off at probe time. Acked-by: Jon Hunter <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
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