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2017-01-26clk: mediatek: Fix MT2701 dependenciesJean Delvare1-7/+8
If I say "no" to "Clock driver for Mediatek MT2701", I don't want to be asked individually about each sub-driver. No means no. Additionally, this driver shouldn't be proposed at all on non-mediatek builds, unless build-testing. Signed-off-by: Jean Delvare <[email protected]> Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support") Reviewed-by: Andreas Färber <[email protected]> Reviewed-by: James Liao <[email protected]> Cc: Shunli Wang <[email protected]> Cc: Erin Lo <[email protected]> Cc: Michael Turquette <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-26clk: ti: divider: Add the table parsing to get the best divider valueKeerthy1-1/+30
Currently the divider selection logic blindly divides the parent_rate by the clk rate and gives the divider value for the divider clocks which do not have the CLK_SET_RATE_PARENT flag set. Add the clk divider table parsing to get the closest divider available in the table provided via Device tree. The code is pretty much taken from: drivers/clk/clk-divider.c. and used here to fix up the best divider selection logic. Signed-off-by: Keerthy <[email protected]> Reported-by: Richard Woodruff <[email protected]> Acked-by: Tero Kristo <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-26clk: qcom: gdsc: Fix handling of hw control enable/disableRajendra Nayak1-13/+45
Once a gdsc is brought in and out of HW control, there is a power down and up cycle which can take upto 1us. Polling on the gdsc status immediately after the hw control enable/disable can mislead software/firmware to belive the gdsc is already either on or off, while its yet to complete the power cycle. To avoid this add a 1us delay post a enable/disable of HW control mode. Also after the HW control mode is disabled, poll on the status to check gdsc status reflects its 'on' before force disabling it in software. Reported-by: Stanimir Varbanov <[email protected]> Reviewed-by: Stanimir Varbanov <[email protected]> Tested-by: Stanimir Varbanov <[email protected]> Signed-off-by: Rajendra Nayak <[email protected]> Fixes: 904bb4f5c7de ("clk: qcom: gdsc: Add support for gdscs with HW control") Signed-off-by: Stephen Boyd <[email protected]>
2017-01-26clk: meson8b: fix clk81 register addressJerome Brunet1-1/+0
During meson8b clock probe, clk81 register address is fixed twice. First using the meson8b_clk_gates array, then by directly changing meson8b_clk81 register. As a result meson8b_clk81.reg = HHI_MPEG_CLK_CNTL + clk_base + clk_base. Fixed by just removing the second fixup. Fixes: e31a1900c1ff ("meson: clk: Add support for clock gates") Signed-off-by: Jerome Brunet <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-26clk: stm32f7: Introduce stm32f7 clocks for STM32F746 boardsGabriel Fernandez1-6/+271
This patch enables clocks for STM32F746 boards. Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-26Merge branch 'clk-stm32f4' into clk-nextStephen Boyd2-0/+40
* clk-stm32f4: clk: stm32f7: Add stm32f7 clock DT bindings for STM32F746 boards
2017-01-26clk: uniphier: continue probing even if some clocks fail to registerMasahiro Yamada1-5/+2
Do not let the entire probe function fail even if some clocks fail to register. Let's continue with succeeded clocks. This will give the system more chances to boot and allow us to investigate the cause of the failure. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-26Merge branch 'clk-imx7', 'clk-bcm2835' into clk-nextStephen Boyd5-51/+273
* clk-imx7: clk: imx7d: Add the OCOTP clock * clk-bcm2835: clk: bcm2835: Add leaf clock measurement support, disabled by default clk: bcm2835: Register the DSI0/DSI1 pixel clocks. clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.
2017-01-23ARM: gr8: Convert to CCUMaxime Ripard1-464/+56
Now that we have a driver for the GR8, we can convert our DT to it. Acked-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2017-01-23ARM: sun5i: Convert to CCUMaxime Ripard4-513/+75
Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2017-01-23clk: sunxi-ng: Add sun5i CCU driverMaxime Ripard6-0/+1235
The Allwinner A10s, A13, R8 and NextThing GR8 are all based on the same silicon, and all share the same clocks. However, they're not packaged in the same way, and therefore not all the controllers are actually available on all these SoCs. Introduce a clock controller driver for all these SoCs with different compatibles to take that into account. Acked-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2017-01-23clk: sunxi-ng: Implement global pre-dividerMaxime Ripard2-1/+9
Some clocks have a global pre-divider that applies to all their parents. Since it might also apply to clocks that have a single parent, this is merged in the ccu_common structure, unlike the other pre-divider settings that are tied to a specific index, and thus a specific parent. Acked-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2017-01-23clk: sunxi-ng: Implement multiplier maximumMaxime Ripard6-20/+32
Some multipliers have a maximum rate that is lower than what the register width allows to. Add a field in the multiplier structure to allow CCU driver to set that maximum. Acked-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2017-01-23clk: sunxi-ng: mult: Fix minimum in round rateMaxime Ripard1-1/+1
The previous code was always taking 1 as the minimum in it's round_rate function, ignoring entirely what was set as minimum in the clock definition. Make sure that's not the case anymore. Fixes: 2beaa601c849 ("clk: sunxi-ng: Implement minimum for multipliers") Acked-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2017-01-23clk: sunxi-ng: Implement factors offsetsMaxime Ripard8-29/+79
The factors we've seen so far all had an offset of one. However, on the earlier Allwinner SoCs, some factors could have no offset at all, meaning that the value computed to reach the rate we want to use was the one we had to program in the registers. Implement an additional field for the factors that can have such an offset (linears, not based on a power of two) to specify that offset. This offset is not linked to the extremums that can be specified in those structures too. The minimum and maximum are representing the range of values we can use to try to compute the best rate. The offset comes later on when we want to set the best value in the registers. Acked-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2017-01-23clk: sunxi-ng: multiplier: Add fractional supportMaxime Ripard2-0/+10
Some clocks on the earlier SoCs such as the video PLLs are multipliers with fractional settings. Support those cases. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]>
2017-01-23clk: renesas: mstp: Make INTC-SYS a critical clockGeert Uytterhoeven1-0/+5
INTC-SYS is the module clock for the GIC. Accessing the GIC while it is disabled causes: Unhandled fault: asynchronous external abort (0x1211) at 0x00000000 Currently, the GIC-400 driver cannot enable its module clock for several reasons: - It does not use a platform device, so Runtime PM is not an option, - gic_of_init() runs before any clocks are registered, so it cannot enable the clock explicitly, - gic_of_init() cannot return -EPROBE_DEFER, as IRQCHIP_DECLARE() doesn't support deferred probing. Hence we have to keep on relying on the boot loader for enabling the module clock. To prevent the module clock from being disabled when the CCF core thinks it is unused, and thus causing a system lock-up, add a check to the MSTP clock driver and enable CLK_IS_CRITICAL. This will make sure the module clock is never disabled. This is a hard dependency for describing the INTC-SYS clock in DT on R-Mobile APE6 and R-Car Gen2. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Stephen Boyd <[email protected]>
2017-01-23clk: renesas: cpg-mssr: Migrate to CLK_IS_CRITICALGeert Uytterhoeven1-9/+2
When the Renesas CPG/MSSR driver was introduced, it was anticipated that critical clocks would be handled through a new CLK_ENABLE_HAND_OFF flag soon. However, CLK_ENABLE_HAND_OFF never made it upstream. Instead, commit 32b9b10961860860 ("clk: Allow clocks to be marked as CRITICAL") introduced CLK_IS_CRITICAL, a flag with slightly differing semantics. Still, it can be used to prevent e.g. the GIC module clock from being turned off, until the GIC-400 driver has full support for Runtime PM. Hence migrate the Renesas CPG/MSSR driver from CLK_ENABLE_HAND_OFF to CLK_IS_CRITICAL. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Stephen Boyd <[email protected]>
2017-01-23clk: rockchip: rk3288: make all niu clocks criticalJacob Chen1-7/+14
NIU clocks are related to the interconnect and it's important to other blocks. Since we don't have a driver to handle it, we should always enable it to avoid casually close. Make all of them critical,so that we don't have to each clock on its own once things break. Signed-off-by: Jacob Chen <[email protected]> [dropped the matching CLK_IGNORE_UNUSED flags] Signed-off-by: Heiko Stuebner <[email protected]>
2017-01-22clk: rockchip: use rk3288 vip_out clock idsJacob Chen1-1/+1
Reference the newly added vip clock-ids in the clock-tree. Signed-off-by: Jacob Chen <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2017-01-22Merge branch 'v4.11-shared/clkids' into v4.11-clk/nextHeiko Stuebner1-0/+1
2017-01-22clk: rockchip: add rk3288 vip_out clock idJacob Chen1-0/+1
Add clock-ids for the vip block of the rk3288 Signed-off-by: Jacob Chen <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2017-01-20clk: stm32f7: Add stm32f7 clock DT bindings for STM32F746 boardsGabriel Fernandez2-0/+40
This patch introduces the stm32f7 clock DT bindings. Signed-off-by: Gabriel Fernandez <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-20clk: imx7d: Add the OCOTP clockFabio Estevam2-1/+3
Add the OCOTP so that this hardware block can be used. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-20clk: bcm2835: Add leaf clock measurement support, disabled by defaultEric Anholt1-25/+119
This proved incredibly useful during debugging of the DSI driver, to see if our clocks were running at rate we requested. Let's leave it here for the next person interacting with clocks on the platform (and so that hopefully we can just hook it up to debugfs some day). Signed-off-by: Eric Anholt <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-20clk: bcm2835: Register the DSI0/DSI1 pixel clocks.Eric Anholt3-13/+125
The DSI pixel clocks are muxed from clocks generated in the analog phy by the DSI driver. In order to set them as parents, we need to do the same name lookup dance on them as we do for our root oscillator. Signed-off-by: Eric Anholt <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-20clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.Eric Anholt1-14/+28
Our core PLLs are intended to be configured once and left alone. With the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would change PLLD just to get closer to the requested DSI clock, thus changing PLLD_PER, the UART and ethernet PHY clock rates downstream of it, and breaking ethernet. We *do* want PLLH to change so that PLLH_AUX can be exactly the value we want, though. Thus, we need to have a per-divider policy of whether to pass rate changes up. Signed-off-by: Eric Anholt <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-20clk: cs2000: add Suspend/Resume featureKhiem Nguyen1-0/+22
CS2000 needs re-setup when redume, otherwise, it can't handle correct clock rate. Signed-off-by: Khiem Nguyen <[email protected]> [Kuninori: cleanup original patch] Signed-off-by: Kuninori Morimoto <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-20clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933Marek Vasut4-0/+807
Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These chips have two clock inputs, XTAL or CLK, which are muxed into single PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip while the 5P49V5923 requires external XTAL. The PLL feeds two fractional dividers. Each fractional divider feeds output mux, which allows selecting between clock from the fractional divider itself or from output mux on output N-1. In case of output mux 0, the output N-1 is instead connected to the output from the mux feeding the PLL. The driver thus far supports only the 5P49V5923 and 5P49V5933, while it should be easily extensible to the whole 5P49V59xx family of chips as they are all pretty similar. Signed-off-by: Marek Vasut <[email protected]> Cc: Michael Turquette <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Tested-by: Laurent Pinchart <[email protected]> Cc: [email protected] Signed-off-by: Stephen Boyd <[email protected]>
2017-01-20clk: vc5: Add bindings for IDT VersaClock 5P49V5923 and 5P49V5933Marek Vasut1-0/+65
Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These are I2C clock generators with optional clock source from either XTal or dedicated clock generator and, depending on the model, two or more clock outputs. Signed-off-by: Marek Vasut <[email protected]> Cc: Michael Turquette <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Acked-by: Rob Herring <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Stephen Boyd <[email protected]>
2017-01-20Merge tag 'v4.11-rockchip-clk1' of ↵Stephen Boyd13-13/+1533
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk updates from Heiko Stuebner: A new clock-type for the 1-2 muxes per soc that are for whatever reason controlled through the General Register Files, support for the rk3328 clock-controller (including a new pll-type) and the usual clock ids and some fixes. * tag 'v4.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: clk: add rockchip,grf property for RK3399 clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188 clk: rockchip: use rk3288 isp_in clock ids clk: rockchip: add clock ids for memory controller parts on rk3066/rk3188 clk: rockchip: add rk3288 isp_in clock ids clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFER clk: rockchip: add clock controller for rk3328 dt-bindings: add bindings for rk3328 clock controller clk: rockchip: add dt-binding header for rk3328 clk: rockchip: add new pll-type for rk3328 clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288 clk: rockchip: add a clock-type for muxes based in the grf
2017-01-20Merge tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung into ↵Stephen Boyd7-1439/+18
clk-next Pull Samsung clk updates from Sylwester Nawrocki: - addition of the CPU clock configuration data for Exynos4412 Prime SoC variant, - removal of driver for deprecated Exynos4415 SoC, - switching from the syscore to regular system sleep PM ops in the audio subsystem clocks controller driver, - updates of the definitions of some "Network On Chip" related clocks. * tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung: clk: samsung: Remove Exynos4415 driver (SoC not supported anymore) clk: samsung: exynos-audss: Replace syscore PM with platform device PM clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as critical clk: samsung: Add CPU clk configuration data for Exynos4412 Prime
2017-01-20clk: imx6: don't restrict LDB mux changes on QuadPlusLucas Stach1-8/+13
The LDB mux/gate layout has been fixed on QuadPlus, so there is no need to restrict the LDB mux changes on this hardware, as the erratum preventing this from working properly is gone. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-20Merge tag 'clk-renesas-for-v4.11-tag1' of ↵Stephen Boyd1-0/+9
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull renesas clk updates from Geert Uytterhoeven: - Add CAN and MSIOF related clocks for R-Car M3-W. * tag 'clk-renesas-for-v4.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add MSIOF controller clocks clk: renesas: r8a7796: Add CAN FD peripheral clock clk: renesas: r8a7796: Add CANFD clock clk: renesas: r8a7796: Add CAN peripheral clock
2017-01-20clk: sunxi-ng: add support for V3s CCUIcenowy Zheng6-0/+851
V3s has a similar but cut-down CCU to H3. Some muxes, especially clocks about CSI, are different, which makes it to need a new CCU driver. Add such a new driver for it. Signed-off-by: Icenowy Zheng <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2017-01-20dt-bindings: add device binding for the CCU of Allwinner V3sIcenowy Zheng1-0/+1
Allwinner V3s is now driven by sunxi-ng CCU driver. Add devicetree binding for it. Signed-off-by: Icenowy Zheng <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2017-01-18clk: rockchip: fix the incorrect pclk_edp div width for RK3399Xing Zheng1-1/+1
The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5. Reported-by: Lin Huang <[email protected]> Signed-off-by: Xing Zheng <[email protected]> Tested-by: Lin Huang <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2017-01-17clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-digMylène Josserand1-1/+1
The audio DAI needs to set the clock rates of the ac-dig clock. To make it possible, the parent PLL audio clock rates should also be changed. This is possible via "CLK_SET_RATE_PARENT" flag. Signed-off-by: Mylène Josserand <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2017-01-16clk: samsung: Remove Exynos4415 driver (SoC not supported anymore)Krzysztof Kozlowski4-1421/+0
Support for Exynos4415 is going away because there are no internal nor external users. Since commit 46dcf0ff0de3 ("ARM: dts: exynos: Remove exynos4415.dtsi"), the platform cannot be instantiated so remove also the drivers. Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Kukjin Kim <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2017-01-13dt-bindings: clk: add rockchip,grf property for RK3399Xing Zheng1-0/+6
Add support for rockchip,grf property which is used for GRF muxes on RK3399. Signed-off-by: Xing Zheng <[email protected]> Reviewed-by: Douglas Anderson <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2017-01-13clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188Heiko Stuebner1-2/+2
Add the newly added clock ids to the clock entries of the rk3066/rk3188 clock driver. We won't be needing them in the kernel for a bit yet but as they're used in the new u-boot ddr setup code/dts we should make sure the clock ids stay identical and do not differ. Signed-off-by: Heiko Stuebner <[email protected]>
2017-01-13clk: rockchip: use rk3288 isp_in clock idsJacob Chen1-1/+1
Reference the newly added isp clock-ids in the clock-tree. Signed-off-by: Jacob Chen <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2017-01-13Merge branch 'v4.11-shared/clkids' into v4.11-clk/nextHeiko Stuebner2-0/+3
2017-01-13clk: rockchip: add clock ids for memory controller parts on rk3066/rk3188Heiko Stuebner1-0/+2
Add clock ids for the upctl and publ controllers used for ddr control. Signed-off-by: Heiko Stuebner <[email protected]>
2017-01-13clk: rockchip: add rk3288 isp_in clock idsJacob Chen1-0/+1
Add clock-ids for the isp block of the rk3288. Signed-off-by: Jacob Chen <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2017-01-12clk: stm32f4: avoid uninitialized variable accessArnd Bergmann1-5/+7
The failure path in the newly added function tries to free an uninitialized pointer: drivers/clk/clk-stm32f4.c: In function 'stm32f4_rcc_init': drivers/clk/clk-stm32f4.c:1106:4: error: 'gate' may be used uninitialized in this function [-Werror=maybe-uninitialized] I'm adding an initialization to NULL here to make the kfree() succeed, and I'm also rearranging the cleanup so that the same kfree() is used for any error path, making the function slightly more robust against newly introduced bugs in the error handling. Fixes: daf2d117cbca ("clk: stm32f4: Add lcd-tft clock") Signed-off-by: Arnd Bergmann <[email protected]> Acked-by: Gabriel Fernandez <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-09Merge branch 'clk-fixes' into clk-nextStephen Boyd1-7/+7
* clk-fixes: clk/samsung: exynos542x: mark some clocks as critical
2017-01-09clk: cdce925: add support for CDCE913, CDCE937, and CDCE949Akinobu Mita3-34/+100
The CDCE925 is a member of the CDCE(L)9xx programmable clock generator family. There are also CDCE913, CDCE937, CDCE949 which have different number of PLLs and outputs. The clk-cdce925 driver supports only CDCE925 in the family. This adds support for the CDCE913, CDCE937, CDCE949, too. Signed-off-by: Akinobu Mita <[email protected]> Acked-by: Rob Herring <[email protected]> Cc: Mike Looijmans <[email protected]> Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-09clk: mdm9615: Add EBI2 clockZoran Markovic2-0/+32
Add definition of EBI2 clock used by MDM9615 NAND controller. Cc: Andy Gross <[email protected]> Cc: David Brown <[email protected]> Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Signed-off-by: Zoran Markovic <[email protected]> Acked-by: Neil Armstrong <[email protected]> [[email protected]: ebi2_clk halt bit is 24 not 23] Signed-off-by: Stephen Boyd <[email protected]>
2017-01-09clk: uniphier: remove unneeded #include <linux/delay.h>Masahiro Yamada1-1/+0
This include was needed to suppress build error when this driver was initially merged because <linux/regmap.h> did not include <linux/delay.h> at that time. (developers' headache across sub-systems) The root cause has been fixed by commit adf08d481b52 ("regmap: include <linux/delay.h> from include/linux/regmap.h"), so this line can be dropped now. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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