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2017-01-09clk: mvebu: adjust AP806 CPU clock frequencies to production chipThomas Petazzoni1-5/+23
This commit adjusts the list of possible "Sample At Reset" values that define the CPU clock frequency of the AP806 (part of Marvell Armada 7K/8K) to the values that have been validated with the production chip. Earlier values were preliminary. Signed-off-by: Thomas Petazzoni <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-09Merge branch 'clk-hi3660' into clk-nextStephen Boyd5-0/+811
* clk-hi3660: clk: hisilicon: Add clock driver for hi3660 SoC dt-bindings: Document the hi3660 clock bindings
2017-01-09clk: hisilicon: Add clock driver for hi3660 SoCZhangfei Gao4-0/+769
Add clock drivers for hi3660 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. Signed-off-by: Zhangfei Gao <[email protected]> [[email protected]: Simplify probe with function pointer] Signed-off-by: Stephen Boyd <[email protected]>
2017-01-09dt-bindings: Document the hi3660 clock bindingsZhangfei Gao1-0/+42
Add DT bindings documentation for hi3660 SoC clock. Signed-off-by: Zhangfei Gao <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-09clk/samsung: exynos542x: mark some clocks as criticalMarek Szyprowski1-7/+7
Some parent clocks of the Exynos542x clock blocks, which have separate power domains (like DISP, MFC, MSC, GSC, FSYS and G2D) must be always enabled to access any register related to power management unit or devices connected to it. For the time being, until a proper solution based on runtime PM is applied, mark those clocks as critical (instead of ignore unused or even no flags) to prevent disabling them. Signed-off-by: Marek Szyprowski <[email protected]> Acked-by: Sylwester Nawrocki <[email protected]> Reviewed-by: Chanwoo Choi <[email protected]> Reviewed-by: Javier Martinez Canillas <[email protected]> Tested-by: Javier Martinez Canillas <[email protected]> [Exynos5800 Peach Pi Chromebook] Signed-off-by: Stephen Boyd <[email protected]>
2017-01-09clk: clk-conf: Do not print error messages if EPROBE_DEFERGeert Uytterhoeven1-6/+9
EPROBE_DEFER is not an error, hence printing an error message like clk: couldn't get clock 0 for /soc/display@feb00000 may confuse the user. Suppress error messages in case of probe deferral to fix this. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Javier Martinez Canillas <[email protected]> Reviewed-by: Marek Vasut <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-09clk: scpi: don't add cpufreq device if the scpi dvfs node is disabledSudeep Holla1-6/+8
Currently we add the virtual cpufreq device unconditionally even when the SCPI DVFS clock provider node is disabled. This will cause cpufreq driver to throw errors when it gets initailised on boot/modprobe and also when the CPUs are hot-plugged back in. This patch fixes the issue by adding the virtual cpufreq device only if the SCPI DVFS clock provider is available and registered. Fixes: 9490f01e2471 ("clk: scpi: add support for cpufreq virtual device") Reported-by: Michał Zegan <[email protected]> Cc: Neil Armstrong <[email protected]> Signed-off-by: Sudeep Holla <[email protected]> Tested-by: Michał Zegan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-09clk: qcom: Add GCC_MSS_RESET supportAvaneesh Kumar Dwivedi2-0/+2
Add support to use reset control framework for resetting MSS with hexagon v56 1.5.0. Signed-off-by: Avaneesh Kumar Dwivedi <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-09clk: zte: add audio clocks for zx296718Jun Nie3-0/+275
The audio related clock support is missing from the existing zx296718 clock driver. Let's add it, so that the upstream ZX SPDIF driver can work for HDMI audio support. Signed-off-by: Jun Nie <[email protected]> Signed-off-by: Shawn Guo <[email protected]> [[email protected]: Staticize some more structures] Signed-off-by: Stephen Boyd <[email protected]>
2017-01-09dt-bindings: zx296718-clk: add compatible for audio clock controllerShawn Guo1-0/+3
It adds the compatible string for zx296718 audio clock controller. Signed-off-by: Shawn Guo <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-09clk: zx296718: do not panic on failureShawn Guo1-9/+18
Instead of using panic, we should give an error message and return error code when of_clk_add_hw_provider() call fails. Since we have error prompt for failures, the "init over" pr_info output isn't really necessary but becomes a debug noise. So let's clean it up along the way. Signed-off-by: Shawn Guo <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-09clk: wm831x: fix usleep_range with bad rangeNicholas Mc Guire1-1/+2
The delay here is not in atomic context and does not seem critical with respect to precision, but usleep_range(min,max) with min==max results in giving the timer subsystem no room to optimize uncritical delays. Fix this by setting the range to 2000,3000 us. Fixes: commit f05259a6ffa4 ("clk: wm831x: Add initial WM831x clock driver") Signed-off-by: Nicholas Mc Guire <[email protected]> Acked-by: Charles Keepax <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-09clk: imx: pllv3: support fractional multiplier on vf610 PLL1/PLL2Nikita Yushchenko3-2/+102
On vf610, PLL1 and PLL2 have registers to configure fractional part of frequency multiplier. This patch adds support for these registers. This fixes "fast system clock" issue on boards where bootloader sets fractional multiplier for PLL1. Suggested-by: Andrey Smirnov <[email protected]> CC: Chris Healy <[email protected]> Signed-off-by: Nikita Yushchenko <[email protected]> Tested-by: Andrey Smirnov <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-09clk/axs10x: Clear init field in driver probeJose Abreu1-0/+1
Init field must be cleared in driver probe as this structure is not dinamically allocated. If not, wrong flags can be passed to core. Signed-off-by: Jose Abreu <[email protected]> Cc: Carlos Palminha <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: Michael Turquette <[email protected]> Cc: [email protected] Cc: [email protected] Fixes: 923587aafc2c ("clk/axs10x: Add I2S PLL clock driver") Signed-off-by: Michael Turquette <[email protected]> Link: lkml.kernel.org/r/040cc9afdfa0e95ce7a01c406ff427ef7dc0c0fd.1481540717.git.joabreu@synopsys.com
2017-01-09Merge branches 'clk-qcom-rpm8974', 'clk-stm32f4', 'clk-ipq4019' and ↵Stephen Boyd9-42/+1242
'clk-fixes' into clk-next * clk-qcom-rpm8974: clk: qcom: smd-rpmcc: Add msm8974 clocks * clk-stm32f4: clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board clk: stm32f4: Add SAI clocks clk: stm32f4: Add I2S clock clk: stm32f4: Add lcd-tft clock clk: stm32f4: Add post divisor for I2S & SAI PLLs clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards clk: stm32f4: Update DT bindings documentation * clk-ipq4019: clk: qcom: ipq4019: Add the cpu clock frequency change notifier clk: qcom: ipq4019: Add all the frequencies for apss cpu clk: qcom: ipq4019: correct sdcc frequency and parent name clk: qcom: ipq4019: Add the nodes for pcnoc clk: qcom: ipq4019: Add the apss cpu pll divider clock node clk: qcom: ipq4019: remove fixed clocks and add pll clocks * clk-fixes: clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method clk: renesas: mstp: Support 8-bit registers for r7s72100
2017-01-06clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFERDouglas Anderson1-1/+0
When we used to defer setting the "grf" member to rockchip_clk_get_grf() it was important to init the "grf" member to an error value in rockchip_clk_init(). With recent changes, we now set "grf" right in rockchip_clk_init() (two lines below the place where we initted it). That makes the old init useless. Get rid of it. Fixes: 6f339dc2719e ("clk: rockchip: lookup General Register Files in rockchip_clk_init") Signed-off-by: Douglas Anderson <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2017-01-05clk: rockchip: add clock controller for rk3328Elaine Zhang3-0/+914
Add the clock tree definition for the new rk3328 SoC. Signed-off-by: Elaine Zhang <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2017-01-05dt-bindings: add bindings for rk3328 clock controllerElaine Zhang1-0/+57
Add devicetree bindings for Rockchip cru which found on Rockchip SoCs. Signed-off-by: Elaine Zhang <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2017-01-05Merge branch 'v4.11-shared/clkids' into v4.11-clk/nextHeiko Stuebner1-0/+400
2017-01-05clk: rockchip: add dt-binding header for rk3328Elaine Zhang1-0/+400
Add the dt-bindings header for the rk3328, that gets shared between the clock controller and the clock references in the dts. Add softreset ID for rk3328. Signed-off-by: Elaine Zhang <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2017-01-02clk: sunxi-ng: A31: Fix spdif clock registerMarcus Cooper1-2/+2
As the SPDIF was rarely documented on the earlier Allwinner SoCs it was assumed that it had a similar clock register to the one described in the H3 User Manual. However this is not the case and it looks to shares the same setup as the I2S clock registers. Signed-off-by: Marcus Cooper <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2017-01-02clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33Icenowy Zheng1-1/+1
The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to be changeable by changing the rate of PLL_CPUX. Add CLK_SET_RATE_PARENT flag to this clock. Signed-off-by: Icenowy Zheng <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2017-01-02clk: sunxi-ng: fix PLL_CPUX adjusting on A33Icenowy Zheng1-0/+10
When adjusting PLL_CPUX on A33, the PLL is temporarily driven too high, and the system hangs. Add a notifier to avoid this situation by temporarily switching to a known stable 24 MHz oscillator. Signed-off-by: Icenowy Zheng <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2017-01-02clk: sunxi-ng: fix PLL_CPUX adjusting on H3Ondrej Jirman1-0/+10
When adjusting PLL_CPUX on H3, the PLL is temporarily driven too high, and the system becomes unstable (oopses or hangs). Add a notifier to avoid this situation by temporarily switching to a known stable 24 MHz oscillator. Signed-off-by: Ondrej Jirman <[email protected]> Tested-by: Lutz Sammer <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2017-01-02clk: rockchip: add new pll-type for rk3328Elaine Zhang2-3/+14
The rk3328's pll and clock are similar with rk3036's, it different with pll_mode_mask, the rk3328 soc pll mode only one bit(rk3036 soc have two bits) so these should be independent and separate from the series of rk3328s. Signed-off-by: Elaine Zhang <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2017-01-02clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288Heiko Stuebner1-6/+5
With the newly introduced clk type for muxes in the grf we now can describe some missing clocks, like the aclk_vcodec that selects between aclk_vdpu and aclk_vepu based on a bit set in the general register files. Signed-off-by: Heiko Stuebner <[email protected]>
2017-01-02clk: rockchip: add a clock-type for muxes based in the grfHeiko Stuebner4-0/+131
Rockchip socs often have some tiny number of muxes not controlled from the core clock controller but through bits set in the general register files. Add a clock-type that can control these as well, so that we don't need to work around them being absent. Signed-off-by: Heiko Stuebner <[email protected]>
2017-01-01Linux 4.10-rc2Linus Torvalds1-1/+1
2017-01-01Merge branch 'libnvdimm-fixes' of ↵Linus Torvalds5-143/+229
git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm Pull DAX updates from Dan Williams: "The completion of Jan's DAX work for 4.10. As I mentioned in the libnvdimm-for-4.10 pull request, these are some final fixes for the DAX dirty-cacheline-tracking invalidation work that was merged through the -mm, ext4, and xfs trees in -rc1. These patches were prepared prior to the merge window, but we waited for 4.10-rc1 to have a stable merge base after all the prerequisites were merged. Quoting Jan on the overall changes in these patches: "So I'd like all these 6 patches to go for rc2. The first three patches fix invalidation of exceptional DAX entries (a bug which is there for a long time) - without these patches data loss can occur on power failure even though user called fsync(2). The other three patches change locking of DAX faults so that ->iomap_begin() is called in a more relaxed locking context and we are safe to start a transaction there for ext4" These have received a build success notification from the kbuild robot, and pass the latest libnvdimm unit tests. There have not been any -next releases since -rc1, so they have not appeared there" * 'libnvdimm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm: ext4: Simplify DAX fault path dax: Call ->iomap_begin without entry lock during dax fault dax: Finish fault completely when loading holes dax: Avoid page invalidation races and unnecessary radix tree traversals mm: Invalidate DAX radix tree entries only if appropriate ext2: Return BH_New buffers for zeroed blocks
2016-12-30Merge tag 'docs-4.10-rc1-fix' of git://git.lwn.net/linuxLinus Torvalds2-2/+2
Pull documentation fixes from Jonathan Corbet: "Two small fixes: - A merge error on my part broke the DocBook build. I've requisitioned one of tglx's frozen sharks for appropriate disciplinary action and resolved to be more careful about testing the DocBook stuff as long as it's still around. - Fix an error in unaligned-memory-access.txt" * tag 'docs-4.10-rc1-fix' of git://git.lwn.net/linux: Documentation/unaligned-memory-access.txt: fix incorrect comparison operator docs: Fix build failure
2016-12-30Merge branch 'linus' of ↵Linus Torvalds1-2/+28
git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 Pull crypto fix from Herbert Xu: "This fixes a boot failure on some platforms when crypto self test is enabled along with the new acomp interface" * 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: crypto: testmgr - Use heap buffer for acomp test input
2016-12-29mm/filemap: fix parameters to test_bit()Olof Johansson1-1/+1
mm/filemap.c: In function 'clear_bit_unlock_is_negative_byte': mm/filemap.c:933:9: error: too few arguments to function 'test_bit' return test_bit(PG_waiters); ^~~~~~~~ Fixes: b91e1302ad9b ('mm: optimize PageWaiters bit use for unlock_page()') Signed-off-by: Olof Johansson <[email protected]> Brown-paper-bag-by: Linus Torvalds <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2016-12-29mm: optimize PageWaiters bit use for unlock_page()Linus Torvalds3-6/+45
In commit 62906027091f ("mm: add PageWaiters indicating tasks are waiting for a page bit") Nick Piggin made our page locking no longer unconditionally touch the hashed page waitqueue, which not only helps performance in general, but is particularly helpful on NUMA machines where the hashed wait queues can bounce around a lot. However, the "clear lock bit atomically and then test the waiters bit" sequence turns out to be much more expensive than it needs to be, because you get a nasty stall when trying to access the same word that just got updated atomically. On architectures where locking is done with LL/SC, this would be trivial to fix with a new primitive that clears one bit and tests another atomically, but that ends up not working on x86, where the only atomic operations that return the result end up being cmpxchg and xadd. The atomic bit operations return the old value of the same bit we changed, not the value of an unrelated bit. On x86, we could put the lock bit in the high bit of the byte, and use "xadd" with that bit (where the overflow ends up not touching other bits), and look at the other bits of the result. However, an even simpler model is to just use a regular atomic "and" to clear the lock bit, and then the sign bit in eflags will indicate the resulting state of the unrelated bit #7. So by moving the PageWaiters bit up to bit #7, we can atomically clear the lock bit and test the waiters bit on x86 too. And architectures with LL/SC (which is all the usual RISC suspects), the particular bit doesn't matter, so they are fine with this approach too. This avoids the extra access to the same atomic word, and thus avoids the costly stall at page unlock time. The only downside is that the interface ends up being a bit odd and specialized: clear a bit in a byte, and test the sign bit. Nick doesn't love the resulting name of the new primitive, but I'd rather make the name be descriptive and very clear about the limitation imposed by trying to work across all relevant architectures than make it be some generic thing that doesn't make the odd semantics explicit. So this introduces the new architecture primitive clear_bit_unlock_is_negative_byte(); and adds the trivial implementation for x86. We have a generic non-optimized fallback (that just does a "clear_bit()"+"test_bit(7)" combination) which can be overridden by any architecture that can do better. According to Nick, Power has the same hickup x86 has, for example, but some other architectures may not even care. All these optimizations mean that my page locking stress-test (which is just executing a lot of small short-lived shell scripts: "make test" in the git source tree) no longer makes our page locking look horribly bad. Before all these optimizations, just the unlock_page() costs were just over 3% of all CPU overhead on "make test". After this, it's down to 0.66%, so just a quarter of the cost it used to be. (The difference on NUMA is bigger, but there this micro-optimization is likely less noticeable, since the big issue on NUMA was not the accesses to 'struct page', but the waitqueue accesses that were already removed by Nick's earlier commit). Acked-by: Nick Piggin <[email protected]> Cc: Dave Hansen <[email protected]> Cc: Bob Peterson <[email protected]> Cc: Steven Whitehouse <[email protected]> Cc: Andrew Lutomirski <[email protected]> Cc: Andreas Gruenbacher <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Mel Gorman <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2016-12-29clk: samsung: exynos-audss: Replace syscore PM with platform device PMMarek Szyprowski1-14/+10
Exynos AUDSS clock driver has been already converted to platform driver, so remove the dependency on the syscore ops - the last remaining non-platform driver feature. Platform device's system sleep PM provides all needed infrastructure for replacing syscore-based PM, so do it now. Signed-off-by: Marek Szyprowski <[email protected]> Reviewed-by: Javier Martinez Canillas <[email protected]> Reviewed-by: Chanwoo Choi <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2016-12-29clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as criticalChanwoo Choi1-4/+4
The ACLK_BUS0/1/2 are used for NoC (Network on Chip). If NoC's clocks are disabled, the system halt happens. Following clocks must be always enabled: - CLK_ACLK_BUS0_400 : NoC's bus clock for PERIC/PERIS/FSYS/MSCL, - CLK_ACLK_BUS1_400 : NoC's bus clock for MFC/HEVC/G3D, - CLK_ACLK_BUS2_400 : NoC's bus clock for GSCL/DISP/G2D/CAM0/CAM1/ISP. This patch also adds the CLK_SET_RATE_PARENT flag to the CLK_SCLK_JPEG_MSCL because this clock should be used for bus frequency scaling. This clock need to be changed on the fly with CLK_SET_RATE_PARENT flag. Signed-off-by: Chanwoo Choi <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2016-12-29clk: samsung: Add CPU clk configuration data for Exynos4412 PrimeBartlomiej Zolnierkiewicz1-0/+4
Add cpu clock configuration data for Exynos4412 Prime SoC (it supports additional PLL rates & CPU frequencies). Based on Hardkernel's kernel for ODROID-X2/U2/U3 boards. Signed-off-by: Bartlomiej Zolnierkiewicz <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2016-12-27Merge branch 'linus' of ↵Linus Torvalds3-3/+43
git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 Pull crypto fix from Herbert Xu: "This fixes a hash corruption bug in the marvell driver" * 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: crypto: marvell - Copy IVDIG before launching partial DMA ahash requests
2016-12-27Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netLinus Torvalds17-86/+112
Pull networking fixes from David Miller: 1) Various ipvlan fixes from Eric Dumazet and Mahesh Bandewar. The most important is to not assume the packet is RX just because the destination address matches that of the device. Such an assumption causes problems when an interface is put into loopback mode. 2) If we retry when creating a new tc entry (because we dropped the RTNL mutex in order to load a module, for example) we end up with -EAGAIN and then loop trying to replay the request. But we didn't reset some state when looping back to the top like this, and if another thread meanwhile inserted the same tc entry we were trying to, we re-link it creating an enless loop in the tc chain. Fix from Daniel Borkmann. 3) There are two different WRITE bits in the MDIO address register for the stmmac chip, depending upon the chip variant. Due to a bug we could set them both, fix from Hock Leong Kweh. 4) Fix mlx4 bug in XDP_TX handling, from Tariq Toukan. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: net: stmmac: fix incorrect bit set in gmac4 mdio addr register r8169: add support for RTL8168 series add-on card. net: xdp: remove unused bfp_warn_invalid_xdp_buffer() openvswitch: upcall: Fix vlan handling. ipv4: Namespaceify tcp_tw_reuse knob net: korina: Fix NAPI versus resources freeing net, sched: fix soft lockup in tc_classify net/mlx4_en: Fix user prio field in XDP forward tipc: don't send FIN message from connectionless socket ipvlan: fix multicast processing ipvlan: fix various issues in ipvlan_process_multicast()
2016-12-27clk: qcom: ipq4019: Add the cpu clock frequency change notifierAbhishek Sahu1-1/+39
The current driver code gives the crash or gets hang while switching the CPU frequency some time. The APSS CPU Clock divider is not glitch free so it the APPS clock need to be switched for stable clock during the change. This patch adds the frequency change notifier for APSS CPU clock. It changes the parent of this clock to stable PLL FEPLL500 for PRE_RATE_CHANGE event. This event will be generated before actual clock set operations. The clock set operation will again change its corresponding parent by getting the same from frequency table. Signed-off-by: Abhishek Sahu <[email protected]> [[email protected]: Indent less in probe] Signed-off-by: Stephen Boyd <[email protected]>
2016-12-27Documentation/unaligned-memory-access.txt: fix incorrect comparison operatorCihangir Akturk1-1/+1
In the actual implementation ether_addr_equal function tests for equality to 0 when returning. It seems in commit 0d74c4 it is somehow overlooked to change this operator to reflect the actual function. Signed-off-by: Cihangir Akturk <[email protected]> Signed-off-by: Jonathan Corbet <[email protected]>
2016-12-27docs: Fix build failureJohn Brooks1-1/+1
The 80211.tmpl DocBook file was removed in commit 819bf593767c ("docs-rst: sphinxify 802.11 documentation"), but the 80211.xml target was re-added to the Makefile by commit 7ddedebb03b7 ("ALSA: doc: ReSTize writing-an-alsa-driver document"), leading to a failure when building the documentation: *** No rule to make target 'Documentation/DocBook/80211.xml', needed by 'Documentation/DocBook/80211.aux.xml'. cc: [email protected] Signed-off-by: John Brooks <[email protected]> Mea-culpa-by: Jonathan Corbet <[email protected]> Signed-off-by: Jonathan Corbet <[email protected]>
2016-12-27Merge tag 'v4.10-rc1' into docs-nextJonathan Corbet11424-224736/+700098
Linux 4.10-rc1
2016-12-27net: stmmac: fix incorrect bit set in gmac4 mdio addr registerKweh, Hock Leong1-1/+3
Fixing the gmac4 mdio write access to use MII_GMAC4_WRITE only instead of OR together with MII_WRITE. Signed-off-by: Kweh, Hock Leong <[email protected]> Acked-By: Joao Pinto <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2016-12-27r8169: add support for RTL8168 series add-on card.Chun-Hao Lin1-0/+1
This chip is the same as RTL8168, but its device id is 0x8161. Signed-off-by: Chun-Hao Lin <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2016-12-27net: xdp: remove unused bfp_warn_invalid_xdp_buffer()Jason Wang2-7/+0
After commit 73b62bd085f4737679ea9afc7867fa5f99ba7d1b ("virtio-net: remove the warning before XDP linearizing"), there's no users for bpf_warn_invalid_xdp_buffer(), so remove it. This is a revert for commit f23bc46c30ca5ef58b8549434899fcbac41b2cfc. Cc: Daniel Borkmann <[email protected]> Cc: John Fastabend <[email protected]> Signed-off-by: Jason Wang <[email protected]> Acked-by: Daniel Borkmann <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2016-12-27openvswitch: upcall: Fix vlan handling.pravin shelar2-28/+27
Networking stack accelerate vlan tag handling by keeping topmost vlan header in skb. This works as long as packet remains in OVS datapath. But during OVS upcall vlan header is pushed on to the packet. When such packet is sent back to OVS datapath, core networking stack might not handle it correctly. Following patch avoids this issue by accelerating the vlan tag during flow key extract. This simplifies datapath by bringing uniform packet processing for packets from all code paths. Fixes: 5108bbaddc ("openvswitch: add processing of L3 packets"). CC: Jarno Rajahalme <[email protected]> CC: Jiri Benc <[email protected]> Signed-off-by: Pravin B Shelar <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2016-12-27ipv4: Namespaceify tcp_tw_reuse knobHaishuang Yan4-10/+10
Different namespaces might have different requirements to reuse TIME-WAIT sockets for new connections. This might be required in cases where different namespace applications are in place which require TIME_WAIT socket connections to be reduced independently of the host. Signed-off-by: Haishuang Yan <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2016-12-27clk: renesas: r8a7796: Add MSIOF controller clocksHiromitsu Yamasaki1-0/+5
This patch adds MSIOF{0,1,2,3} clocks for R8A7796 SoC. Signed-off-by: Hiromitsu Yamasaki <[email protected]> Signed-off-by: Takeshi Kihara <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-12-27clk: renesas: r8a7796: Add CAN FD peripheral clockChris Paterson1-0/+1
Based on a patch for r8a7795 by Ramesh Shanmugasundaram. Signed-off-by: Chris Paterson <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2016-12-27clk: renesas: r8a7796: Add CANFD clockChris Paterson1-0/+1
Based on a patch for r8a7795 by Ramesh Shanmugasundaram. Signed-off-by: Chris Paterson <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
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