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2018-05-24dt-bindings: pinctrl: add external interrupt support to MT7622 pinctrlSean Wang1-0/+10
Extend the capability of MT7622 pinctrl with adding EINT so that each GPIO can be used to notify CPU when a signal state is changing on the line as an external interrupt. Signed-off-by: Sean Wang <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-24pinctrl: freescale: Switch to SPDX identifierFabio Estevam25-271/+151
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <[email protected]> Reviewed-by: Stefan Agner <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-24Merge tag 'samsung-pinctrl-4.18-2' of ↵Linus Walleij6-1017/+51
https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v4.18 1. Driver expects specific order of GPIO interrupt banks. For S5Pv220 and Exynos5410 this order was not preserved so fix and document it. 2. Remove support for Exynos5440 (tree-wide, support is dropped because there are no real users of this platform, it also did not get testing since long time). 3. Fix lost state of GPF1..5 pins on Exynos5433 during system suspend.
2018-05-24Merge tag 'sh-pfc-for-v4.18-tag2' of ↵Linus Walleij10-14/+2804
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.18 (take two) - Add support for the new R-Car E3 SoC, - Add I2C pin groups on R-Car M3-N, - Small fixes and cleanups.
2018-05-23pinctrl: samsung: Fix suspend/resume for Exynos5433 GPF1..5 banksMarek Szyprowski1-1/+1
GPF1..5 banks in Exynos5433 are located in two pinctrl devices: ALIVE and IMEM. Although they are partially located in ALIVE section, the state of their registers in IMEM section is lost after suspend/resume cycle. To properly handle such case, those banks have to be defined with standard 'exynos5433_bank_type_off' type (with PINCFG_TYPE_CON_PDN and PINCFG_TYPE_PUD_PDN register offsets). This automatically instructs the generic Samsung pinctrl suspend/resume code to save and restore state of those registers. Signed-off-by: Marek Szyprowski <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]>
2018-05-23pinctrl: sh-pfc: rcar-gen3: Fix grammar in static pin commentsGeert Uytterhoeven4-12/+12
The comment block explaining the rationale for static pins contains grammar errors. It appeared first in the pin control driver for R-Car H3 ES1.x, and spread to R-Car M3-W, H3 ES2.0, and M3-N later. Fix the grammar in all copies at once. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Niklas Söderlund <[email protected]>
2018-05-23pinctrl: sh-pfc: r8a77965: Add I2C pin supportNiklas Söderlund1-0/+77
Signed-off-by: Niklas Söderlund <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-05-23pinctrl: sh-pfc: r8a77990: Add EthernetAVB pins, groups and functionsTakeshi Kihara1-0/+90
This patch adds group and function of AVB PHY, LINK, MAGIC, MII and PTP pins for the R8A77990 SoC. Signed-off-by: Takeshi Kihara <[email protected]> Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-05-23pinctrl: sh-pfc: r8a77990: Add I2C{1,2,4,5,6,7} pins, groups and functionsTakeshi Kihara1-0/+190
This patch adds I2C{1,2,4,5,6,7} pins, groups and functions to the R8A77990 SoC. NOTE: I2C0 and I2C3 are not pin multiplexed. Signed-off-by: Takeshi Kihara <[email protected]> Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-05-23pinctrl: sh-pfc: r8a77990: Add SCIF pins, groups and functionsTakeshi Kihara1-0/+365
This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A77990 SoC. Signed-off-by: Takeshi Kihara <[email protected]> Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-05-23pinctrl: sh-pfc: r8a77990: Add bias pinconf supportTakeshi Kihara1-9/+331
This patch implements control of pull-up and pull-down. On this SoC there is no simple mapping of GP pins to bias register bits, so we need a table. Signed-off-by: Takeshi Kihara <[email protected]> Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-05-23pinctrl: sh-pfc: Initial R8A77990 PFC supportTakeshi Kihara6-0/+1742
This patch adds initial pinctrl driver to support for the R8A77990 SoC. Signed-off-by: Takeshi Kihara <[email protected]> Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-05-23pinctrl: sh-pfc: Add PORT_GP_11 helper macroTakeshi Kihara1-2/+6
This follows the style of existion PORT_GP_X macros and will be used by a follow-up patch for the r8a77990 SoC. Signed-off-by: Takeshi Kihara <[email protected]> Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-05-23pinctrl: berlin: switch to SPDX license identifierJisheng Zhang6-32/+6
Use the appropriate SPDX license identifier in the berlin pinctrl driver source file and drop the previous license text. Signed-off-by: Jisheng Zhang <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-23pinctrl: rockchip: Add set_config callback support for gpiolibShawn Lin1-0/+52
Could only support PIN_CONFIG_INPUT_DEBOUNCE now as the HW block is too simple to support others. But even wrt. debounce capability, it now could only support very limited period of time to satisfy the real usecase. But still be useful to enable the crippled HW debounce to prevent any spurious glitches from waking up the system if the gpio is conguired as wakeup interrupt source. Signed-off-by: Shawn Lin <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-23pinctrl: rockchip: Add pinctrl support for PX30David Wu2-0/+195
There are 4 banks (GPIO0 ~ GPIO3), bank0 is in PD_PMU subsystem, bank1/bank2/bank3 are in PD_BUS subsystem. Signed-off-by: David Wu <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-23pinctrl: mvebu: update use "nand" function for "rb" pinChris Packham1-1/+1
The Armada 98dx3236 SoCs don't have a different MPP sel value for nand specific pins so "dev" was technically correct. But all the other Armada SoCs use "nand" in their dts and the pin is specific to the nand interface so use "nand" for the function name. Signed-off-by: Chris Packham <[email protected]> Acked-by: Gregory CLEMENT <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-23MAINTAINERS: Add Actions Semi S900 pinctrl entriesManivannan Sadhasivam1-0/+2
Add S900 pinctrl entries under ARCH_ACTIONS Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-23pinctrl: actions: Add gpio support for Actions S900 SoCManivannan Sadhasivam4-1/+247
Add gpio support to pinctrl driver for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-23dt-bindings: pinctrl: Add gpio bindings for Actions S900 SoCManivannan Sadhasivam1-0/+16
Add gpio bindings for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-23pinctrl: pinctrl-single: Add functions to save and restore pinctrl contextKeerthy1-1/+71
This adds a pair of context save/restore functions to save/restore the state of a set of pinctrl registers. The context is lost during rtc only suspend with ddr in self-refresh on am43xx. Currently the save/restore is being done unconditionally. This will be optimized later with a pdata-quirk function which will allow is to save/restore only when doing the rtc only mode with ddr in self refresh. Signed-off-by: Keerthy <[email protected]> Acked-by: Tony Lindgren <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: nand: meson-gxl: fix missing data pinsYixun Lan1-2/+2
The data pin 0-7 of the NAND controller are actually missing from the nand pinctrl group, so we fix it here. Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions") Reported-by: Liang Yang <[email protected]> Signed-off-by: Yixun Lan <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: nand: meson-gxbb: fix missing data pinsYixun Lan1-2/+2
The data pin 0-7 of the NAND controller are actually missing from the nand pinctrl group, so we fix it here. Fixes: cd1e3b01c7d3 ("pinctrl: amlogic: gxbb: add nand pins") Reported-by: Liang Yang <[email protected]> Signed-off-by: Yixun Lan <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: qcom: Print high/low status of gpios in debugfsStephen Boyd1-2/+10
I was debugging some gpio issues and I thought that the output of gpio debugfs was telling me the high or low level of the gpios with a '1' or a '0'. We saw a line like this though: gpio93 : in 4 2mA pull down and I started to think that there may be a gas leak in the building because '4' doesn't mean high or low, and other pins said '0' or '1'. It turns out, '4' is the function selection for the pinmux of the gpio and not the value on the pin. Reading code helps decipher what debugfs is actually saying. Add support to read the input or output pin depending on how the pin is configured so we can easily see the high or low value of the pin in debugfs. Now the output looks like gpio93 : in low func4 2mA pull down which clearly shows that the pin is an input, low, with function 4 and a 2mA drive strength plus a pull down. Cc: Bjorn Andersson <[email protected]> Cc: Alexandru M Stan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: mvebu: use correct MPP sel value for dev pinsChris Packham1-10/+10
The "dev" function is selected with the value 0x4 not 0x01. Fixes: commit d7ae8f8dee7f ("pinctrl: mvebu: pinctrl driver for 98DX3236 SoC") Signed-off-by: Chris Packham <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: qcom: fix wrong pull status display for no_keeper SoCClément Péron1-2/+11
DebugFS strings about pin pull status for no_keeper SoC are wrong Fix this by adding a different string array for no_keeper SoC Signed-off-by: Clément Péron <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: tegra20: Provide CDEV1/2 clock muxesDmitry Osipenko3-12/+40
Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks. Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so that main clk-controller driver could get an actual parent clock for the CDEV1/2 clocks. Signed-off-by: Dmitry Osipenko <[email protected]> Reviewed-by: Marcel Ziswiler <[email protected]> Tested-by: Marcel Ziswiler <[email protected]> Tested-by: Marc Dietrich <[email protected]> Acked-by: Peter De Schrijver <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: sunxi: add support for H6 R_PIO pin controllerIcenowy Zheng4-0/+134
Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs, which controls the PL and PM pin banks. Add support for it. Signed-off-by: Icenowy Zheng <[email protected]> Acked-by: Maxime Ripard <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: armada-37xx: Convert to use match_string() helperAndy Shevchenko1-21/+8
The new helper returns index of the matching string in an array. We are going to use it here. Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: bcm2835: Add support for output-low output-high propertiesMatheus Castello1-0/+5
Properties to set initial value of pin output buffer. This can be useful for configure hardware in overlay files, and in early boot for checking it states in QA sanity tests. Signed-off-by: Matheus Castello <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Acked-by: Stefan Wahren <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: bcm2835: Add support for generic pinctrl bindingMatheus Castello2-37/+59
To keep driver up to date we add generic pinctrl binding support, which covers the features used in this driver and has additional node properties that this SoC has compatibility, so enabling future implementations of these properties without the need to create new node properties in the device trees. The logic of this change maintain the old brcm legacy binding support in order to keep the ABI stable. Signed-off-by: Matheus Castello <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Acked-by: Stefan Wahren <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: sh-pfc: Add r8a77470 PFC supportBiju Das5-0/+2356
Add PFC support for the R8A77470 SoC including pin groups for some on-chip devices such as SCIF and MMC. Signed-off-by: Biju Das <[email protected]> Reviewed-by: Fabrizio Castro <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functionsTakeshi Kihara1-0/+326
This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <[email protected]> Signed-off-by: Yoshihiro Kaneko <[email protected]> Reviewed-by: Simon Horman <[email protected]> Tested-by: Simon Horman <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: sh-pfc: r8a77965: Add DU RGB output pins, groups and functionsKieran Bingham1-0/+116
This patch adds pins, groups and functions for parallel RGB output signals from DU. The HDMI and TCON pins are added to separate groups. Based on a similar patch of the R8A7796 PFC driver by Niklas Söderlund <[email protected]>. Signed-off-by: Takeshi Kihara <[email protected]> [Kieran: Rebase on top of tree] Signed-off-by: Kieran Bingham <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: sh-pfc: r8a77965: Fixup incorrect SPDX identifierThomas Gleixner1-1/+1
GPL-2. is not a valid SPDX identifier. Make it GPL-2.0 Fixes: 490e687eb8b2 ("pinctrl: sh-pfc: Initial R-Car M3-N support") Signed-off-by: Thomas Gleixner <[email protected]> Cc: Jacopo Mondi <[email protected]> Cc: Rob Herring <[email protected]> Cc: Geert Uytterhoeven <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: sh-pfc: r8a77970: Fix pin I/O voltage control supportSergei Shtylyov1-8/+24
I've included the pin I/O voltage control into the R8A77970 PFC driver but it was incomplete because: - SH_PFC_PIN_CFG_IO_VOLTAGE pin flags weren't set properly; - sh_pfc_soc_info::ioctrl_regs wasn't set at all... Fixes: b92ac66a1819 ("pinctrl: sh-pfc: Add R8A77970 PFC support") Signed-off-by: Sergei Shtylyov <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: sh-pfc: r8a77980: Add pin I/O voltage control supportSergei Shtylyov1-3/+49
Add the pin I/O voltage level control support to the R8A77980 PFC driver. Loosely based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <[email protected]> Signed-off-by: Sergei Shtylyov <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16dt-bindings: pinctrl: sh-pfc: Document r8a77470 PFC supportBiju Das1-0/+1
Document PFC support for the R8A77470 SoC. Signed-off-by: Biju Das <[email protected]> Reviewed-by: Fabrizio Castro <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: sh-pfc: r8a77965: Add PWM pins, groups and functionsTakeshi Kihara1-0/+153
This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to R8A77965 SoC. Signed-off-by: Takeshi Kihara <[email protected]> Signed-off-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: sh-pfc: r8a7796: Fix comment for MSIOF3 SS2_E pinGeert Uytterhoeven1-1/+1
Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: sh-pfc: r8a7795: Fix comment for MSIOF3 SS2_E pinGeert Uytterhoeven1-1/+1
Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: sh-pfc: r8a77965: Add MSIOF pins, groups and functionsTakeshi Kihara1-0/+912
This patch adds MSIOF{0,1,2,3} pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <[email protected]> [geert: Correct MSIOF3 SS2_E comment] Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-02pinctrl: samsung: Remove support for Exynos5440Krzysztof Kozlowski3-1014/+2
The Exynos5440 is not actively developed, there are no development boards available and probably there are no real products with it. Remove wide-tree support for Exynos5440. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Chanwoo Choi <[email protected]>
2018-05-02pinctrl: imx: use seq_puts() instead of seq_printf()Dong Aisheng1-2/+2
For a constant format without additional arguments, use seq_puts() instead of seq_printf(). Also, it fixes the following checkpatch warning. WARNING: Prefer seq_puts to seq_printf + seq_printf(s, "N/A"); WARNING: Prefer seq_puts to seq_printf + seq_printf(s, "\n"); Cc: Linus Walleij <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Stefan Agner <[email protected]> Cc: Pengutronix Kernel Team <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-02pinctrl: pinctrl-imx: improve the code comments of PIN_FUNC_IDDong Aisheng1-4/+11
The current code comments of PIN_FUNC_ID actually is not true for SHARE_MUX_CONF_REG case which should be a 4 u32 PIN_FUNC_ID. Fix the comments and re-org it a bit for better extendibility as we may add a different size for SCU based PIN_FUNC_ID later. Cc: Linus Walleij <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Stefan Agner <[email protected]> Cc: Pengutronix Kernel Team <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-02pinctrl: imx: fix unsigned check if nfuncs with less than or equal zeroDong Aisheng1-1/+1
The unsigned integer nfuncs is being error checked with a value less or equal to zero; this is always false if of_get_child_count returns a -ve for an error condition since nfuncs is not signed. Fix this by making variables nfuncs and i signed integers. Detected with Coccinelle: drivers/pinctrl/freescale/pinctrl-imx.c:620:6-12: WARNING: Unsigned expression compared with zero: nfuncs <= 0 Cc: Linus Walleij <[email protected]> Reported-by: Colin Ian King <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-02pinctrl: uniphier: add LD11 MPEG2-TS I/O pin-mux settingsKatsuhiro Suzuki1-0/+49
The MPEG2-TS input/output core both accepts serial TS and parallel TS. The serial TS interface uses following pins: hscin0_s : HS0DOUT[0-3] hscin1_s : HS0DOUT[4-7] hscin2_s : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN0 hscout0_s: HS0DOUT[0-3] hscout1_s: HS0DOUT[4-7] And the parallel TS interface uses following pins: hscin0_p : HS0BCLKIN, HS0SYNCIN, HS0VALIN, HS0DIN[0-7] hscin1_p : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN[0-7] hscout0_p: HS0BCLKOUT, HS0SYNCOUT, HS0VALOUT, HS0DOUT[0-7] Signed-off-by: Katsuhiro Suzuki <[email protected]> Acked-by: Masahiro Yamada <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-02pinctrl: uniphier: add LD20 MPEG2-TS I/O pin-mux settingsKatsuhiro Suzuki1-0/+54
The MPEG2-TS input/output core both accepts serial TS and parallel TS. The serial TS interface uses following pins: hscin0_s : HS0DOUT[0-3] hscin1_s : HS0DOUT[4-7] hscin2_s : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN0 hscin3_s : HS1DIN[2-5] hscout0_s: HS0DOUT[0-3] hscout1_s: HS0DOUT[4-7] And the parallel TS interface uses following pins: hscin0_p : HS0BCLKIN, HS0SYNCIN, HS0VALIN, HS0DIN[0-7] hscin1_p : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN[0-7] hscout0_p: HS0BCLKOUT, HS0SYNCOUT, HS0VALOUT, HS0DOUT[0-7] Signed-off-by: Katsuhiro Suzuki <[email protected]> Acked-by: Masahiro Yamada <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-02pinctrl: actions: Fix Kconfig dependency and help textManivannan Sadhasivam1-2/+4
1. Fix Kconfig dependency for Actions Semi S900 pinctrl driver which generates below warning in x86: WARNING: unmet direct dependencies detected for PINCTRL_OWL Depends on [n]: PINCTRL [=y] && (ARCH_ACTIONS || COMPILE_TEST [=n]) && OF [=n] Selected by [y]: - PINCTRL_S900 [=y] && PINCTRL [=y] 2. Add help text for OWL pinctrl driver Signed-off-by: Manivannan Sadhasivam <[email protected]> Reported-by: Randy Dunlap <[email protected]> Tested-by: Randy Dunlap <[email protected]> Acked-by: Randy Dunlap <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-02pinctrl: actions: fix missing break in PIN_CONFIG_DRIVE_STRENGTH case.Colin Ian King1-0/+2
There is a missing break in case PIN_CONFIG_DRIVE_STRENGTH leading to a fall-through to the PIN_CONFIG_SLEW_RATE case that performs different checks against *arg. This looks like an unintentional missing break so add in the break. Detected by CoverityScan, CID#1468456, 1468459 ("Missing break in switch") Fixes: 513d7a2f7e0f ("pinctrl: actions: Add Actions S900 pinctrl driver") Signed-off-by: Colin Ian King <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
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