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2014-12-02nouveau: move the hotplug ignore to correct place.Dave Airlie1-1/+1
Introduced in b440bde74f, however it was added to the wrong function in nouveau. https://bugzilla.kernel.org/show_bug.cgi?id=86011 Cc: Bjorn Helgaas <[email protected]> CC: [email protected] # v3.15+ Signed-off-by: Dave Airlie <[email protected]>
2014-12-02Merge branch 'linux-3.19' of ↵Dave Airlie126-2636/+6261
git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next - Tegra K1 voltage support, and coherency improvements - GM204 support (modesetting, still waiting on NVIDIA for signed fw to proceed further), and a lot of bios/i2c/devinit adjustments needed to support it - GT21x memory reclocking work - Various other bits and pieces, most of which are prep-work for a couple of bigger projects I didn't get finished in time * 'linux-3.19' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (73 commits) drm/nv50/kms: drop requirement that framebuffer bos be contig up-front drm/nv50/kms: directly use cursor image from userspace buffer drm/nouveau/kms: when pinning display-related buffers, force contig vram drm/nouveau: teach nouveau_bo_pin() how to force a contig vram allocation drm/nouveau/volt: add support for GK20A drm/nouveau/platform: add GPU speedo information to nouveau platform drm/nouveau/volt: allow non-bios voltage scaling drm/gf100-/gr: return non-fatal error code when fw not present drm/nouveau/devinit: bump priv ring timeouts before executing scripts drm/nouveau/bios: translate ramcfg strap through M0203 drm/nouveau/fb: make use of M0203 routines for ram type determination drm/nouveau/bios: add parsing of BIT M(v2) +0x03 table drm/nouveau/core: allow vbios parsing without knowing chipset type drm/nouveau/lib: add null backend drm/nouveau/device: store revision drm/nouveau/core: add some forgotten subdevs to disable mask drm/gk20a/clk: fix max VCO value drm/nouveau: we need pin_refcnt for nouveau_bo_placement_set() drm/nv50-/kms: add some evo tracing ability for debugging drm/nv50/kms: use sclass() instead of trial-and-error ...
2014-12-02drm/nv50/kms: drop requirement that framebuffer bos be contig up-frontBen Skeggs1-5/+0
We'll move them at pin() time if necessary. Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nv50/kms: directly use cursor image from userspace bufferBen Skeggs2-49/+32
Preparation for transition to planes, which use framebuffers for the cursor image. We've always done copies from the userspace buffer up until now for legacy reasons, there's no good reason to do so on the chipsets this code covers. Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/kms: when pinning display-related buffers, force contig vramBen Skeggs2-7/+7
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: teach nouveau_bo_pin() how to force a contig vram allocationBen Skeggs13-27/+52
We have the ability to move buffers around in the kernel if necessary, and should probably use it rather than failing if userspace passes us a non-contig buffer for a plane. The NOUVEAU_GEM_TILE_NONCONTIG flag from userspace will become a mere initial placement hint once all the relevant paths have been updated. Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/volt: add support for GK20AVince Hsu6-0/+218
The voltage value are calculated by the hardware characterized result. Signed-off-by: Vince Hsu <[email protected]> Reviewed-by: Alexandre Courbot <[email protected]> Acked-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/platform: add GPU speedo information to nouveau platformVince Hsu2-0/+4
For GK20A we need the GPU speedo value to calculate voltage levels. Signed-off-by: Vince Hsu <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/volt: allow non-bios voltage scalingVince Hsu1-29/+38
Move the vbios parsing out of init() and call it conditionally if the platform has a vbios. Non-vbios platforms can use the ctor() to init the data structures. Signed-off-by: Vince Hsu <[email protected]> Acked-by: Alexandre Courbot <[email protected]> Acked-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/gf100-/gr: return non-fatal error code when fw not presentBen Skeggs1-1/+1
This allows the module to load without acceleration. Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/devinit: bump priv ring timeouts before executing scriptsBen Skeggs2-1/+10
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: translate ramcfg strap through M0203Ben Skeggs1-1/+12
A machine has been spotted where the ramcfg strap is "8", and the ramcfg xlat table goes 0-7,0-7, resulting in us selecting config 0 for memory items. On this particular system, config "8" is available and supposed to be used. It appears that starting from GT21x (where Mv2 appears), we're supposed to use the value in this table instead. One concern here is that not all the places we currently use ramcfg xlat are supposed to be treated the same now. The strap xlat table wasn't removed from the vbios either, presumably for some kind of good reason. Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/fb: make use of M0203 routines for ram type determinationBen Skeggs1-22/+15
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: add parsing of BIT M(v2) +0x03 tableBen Skeggs3-0/+161
We only support one kind of matching here (ramcfg strap), but it appears alternate methods are possible. I wrote a tool to scan our vbios repo for other types, but did not see any used. Hopefully this means there aren't any in the wild that will now break. Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/core: allow vbios parsing without knowing chipset typeBen Skeggs1-0/+5
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/lib: add null backendBen Skeggs2-0/+2
For the moment, just used to speed up vbios-only testing. Have some ideas for extending in the future. Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/device: store revisionBen Skeggs2-1/+4
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/core: add some forgotten subdevs to disable maskBen Skeggs2-0/+3
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/gk20a/clk: fix max VCO valueAlexandre Courbot1-1/+1
For some reason max_vco was set to a lower value that it can support, which prevented some clock states to be applied. Fix this by setting it to the same value as downstream. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: we need pin_refcnt for nouveau_bo_placement_set()Ben Skeggs1-5/+9
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nv50-/kms: add some evo tracing ability for debuggingBen Skeggs1-0/+13
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nv50/kms: use sclass() instead of trial-and-errorBen Skeggs1-6/+20
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nv50/kms: remove a couple of cursor-related stub functionsBen Skeggs2-12/+2
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: fix pin refcnt leak in failure pathBen Skeggs1-12/+12
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: synchronize BOs when requiredAlexandre Courbot3-0/+56
On architectures for which access to GPU memory is non-coherent, caches need to be flushed and invalidated explicitly when BO control changes between CPU and GPU. This patch adds buffer synchronization functions which invokes the correct API (PCI or DMA) to ensure synchronization is effective. Based on the TTM DMA cache helper patches by Lucas Stach. Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: allocate GPFIFOs and fences coherentlyAlexandre Courbot2-3/+3
Specify TTM_PL_FLAG_UNCACHED when allocating GPFIFOs and fences to allow them to be safely accessed by the kernel without being synced on non-coherent architectures. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: implement explicitly coherent BOsAlexandre Courbot2-8/+73
Allow nouveau_bo_new() to recognize the TTM_PL_FLAG_UNCACHED flag, which means that we want the allocated BO to be perfectly coherent between the CPU and GPU. This is useful on non-coherent architectures for which we do not want to manually sync some rarely-accessed buffers: typically, fences and pushbuffers. A TTM BO allocated with the TTM_PL_FLAG_UNCACHED on a non-coherent architecture will be populated using the DMA API, and accesses to it performed using the coherent mapping performed by dma_alloc_coherent(). Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: introduce nv_device_is_cpu_coherent()Alexandre Courbot1-0/+6
Add a function allowing us to know whether a device is CPU-coherent, i.e. accesses performed by the CPU on GPU-mapped buffers will be immediately visible on the GPU side and vice-versa. For now, a device is considered to be coherent if it uses the PCI bus on a non-ARM architecture. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: warn when moving a pinned objectAlexandre Courbot1-2/+9
Pinned BOs are supposed to remain in their current location until unpinned. Display a warning for the supposedly-erroneous case where we are trying to move such objects. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/disp: clear notify intr status when enabling, to prevent racesBen Skeggs2-0/+4
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nv50-/disp: rename class members to match nvidia channel namesBen Skeggs11-206/+206
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/core: remove some dead code that got forgottenBen Skeggs3-135/+0
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/pwr/fuc: Fix thinko in nouveau_memx_wait()Roy Spliet1-1/+1
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nva3/clock: Allow user reclockingRoy Spliet1-1/+1
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/fb/ramnva3: Reclocking script for GDDR3Roy Spliet2-10/+92
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/fb/ramnva3: Reclocking script for DDR2Roy Spliet1-15/+42
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/fb/ramnva3: Reclocking script for DDR3Roy Spliet3-75/+219
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/fb/ramnva3: Ressurect timing calculation codeRoy Spliet3-14/+132
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/fb/ramnva3: Link training for DDR3Roy Spliet10-1415/+2259
V2: fix whitespace errors in memx.fuc Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/fb/gddr3: Generate MR valuesRoy Spliet3-0/+119
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios/ramcfg: 10_02_40 -> DLLoffRoy Spliet4-4/+4
Signed-off-by: Roy Spliet <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: move the (far too many...) different s/r paths to the same placeBen Skeggs2-138/+144
No code changes. Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/gk104-/fifo: handle copy engine class errorsBen Skeggs1-6/+42
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: stop after NV+NPDS+ISBN imageBen Skeggs1-4/+9
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/bios: add some more signatures as seen on my gtx660Ben Skeggs2-0/+2
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau: add support for gm204Ben Skeggs3-11/+16
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/nouveau/device: recognise GM204Ben Skeggs2-1/+45
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/gm204/disp: some magic that fixes bringup of uninitialised outputsBen Skeggs5-3/+24
Probably missing something here, doesn't make a lot of sense to write or+link data into a register whose offset is calculated by the same or+link info.. This is the all I've witnessed the binary driver and vbios doing so far, so it'll do. Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/gm204/disp: initial supportBen Skeggs8-1/+255
Signed-off-by: Ben Skeggs <[email protected]>
2014-12-02drm/gf110-/disp: magic that might help some tmds issuesBen Skeggs1-2/+10
The binary driver has been doing this since GF119, and we've somehow gotten away with it. But, TMDS that hasn't been initialised already by the x86 vbios code is distorted without it on GM204. Signed-off-by: Ben Skeggs <[email protected]>
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