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2024-03-02clk: qcom: camcc-sc8280xp: fix terminating of frequency table arraysGabor Juhos1-0/+21
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Only compile tested. Fixes: ff93872a9c61 ("clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCC") Signed-off-by: Gabor Juhos <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-03-02clk: qcom: gcc-ipq9574: fix terminating of frequency table arraysGabor Juhos1-0/+1
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Only compile tested. Fixes: d75b82cff488 ("clk: qcom: Add Global Clock Controller driver for IPQ9574") Signed-off-by: Gabor Juhos <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-03-02clk: qcom: gcc-ipq8074: fix terminating of frequency table arraysGabor Juhos1-0/+2
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Only compile tested. Fixes: 9607f6224b39 ("clk: qcom: ipq8074: add PCIE, USB and SDCC clocks") Signed-off-by: Gabor Juhos <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-03-02clk: qcom: gcc-ipq6018: fix terminating of frequency table arraysGabor Juhos1-0/+2
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Only compile tested. Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support") Signed-off-by: Gabor Juhos <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-03-02clk: qcom: gcc-ipq5018: fix terminating of frequency table arraysGabor Juhos1-0/+3
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by: Gabor Juhos <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-16clk: qcom: dispcc-sdm845: Adjust internal GDSC wait timesKonrad Dybcio1-0/+2
SDM845 downstream uses non-default values for GDSC internal waits. Program them accordingly to avoid surprises. Fixes: 81351776c9fb ("clk: qcom: Add display clock controller driver for SDM845") Signed-off-by: Konrad Dybcio <[email protected]> Tested-by: Caleb Connolly <[email protected]> # OnePlus 6 Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-16dt-bindings: clk: qcom: drop the SC7180 Modem subsystem clock controllerDmitry Baryshkov1-61/+0
This clock controller has never been used in the DT files merged to the kernel. According to Sibi, it only worked on the pre-production devices. For the production devices this functionality has been moved to the firmware. Drop the bindings now after dropping the driver itself. Cc: Sibi Sankar <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-16clk: qcom: drop the SC7180 Modem subsystem clock driverDmitry Baryshkov3-151/+0
This driver has never been used in the DT files merged to the kernel. According to Sibi, it only worked on the pre-production devices. For the production devices this functionality has been moved to the firmware. Drop the driver to remove possible confusion. Cc: Sibi Sankar <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-14clk: qcom: Use qcom_branch_set_clk_en()Konrad Dybcio38-294/+180
Instead of magically poking at the bit0 of branch clocks' CBCR, use the newly introduced helper. Reviewed-by: Bryan O'Donoghue <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-14clk: qcom: branch: Add a helper for setting the enable bitKonrad Dybcio1-0/+6
We hardcode some clocks to be always-on, as they're essential to the functioning of the SoC / some peripherals. Add a helper to do so to make the writes less magic. Reviewed-by: Johan Hovold <[email protected]> Reviewed-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: dispcc-sm8250: Make clk_init_data and pll_vco constSatya Priya Kakitapalli1-60/+58
The clk_init_data and pll_vco structures are never modified, make them const. Signed-off-by: Satya Priya Kakitapalli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: gcc-sc8180x: Add missing UFS QREF clocksManivannan Sadhasivam1-0/+28
Add missing QREF clocks for UFS MEM and UFS CARD controllers. Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x") Acked-by: Konrad Dybcio <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07Merge branch '[email protected]' into ↵Bjorn Andersson1-0/+2
clk-for-6.9 Merge the two SC8180X reset defines through a topic branch, to allow them being picked up in the DeviceTree source tree as well.
2024-02-07clk: qcom: gcc-msm8953: add more resetsVladimir Lypak1-0/+4
Add new entries in the gcc driver for some more resets found on MSM8953. Signed-off-by: Vladimir Lypak <[email protected]> [luca: expand commit message, move entry, add more entries] Signed-off-by: Luca Weiss <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07Merge branch '[email protected]' into ↵Bjorn Andersson1-0/+4
clk-for-6.9 Merge MSM8953 GCC DeviceTree binding update through topic branch, to allow it to be merged into DeviceTree source tree as well.
2024-02-07clk: qcom: videocc-*: switch to module_platform_driverDmitry Baryshkov7-77/+7
There is no need to register video clock controllers during subsys init calls. Use module_platform_driver() instead. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: gpucc-*: switch to module_platform_driverDmitry Baryshkov8-88/+8
There is no need to register GPU clock controllers during subsys init calls. Use module_platform_driver() instead. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: dispcc-*: switch to module_platform_driverDmitry Baryshkov12-132/+12
There is no need to register display clock controllers during subsys init calls. Use module_platform_driver() instead. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: camcc-*: switch to module_platform_driverDmitry Baryshkov4-44/+4
There is no need to register camera clock controllers during subsys init calls. Use module_platform_driver() instead. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: videocc-sm8550: Set delay for Venus CLK resetsKonrad Dybcio1-2/+2
Some Venus resets may require more time when toggling. Describe that. The value for SM8550 is known and extracted from the msm-5.15 driver. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: videocc-sm8450: Set delay for Venus CLK resetsKonrad Dybcio1-2/+2
Some Venus resets may require more time when toggling. Describe that. The value is known for SM8450, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/d0730ea5867264ee50b793f6700eb6a376ddcbbb Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: videocc-sm8350: Set delay for Venus CLK resetsKonrad Dybcio1-2/+2
Some Venus resets may require more time when toggling. Describe that. The value is known for SM8350, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: videocc-sm8250: Set delay for Venus CLK resetsKonrad Dybcio1-2/+2
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.14/19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: videocc-sm8150: Set delay for Venus CLK resetsKonrad Dybcio1-1/+1
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.14/19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: gcc-sm8650: Set delay for Venus CLK resetsKonrad Dybcio1-2/+2
Some Venus resets may require more time when toggling. Describe that. The Venus hw on 8650 is similar to the one on 8550, follow its requirements. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: gcc-sm8550: Set delay for Venus CLK resetsKonrad Dybcio1-2/+2
Some Venus resets may require more time when toggling. Describe that. The value for SM8550 is known and extracted from the msm-5.15 driver. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: gcc-sm8450: Set delay for Venus CLK resetsKonrad Dybcio1-2/+2
Some Venus resets may require more time when toggling. Describe that. The value is known for SM8450, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/d0730ea5867264ee50b793f6700eb6a376ddcbbb Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: gcc-sm8350: Set delay for Venus CLK resetsKonrad Dybcio1-2/+2
Some Venus resets may require more time when toggling. Describe that. The value is known for SM8350, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: gcc-sm8250: Set delay for Venus CLK resetsKonrad Dybcio1-2/+2
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: gcc-sm7150: Set delay for Venus CLK resetsKonrad Dybcio1-1/+1
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.14/19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: gcc-sm4450: Set delay for Venus CLK resetsKonrad Dybcio1-2/+2
Some Venus resets may require more time when toggling. Describe that. The value was obtained on a best-guess basis: msm-5.4 being the base kernel for this SoC and 4450 being somewhat close to 8350 which is known to require a higher delay [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: gcc-sc8280xp: Set delay for Venus CLK resetsKonrad Dybcio1-2/+2
Some Venus resets may require more time when toggling. Describe that. The value was obtained on a best-guess basis: msm-5.4 being the base kernel for this SoC and 8280 being generally close to 8350 which is known to require a higher delay [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: gcc-sc8180x: Set delay for Venus CLK resetsKonrad Dybcio1-3/+3
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: gcc-sa8775p: Set delay for Venus CLK resetsKonrad Dybcio1-2/+2
Some Venus resets may require more time when toggling. Describe that. The value was obtained on a best-guess basis: msm-5.4 being the base kernel for this SoC and 8775 being generally close to 8350 which is known to require a higher delay [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-07clk: qcom: reset: Ensure write completion on reset de/assertionKonrad Dybcio1-1/+6
Trying to toggle the resets in a rapid fashion can lead to the changes not actually arriving at the clock controller block when we expect them to. This was observed at least on SM8250. Read back the value after regmap_update_bits to ensure write completion. Fixes: b36ba30c8ac6 ("clk: qcom: Add reset controller support") Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-06dt-bindings: clock: qcom: Add missing UFS QREF clocksManivannan Sadhasivam1-0/+2
Add missing QREF clocks for UFS MEM and UFS CARD controllers. Fixes: 0fadcdfdcf57 ("dt-bindings: clock: Add SC8180x GCC binding") Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-06dt-bindings: clock: gcc-msm8953: add more resetsVladimir Lypak1-0/+4
Add new defines for some more BCRs found on MSM8953. Signed-off-by: Vladimir Lypak <[email protected]> [luca: expand commit message, add more resets] Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Luca Weiss <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-06clk: qcom: reset: Commonize the de/assert functionsKonrad Dybcio1-13/+9
They do the same thing, except the last argument of the last function call differs. Commonize them. Reviewed-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-06clk: qcom: reset: Increase max reset delayKonrad Dybcio1-1/+1
u8 limits us to 255 microseconds of delay. Promote the delay variable to u16 to hold bigger values. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-06clk: qcom: Add camcc clock driver for x1e80100Rajendra Nayak3-0/+2495
Add the camcc clock driver for x1e80100 Signed-off-by: Rajendra Nayak <[email protected]> Reviewed-by: Bryan O'Donoghue <[email protected]> Tested-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-10-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-06clk: qcom: Add TCSR clock driver for x1e80100Abel Vesa3-0/+294
The TCSR clock controller found on X1E80100 provides refclks for PCIE, USB and UFS. Add clock driver for it. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-06clk: qcom: Add GPU clock driver for x1e80100Rajendra Nayak3-0/+666
Add Graphics Clock Controller (GPUCC) support for X1E80100 platform. Signed-off-by: Rajendra Nayak <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-06clk: qcom: Add dispcc clock driver for x1e80100Rajendra Nayak3-0/+1729
Add the dispcc clock driver for x1e80100. Signed-off-by: Rajendra Nayak <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-06clk: qcom: clk-alpha-pll: Add support for zonda ole pll configureRajendra Nayak2-0/+20
Zonda ole pll has as extra PLL_OFF_CONFIG_CTL_U2 register, hence add support for it. Signed-off-by: Rajendra Nayak <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-06Merge branch ↵Bjorn Andersson10-107/+327
'[email protected]' into clk-for-6.9 Merge X1E clock bindings through a topic branch, to make the defines available for inclusion in DeviceTree branches as well.
2024-02-06dt-bindings: clock: qcom: Document the X1E80100 Camera Clock ControllerRajendra Nayak2-0/+137
Add bindings documentation for the X1E80100 Camera Clock Controller. Signed-off-by: Rajendra Nayak <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-06dt-bindings: clock: qcom: Document the X1E80100 TCSR Clock ControllerAbel Vesa2-0/+24
Add bindings documentation for the X1E80100 TCSR Clock Controller. Co-developed-by: Rajendra Nayak <[email protected]> Signed-off-by: Rajendra Nayak <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-06dt-bindings: clock: qcom: Document the X1E80100 GPU Clock ControllerRajendra Nayak3-0/+62
Add bindings documentation for the X1E80100 Graphics Clock Controller. Signed-off-by: Rajendra Nayak <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-06dt-bindings: clock: qcom: Document the X1E80100 Display Clock ControllerRajendra Nayak2-0/+100
Add bindings documentation for the X1E80100 Display Clock Controller. Signed-off-by: Rajendra Nayak <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2024-02-06dt-bindings: clock: Drop the SM8650 DISPCC dedicated schemaAbel Vesa2-107/+4
The block is the same between these platforms, at least from devicetree point of view. So drop the dedicated schema and use the SM8550 one instead. Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
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