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2017-09-26drm/amd/powerplay: delete SMUM_FIELD_MASKRex Zhu1-2/+2
repeated defining in hwmgr.h Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: delete SMUM_WAIT_INDIRECT_FIELDRex Zhu3-13/+2
repeated defining in hwmgr.h use PHM_WAIT_INDIRECT_FIELD instand. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: delete SMUM_READ_FIELDRex Zhu4-7/+5
repeated defining in hwmgr.h Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: delete SMUM_SET_FIELDRex Zhu2-11/+6
repeated defining in hwmgr.h Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: delete SMUM_READ_VFPF_INDIRECT_FIELDRex Zhu6-14/+9
repeated defining in hwmgr.h Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: delete SMUM_WRITE_VFPF_INDIRECT_FIELDRex Zhu4-29/+23
repeated defining in hwmgr.h Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: delete SMUM_WRITE_FIELDRex Zhu4-11/+8
the macro is as same as PHM_WRITE_FIELD Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: delete SMU_WRITE_INDIRECT_FIELDRex Zhu3-21/+6
the macro is as same as PHM_WRITE_INDIRECT_FIELD Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: move macros to hwmgr.hRex Zhu6-22/+22
the macro is not relevant to SMU, so rename SMU_WAIT_FIELD_UNEQUAL to PHM_WAIT_FIELD_UNEQUAL and move to hwmgr.h Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: move PHM_WAIT_VFPF_INDIRECT_FIELD to hwmgr.hRex Zhu6-23/+25
the macro is not relevant to SMU, so move to hwmgr.h and rename to PHM_WAIT_VFPF_INDIRECT_FIELD Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: move SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL to hwmgr.hRex Zhu5-18/+22
the macro is not relevant to SMU, so move to hwmgr.h and rename to PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: move SMUM_WAIT_INDIRECT_FIELD_UNEQUAL to hwmgr.hRex Zhu4-12/+16
the macro is not relevent to SMU, so move to hwmgr.h and rename to PHM_WAIT_INDIRECT_FIELD_UNEQUAL Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: add new helper functions in hwmgr.hRex Zhu5-9/+50
Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: use SMU_IND_INDEX/DATA_11 pairRex Zhu2-3/+3
in VFPF macros to support virtualization Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: refine powerplay code.Rex Zhu22-425/+339
delete struct smumgr, put smu backend function table in struct hwmgr Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: delete dead code in hwmgr.hRex Zhu1-11/+0
Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: refine interface in struct pp_smumgr_funcRex Zhu32-1248/+1225
unify to use struct hwmgr as function parameter in smumgr. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu: simplify pinning into visible VRAMChristian König1-15/+8
Just set the CPU access required flag when we pin it. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu:fix firmware memoryleak(v2)Monk Liu6-0/+37
this fix memory leak due to request_firmware after driver unloaded v2: release gmc firmware for gmc6/7/8 as well Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu:fix uvd ring fini routine(v2)Monk Liu1-0/+4
fix missing finish uvd enc_ring. v2: since the adev pointer check in already in ring_fini so drop the check outsider Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu/sriov:alloc KIQ MQD in VRAM(v2)Monk Liu1-1/+6
this way after KIQ MQD released in drv unloading, CPC can still let KIQ access this MQD thus RLCV SAVE_VF will not fail v2: always use VRAM domain for KIQ MQD no matter BM or SRIOV Signed-off-by: Monk Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu:unmap KCQ in gfx hw_fini(v2)Monk Liu2-0/+115
v2: move kcq_disable out of SRIOV, make it genearal Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu:halt when vm faultMonk Liu2-0/+13
only with this way we can debug the VMC page fault issue Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu: Add copy_pte_num_dw member in amdgpu_vm_pte_funcsYong Zhao7-1/+15
Use it to replace the hard coded value in amdgpu_vm_bo_update_mapping(). Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu: Fix a bug in amdgpu_fill_buffer()Yong Zhao8-6/+30
When max_bytes is not 8 bytes aligned and bo size is larger than max_bytes, the last 8 bytes in a ttm node may be left unchanged. For example, on pre SDMA 4.0, max_bytes = 0x1fffff, and the bo size is 0x200000, the problem will happen. In order to fix the problem, we separately store the max nums of PTEs/PDEs a single operation can set in amdgpu_vm_pte_funcs structure, rather than inferring it from bytes limit of SDMA constant fill, i.e. fill_max_bytes. Together with the fix, we replace the hard code value "10" in amdgpu_vm_bo_update_mapping() with the corresponding values from structure amdgpu_vm_pte_funcs. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu: Correct bytes limit for SDMA 3.0 copy and fillYong Zhao1-2/+2
Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu: use 2MB fragment size for GFX6,7 and 8Christian König3-3/+3
Use 2MB fragment size by default for older hardware generations as well. Signed-off-by: Christian König <[email protected]> Acked-by: John Bridgman <[email protected]> Reviewed-by: Roger He <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu: Fix driver reloading failureXiangliang.Yu1-0/+2
SRIOV doesn't implement PMC capability of PCIe, so it can't update power state by reading PMC register. Currently, amdgpu driver doesn't disable pci device when removing driver, the enable_cnt of pci device will not be decrease to 0. When reloading driver, pci_enable_device will do nothing as enable_cnt is not zero. And power state will not be updated as PMC is not support. So current_state of pci device is not D0 state and pci_enable_msi return fail. Add pci_disable_device when remmoving driver to fix the issue. Signed-off-by: Xiangliang.Yu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: refine phm_register_thermal_interrupt interfaceRex Zhu1-3/+3
currently, not all asics implement this callback function so not return error to avoid powerplay initialize failed in those asices Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/amdgpu: add vega10/raven mmhub/athub golden settingsEvan Quan1-0/+23
Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: change alert temperature rangeEric Huang1-2/+2
Change to more meaningful range that triggers thermal interrupts. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: implement register thermal interrupt for Vega10Eric Huang1-0/+33
Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/powerplay: add register thermal interrupt in hwmgr_hw_initEric Huang2-1/+80
Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu: add cgs query info of pci bus devfnEric Huang2-0/+4
Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/amdgpu: Partial revert of iova debugfsTom St Denis1-77/+13
We discovered that on some devices even with iommu enabled you can access all of system memory through the iommu translation. Therefore, we revert the read method to the translation only service and drop the write method completely. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Christan König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/amgpu: update vega10 sdma golden settingEvan Quan1-1/+1
Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amd/amgpu: update raven sdma golden settingEvan Quan1-1/+1
Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu/sriov:fix memory leak after gpu resetMonk Liu2-32/+35
GPU reset will require all hw doing hw_init thus ucode_init_bo will be invoked again, which lead to memory leak skip the fw_buf allocation during sriov gpu reset to avoid memory leak. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu:make ctx_add_fence interruptible(v2)Monk Liu3-9/+23
otherwise a gpu hang will make application couldn't be killed under timedout=0 mode v2: Fix memoryleak job/job->s_fence issue unlock mn remove the ERROR msg after waiting being interrupted Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu/sriov:init csb for gfxv9Monk Liu1-1/+3
RLC need CSB registers initiated under SRIOV during world switch otherwise the clear state buffer behav will not be recovered to current VF scheme after switch back Signed-off-by: Monk Liu <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu/sriov:increate mailbox polling timeoutHorace Chen2-2/+2
increase timeout to 12 seconds,because there may have multiple FLR waiting for done, the waiting time of events may be long, increase to 12s to reduce timeout failure. Signed-off-by: Horace Chen <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu/sriov:fix page fault issue of driver unloadMonk Liu3-3/+3
bo_free on csa is too late to put in amdgpu_fini because that time ttm is already finished, Move it earlier to avoid the page fault. Signed-off-by: Monk Liu <[email protected]> Signed-off-by: Horace Chen <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu:use formal register to trigger hdp invalidateMonk Liu4-4/+4
Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu:hdp flush should be put it initializedMonk Liu1-6/+6
Signed-off-by: Monk Liu <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu:insert TMZ_BEGINMonk Liu1-6/+8
FRAME_CONTROL(begin) is needed for vega10 due to ucode logic change, it can fix some CTS random fail under gfx preemption enabled mode. Signed-off-by: Monk Liu <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu/sriov:don't load psp fw during gpu resetMonk Liu1-6/+9
At least for SRIOV we found reload PSP fw during gpu reset cause PSP hang. Signed-off-by: Monk Liu <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu/sriov:move in_reset to adev and renameMonk Liu4-9/+9
currently in_reset is only used in sriov gpu reset, and it will be used for other non-gfx hw component later, like PSP, so move it from gfx to adev and rename to in_sriov_reset make more sense. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu:no kiq in IHMonk Liu1-2/+2
Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu/sriov:fix missing error handlingMonk Liu1-1/+4
Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu: Add GPU reset functionality for Vega10Ken Wang8-15/+83
V2 Signed-off-by: Ken Wang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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